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5G-ready jitter attenuators enhances system reliability and performance

Technology Cover
Post Date: 2019-06-30, Silicon Labs
Silicon Labs has expanded its Si539x jitter attenuator family with new device options that provide fully integrated references, improving system reliability and performance, while simplifying PCB layout in high-speed network designs. The new jitter attenuator is specifically designed to meet the key reference clock requirements of 100/200/400/600 / 800G designs and can provide more than 40% margin for the strict jitter requirements of 56G PAM-4 SerDes that meet the following conditions: : The most advanced Ethernet switch SoC, PHY, FPGA and ASIC, while providing future-oriented solutions for emerging 112G SerDes designs. Network equipment providers are racing to develop higher-speed, higher-capacity devices that can handle 5G wireless traffic. This shift is driving the need for high-performance timing solutions for fronthaul / backhaul, metro / core and data center applications, "said James Wilson, general manager of timing products at Silicon Labs. FPGAs and PHYs with integrated 56 Gbps SerDes can be implemented Higher-capacity 100/200/400/600 / 800G fiber and Ethernet line cards, but face increasingly complex circuit board design and layout challenges. By integrating references into Silicon Labs' latest Si539x jitter attenuator, we Are helping to simplify the industry's migration to high port count, high capacity 100/200/400/600 / 800G designs. "

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