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Teledyne e2v: Immediately improves dynamic performance of wideband ADCs by ~10 dBFS with spurious suppression IP

Technology Cover
Post Date: 2022-06-22, Teledyne LeCroy

The new EV12AQ600/605-ADX4 device options have an integrated ADX4 license key to improve dynamic performance at peak operation up to 6.4 GS/s (single-channel mode).

ADX4 - Xilinx Kintex® Ultrascale FPGA-compatible post-processing algorithm provides up to 10 dBFS of SFDR dynamic spurious suppression and close to 1 significant bit of additional resolution in wideband applications.

Time interleaving, while providing a conceptually well-understood sample rate boost, is difficult to achieve at extended resolutions and wide bandwidths.

Provides immediate, design-free dynamic performance enhancement for EV12AQ600/5

Grenoble, France – Media OutReach announces the upcoming EV12AQ600/5 option with an integrated license key to directly use the new ADX4 post-processing algorithm developed by SP Devices, a Teledyne Group company. The ADX4 Spurious Suppression IP dynamically suppresses spurious frequency components caused by gain, offset, and phase mismatches between the four ADC cores. Time interleaving is a reliable architectural approach to increasing ADC sampling rates. However, at resolutions above 10 bits and in wideband applications, it is very challenging to calibrate to avoid spectral distortion.

For the EV12AQ600/5, time interleaving of the four cores increases the sampling rate from 1.6 to 6.4 GS/s. Mismatch errors between ADC cores reduce spurious-free performance. The ADX4 provides up to 10 dB of spurious-free dynamic range (SFDR) boost. This improvement is especially noticeable in broadband applications because it does not require hardware design changes. Users can easily program the ADX4 code module into the post-processing FPGA, even on the job site.

About ADC time interleaving

High-resolution data converters are rapidly evolving to achieve wider instantaneous bandwidths. A theoretically simple way to achieve higher sample rates is to apply time interleaving to existing kernels. Multiple ADC cores are clocked on different phases of a common sampling clock, allowing for a higher density of signal samples. This increased sampling density provides a useful performance extension and works well with resolutions up to 8 bits. Cross-core matching is relatively easier to manage with standard mixed-signal calibration and circuit layout schemes.

For resolutions of 10-bit and above, especially working in the gigahertz range, it becomes increasingly difficult to ensure a match. As a result, sampling artifacts appear that cause distortion and limit the dynamic performance of the measurement. These high frequency mismatch errors are difficult to mitigate in the analog design world. Therefore, for a 6.4 GS/s time-interleaved ADC, better than 12 fs cross-core phase matching is required to achieve 72 dB SNR (theoretical maximum 12 bits) at a 3 GHz input signal.

Thankfully, the cost of DSP resources has dropped significantly over the past two decades, and algorithmic approaches to spur reduction are now economically feasible. Teledyne SP Devices specializes in the design and manufacture of high-resolution ultra-high-speed digitizers, with decades of experience and expertise in advanced discrete converters.

Unlike single-point or multi-point calibration, ADX4 digital error correction provides spur suppression as the error varies with frequency, so that unwanted aliasing spurs are suppressed into the noise floor.

Implement ADX4

Getting ADX4 Dynamic Boost is very easy. With the required supply chain, customers simply move orders to the -ADX4 option of the EV12AQ600/5 device. Additionally, they need to add the ADX4 module to the Xilinx FPGA code load. This is done.