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© 2004 Fairchild Semiconductor Corporation DS009580 www.fairchildsemi.com
March 1988
Revised January 2004
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74F646
Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceiver circuits with
3-STATE, D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from the input
bus or from the internal registers. Data on the A or B bus
will be clocked into the registers as the appropriate clock
pin goes to a high logic level. Control G and direction pins
are provided to control the transceiver function. In the
transceiver mode, data present at the high impedance port
may be stored in either the A or the B register or in both.
The select controls can multiplex stored and real-time
(transparent mode) data. The direction control determines
which bus will receive data when the enable control G is
Active LOW. In the isolation mode (control G HIGH), A data
may be stored in the B register and/or B data may be
stored in the A register.
Features
■ Independent registers for A and B buses
■Multiplexed real-time and stored data
■74F646 has non-inverting data paths
■3-STATE outputs
■300 mil slim DIP
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74F646MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74F646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
A0–A7 Data Register A Inputs/ 3.5/1.083 70 µ A/− 650 µ A
3-STATE Outputs 600/106.6 (80) − 12 mA/64 mA (48 mA)
B0–B7 Data Register B Inputs/ 3.5/1.083 70 µ A/− 650 µ A
3-STATE Outputs 600/106.6 (80) − 12 mA/64 mA (48 mA)
CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 µ A/− 0.6 mA
SAB, SBA Select Inputs 1.0/1.0 20 µ A/− 0.6 mA
G Output Enable Input 1.0/1.0 20 µ A/− 0.6 mA
DIR Direction Control Input 1.0/1.0 20 µ A/− 0.6 mA
Inputs Data I/O (Note 1)
Function
G DIR CPAB CPBA SAB SBA A0–A7 B0–B7
H X H or L H or L X X Isolation
H X X X X Input Input Clock An Data into A Register
H X X X X Clock Bn Data into B Register
L H X X L X An to Bn—Real Time (Transparent Mode)
L H X L X Input Output Clock An Data into A Register
L H H or L X H X A Register to Bn (Stored Mode)
L H X H X Clock An Data into A Register and Output to Bn
L L X X X L Bn to An—Real Time (Transparent Mode)
L L X X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to An (Stored Mode)
L L X X H Clock Bn Data into B Register and Output to An
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Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature − 65° C to + 150° C
Ambient Temperature under Bias − 55° C to + 125° C
Junction Temperature under Bias − 55° C to + 150° C
VCC Pin Potential to Ground Pin − 0.5V to + 7.0V
Input Voltage (Note 3) − 0.5V to + 7.0V
Input Current (Note 3) − 30 mA to + 5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output − 0.5V to VCC
3-STATE Output − 0.5V to + 5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0° C to + 70° C
Supply Voltage + 4.5V to + 5.5V
Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage − 1.2 V Min IIN = − 18 mA (Non I/O Pins)
VOH Output HIGH 10% VCC
2.0 V Min IOH = − 15 mA (An, Bn)
Voltage
VOL Output LOW 10% VCC
0.55 V Min IOL = 64 mA (An, Bn)
Voltage
IIH Input HIGH
5.0 µ A Max VIN = 2.7V (Non I/O Pins)
Current
IBVI Input HIGH Current
7.0 µ A Max VIN = 7.0V (Non I/O Pins)
Breakdown Test
IBVIT Input HIGH Current
0.5 mA Max VIN = 5.5V (An, Bn)
Breakdown (I/O)
ICEX Output HIGH
50 µ A Max VOUT = VCC
Leakage Current
VID Input Leakage
4.75 V 0.0
IID = 1.9 µ A
Test All Other Pins Grounded
IOD Output Leakage
3.75 µ A 0.0
VIOD = 150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current − 0.6 mA Max VIN = 0.5V (Non I/O Pins)
IIH + IOZH Output Leakage Current 70 µ A Max VOUT = 2.7V (An, Bn)
IIL + IOZL Output Leakage Current − 650 µ A Max VOUT = 0.5V (An, Bn)
IOS Output Short-Circuit Current − 100 − 225 mA Max VOUT = 0V
IZZ Bus Drainage Test 500 µ A 0.0V VOUT = 5.25V
ICCH Power Supply Current 135 mA Max VO = HIGH
ICCL Power Supply Current 150 mA Max VO = LOW
ICCZ Power Supply Current 150 mA Max VO = HIGH Z
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AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = + 25° C TA = − 55° C to + 125° C TA = 0° C to + 70° C
Units
VCC = + 5.0V VCC = + 5.0V VCC = + 5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Max Min Max Min Max
fMAX Maximum Clock Frequency 90 75 90 MHz
tPLH Propagation Delay 2.0 7.0 2.0 8.5 2.0 8.0
ns
tPHL Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0
tPLH Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5
ns
tPHL Bus to Bus 1.0 6.5 1.0 8.0 1.0 7.0
tPLH Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5
ns
tPHL SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0
tPZH Enable Time 2.0 8.5 2.0 10.0 2.0 9.0
ns
tPZL OE to A or B 2.0 12.0 2.0 13.5 2.0 12.5
tPHZ Disable Time 1.0 7.5 1.0 9.0 1.0 8.5
ns
tPLZ OE to A or B 2.0 9.0 2.0 11.0 2.0 9.5
tPZH Enable Time 2.0 14.0 2.0 16.0 2.0 15.0
ns
tPZL DIR to A or B 2.0 13.0 2.0 15.0 2.0 14.0
tPHZ Disable Time 1.0 9.0 1.0 10.0 1.0 9.5
ns
tPLZ DIR to A or B 2.0 11.0 2.0 12.0 2.0 11.5
Symbol Parameter
TA = + 25° C TA = − 55° C to + 125° C TA = 0° C to + 70° C
UnitsVCC = + 5.0V VCC = + 5.0V VCC = + 5.0V
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 5.0 5.0 5.0
ns
tS(L) Bus to Clock 5.0 5.0 5.0
tH(H) Hold Time, HIGH or LOW 2.0 2.5 2.0
ns
tH(L) Bus to Clock 2.0 2.5 2.0
tW(H) Clock Pulse Width 5.0 5.0 5.0
ns
tW(L) HIGH or LOW 5.0 5.0 5.0
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA24
