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74F657SPC

hot 74F657SPC

74F657SPC

For Reference Only

Part Number 74F657SPC
Manufacturer ON Semiconductor
Description IC TXRX NON-INVERT 5.5V 24DIP
Datasheet 74F657SPC Datasheet
Package 24-DIP (0.300", 7.62mm)
In Stock 582 piece(s)
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Lead Time Can Ship Immediately
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74F657SPC

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74F657SPC Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74F657SPC Datasheet
Package24-DIP (0.300", 7.62mm)
Series74F
Logic TypeTransceiver, Non-Inverting
Number of Elements1
Number of Bits per Element8
Output Type3-State
Current - Output High, Low3mA, 24mA
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeThrough Hole
Package / Case24-DIP (0.300", 7.62mm)
Supplier Device Package24-PDIP

74F657SPC Datasheet

Page 1

Page 2

© 1999 Fairchild Semiconductor Corporation DS009584 www.fairchildsemi.com March 1988 Revised August 1999 7 4 F 6 5 7 O c ta l B id ire c tio n a l T ra n s c e iv e r w ith 74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs General Description The 74F657 contains eight non-inverting buffers with 3- STATE outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA at the A Port and 64 mA at the B Port. Features ■ 300 Mil 24-pin slimline DIP ■ Combines 74F245 and 74F280A functions in one package ■ 3-STATE outputs ■ B Outputs sink 64 mA ■ 12 mA source current, B side ■ Input diodes for termination effects Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 75F657SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

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www.fairchildsemi.com 2 7 4 F 6 5 7 Unit Loading/Fan Out Functional Description The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from the A Port to the B Port; Receive (active LOW) enables data from the B Port to the A Port. The Output Enable (OE) input disables the parity and ERROR outputs and both the A and B Ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH. When transmitting (T/R HIGH), the parity generator detects whether an even or odd number of bits on the A Port are HIGH and compares these with the condition of the parity select (ODD/EVEN). If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH. In receiving mode (T/R LOW), the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL A0–A7 Data Inputs/ 4.5/0.15 90 µA/− 90 µA 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) B0–B7 Data Inputs/ 3.5/0.117 70 µA/−70 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) T/R Transmit/Receive Input 2.0/0.067 40 µA/−40 µA OE Enable Input 2.0/0.067 40 µA/−40 µA PARITY Parity Input/ 3.5/0.117 70 µA/−70µA 3-STATE Output 600/106.6 (80) −12 mA/64 mA (48 mA) ODD/EVEN ODD/EVEN Parity Input 1.0/0.033 20 µA/−20 µA ERROR Error Output 600/106.6 (80) −12 mA/64 mA (48 mA) Number of Inputs that are HIGH Inputs Input/ Outputs Output OE T/R ODD/ Parity ERROR Outputs EVEN Mode 0, 2, 4, 6, 8 L H H H Z Transmit L H L L Z Transmit L L H H H Receive L L H L L Receive L L L H L Receive L L L L H Receive 1, 3, 5, 7 L H H L Z Transmit L H L H Z Transmit L L H H L Receive L L H L H Receive L L L H H Receive L L L L L Receive Immaterial H X X Z Z Z Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X High-Z State

Page 4

3 www.fairchildsemi.com 7 4 F 6 5 7 Functional Block Diagram

Page 5

www.fairchildsemi.com 4 7 4 F 6 5 7 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH 10% VCC 2.5 V Min IOH = −1 mA (An) Voltage 10% VCC 2.4 IOH = −3 mA (An Bn, Parity, ERROR) 10% VCC 2.0 IOH = −15 mA (Bn, Parity, ERROR) 5% VCC 2.7 IOH = −1 mA (An) 5% VCC 2.7 IOH = −3 mA (An, Bn, Parity, ERROR) VOL Output LOW 10% VCC 0.5 V Min IOL = 24 mA (An) Voltage 10% VCC 0.55 IOL = 64 mA (Bn Parity, ERROR) IIH Input HIGH 20 µA Max VIN = 2.7V (ODD/EVEN) Current 40 VIN 2.7V (T/R, OE) IBVI Input HIGH Current 100 µA VCC = 0 VIN = 7.0V (T/R, OE, ODD/EVEN) Breakdown Test IBVIT Input HIGH Current 1.0 mA Max VIN = 5.5V (Parity, Bn) Breakdown Test (I/O) 2.0 VIN = 5.5V (An) IIL Input LOW −20 µA Max VIN = 0.5V (ODD/EVEN) Current −40 VIN = 0.5V (T/R, OE) IOZH Output Leakage Current 50 µA Max VOUT = 2.7V (ERROR) IOZL Output Leakage Current −50 µA Max VOUT = 0.5V (ERROR) IIH + IOZH Output Leakage 70 µA Max VI/O = 2.7V (Bn, Parity) Current 90 VI/O = 2.7V (An) IIL + IOZL Output Leakage −70 µA Max VI/O = 0.5V (Bn, Parity) Current −90 VI/O = 0.5V (An) IOS Output Short-Circuit −60 −150 mA Max VOUT = 0V (An) Current −100 −225 VOUT = 0V (Bn, Parity, ERROR) ICEX Output HIGH Leakage 250 µA Max VOUT = VCC (ERROR) Current 1.0 mA Max VOUT = VCC (Bn, Parity) 2.0 mA Max VOUT = VCC (An) IZZ Bus Drainage Test 500 µA 0.0V VOUT = 5.25V (An, Bn, Parity, ERROR) ICCH Power Supply Current 101 125 mA Max VO = HIGH ICCL Power Supply Current 112 150 mA Max VO = LOW ICCZ Power Supply Current 109 145 mA Max VO = HIGH Z

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5 www.fairchildsemi.com 7 4 F 6 5 7 AC Electrical Characteristics Note 3: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) + (Output Enable Time). Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C Units VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 2.5 4.5 8.0 2.5 9.5 2.5 9.0 ns tPHL An to Bn, Bn to An 3.0 4.9 7.5 3.0 8.5 3.0 8.0 tPLH Propagation Delay 6.5 10.1 14.0 5.5 18.0 6.0 16.0 ns tPHL An to Parity 7.0 10.9 15.0 5.5 20.5 6.0 16.5 tPLH Propagation Delay 4.5 7.8 11.0 4.0 14.0 4.0 13.0 ns tPHL ODD/EVEN to PARITY 4.5 8.8 12.0 4.5 16.5 4.5 13.5 tPLH Propagation Delay 4.5 7.5 11.0 4.0 14.0 4.0 13.0 ns tPHL ODD/EVEN to ERROR 4.5 8.2 12.0 4.5 16.5 4.5 13.5 tPLH Propagation Delay 8.0 14.0 20.5 7.5 27.0 7.5 23.0 ns tPHL Bn to ERROR 8.0 15.0 21.5 7.5 28.5 7.5 23.5 tPLH Propagation Delay 7.0 10.8 15.5 6.0 20.0 6.0 17.0 ns tPHL PARITY to ERROR 7.5 11.8 16.5 6.5 22.0 7.5 18.5 tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 ns tPZL OE to An/Bn 4.0 6.5 10.0 3.5 13.5 3.5 11.0 tPHZ Output Disable Time 1.0 4.5 8.0 1.0 9.5 1.0 9.0 ns tPLZ OE to An/Bn 1.0 4.9 7.5 1.0 8.5 1.0 8.0 tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 ns tPZL OE to ERROR (Note 3) 4.0 7.7 10.0 3.5 13.5 3.5 11.0 tPHZ Output Disable Time 1.0 4.5 8.0 1.0 9.5 1.0 9.0 ns tPLZ OE to ERROR 1.0 4.9 7.5 1.0 8.5 1.0 8.0 tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 ns tPZL OE to PARITY 4.0 7.7 10.0 3.5 13.5 3.5 11.0 tPHZ Output Disable Time 1.0 4.6 8.0 1.0 9.5 1.0 9.0 ns tPLZ OE to PARITY 1.0 5.1 7.5 1.0 8.5 1.0 8.0

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www.fairchildsemi.com 6 7 4 F 6 5 7 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B

74F657SPC Guarantees

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