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74LCX16543MTDX

hot 74LCX16543MTDX

74LCX16543MTDX

For Reference Only

Part Number 74LCX16543MTDX
Manufacturer ON Semiconductor
Description IC TXRX NON-INVERT 3.6V 56TSSOP
Datasheet 74LCX16543MTDX Datasheet
Package 56-TFSOP (0.240", 6.10mm Width)
In Stock 393 piece(s)
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74LCX16543MTDX

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74LCX16543MTDX Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74LCX16543MTDX Datasheet
Package56-TFSOP (0.240", 6.10mm Width)
Series74LCX
Logic TypeTransceiver, Non-Inverting
Number of Elements2
Number of Bits per Element8
Output Type3-State
Current - Output High, Low24mA, 24mA
Voltage - Supply2 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case56-TFSOP (0.240", 6.10mm Width)
Supplier Device Package56-TSSOP

74LCX16543MTDX Datasheet

Page 1

Page 2

To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. Is Now Part of ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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© 2001 Fairchild Semiconductor Corporation DS012464 www.fairchildsemi.com May 1995 Revised April 2001 7 4 L C X 1 6 5 4 3 L o w V o lta g e 1 6 -B it R e g is te re d T ra n s c e iv e r w ith 5 V T o le ra n t In p u ts a n d O u tp u ts 74LCX16543 Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and Outputs General Description The LCX16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary stor- age of data flowing in either direction. Each byte has sepa- rate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit inde- pendent input and output control in either direction of data flow. The LCX16543 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16543 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining CMOS low power dissipation. Features ■5V tolerant inputs and outputs ■2.3V–3.6V VCC specifications provided ■5.2 ns tPD max (VCC = 3.3V), 20 µ A ICC max ■Power down high impedance inputs and outputs ■Supports live insertion/withdrawal (Note 1) ■ ± 24 mA Output Drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■Latch-up performance exceeds 500 mA ■ESD performance: Human Body Model > 2000V Machine Model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol Order Number Package Number Package Description 74LCX16543MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74LCX16543MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Page 4

www.fairchildsemi.com 2 7 4 L C X 1 6 5 4 3 Pin Descriptions Data I/O Control Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn Functional Description The LCX16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable (CEABn) input must be LOW in order to enter data from A0–A15 or take data from B0–B15, as indi- cated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable (LEABn) input makes the A-to-B latches transparent; a subsequent LOW- to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBAn, LEBAn and OEBAn inputs. Pin Names Description OEABn A-to-B Output Enable Input (Active LOW) OEBAn B-to-A Output Enable Input (Active LOW) CEABn A-to-B Enable Input (Active LOW) CEBAn B-to-A Enable Input (Active LOW) LEABn A-to-B Latch Enable Input (Active LOW) LEBAn B-to-A Latch Enable Input (Active LOW) A0–A15 A-to-B Data Inputs or B-to-A 3-STATE Outputs B0–B15 B-to-A Data Inputs or A-to-B 3-STATE Outputs Inputs Latch Status Output Buffers CEABn LEABn OEABn (Byte n) (Byte n) H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving

Page 5

3 www.fairchildsemi.com 7 4 L C X 1 6 5 4 3 Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Page 6

www.fairchildsemi.com 4 7 4 L C X 1 6 5 4 3 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 4) Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom- mended Operating Conditions” table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Unused (inputs or I/Os) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol Parameter Value Conditions Units VCC Supply Voltage − 0.5 to + 7.0 V VI DC Input Voltage − 0.5 to + 7.0 V VO DC Output Voltage − 0.5 to + 7.0 Output in 3-STATE V − 0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 3) IIK DC Input Diode Current − 50 VI < GND mA IOK DC Output Diode Current − 50 VO < GND mA + 50 VO > VCC IO DC Output Source/Sink Current ± 50 mA ICC DC Supply Current per Supply Pin ± 100 mA IGND DC Ground Current per Ground Pin ± 100 mA TSTG Storage Temperature − 65 to + 150 ° C Symbol Parameter Min Max Units VCC Supply Voltage Operating 2.0 3.6 V Data Retention 1.5 3.6 VI Input Voltage 0 5.5 V VO Output Voltage HIGH or LOW State 0 VCC V 3-STATE 0 5.5 IOH/IOL Output Current VCC = 3.0V − 3.6V ± 24 mAVCC = 2.7V − 3.0V ± 12 VCC = 2.3V − 2.7V ± 8 TA Free-Air Operating Temperature − 40 85 ° C ∆ t/∆ V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V Symbol Parameter Conditions VCC TA = − 40° C to + 85° C Units (V) Min Max VIH HIGH Level Input Voltage 2.3 − 2.7 1.7 V 2.7 − 3.6 2.0 VIL LOW Level Input Voltage 2.3 − 2.7 0.7 V 2.7 − 3.6 0.8 VOH HIGH Level Output Voltage IOH = − 100 µ A 2.3 − 3.6 VCC − 0.2 V IOH = − 8 mA 2.3 1.8 IOH = − 12 mA 2.7 2.2 IOH = − 18 mA 3.0 2.4 IOH = − 24 mA 3.0 2.2 VOL LOW Level Output Voltage IOL = 100 µ A 2.3 − 3.6 0.2 V IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ± 5.0 µ A IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ± 5.0 µ A VI = VIH or VIL IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 µ A

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5 www.fairchildsemi.com 7 4 L C X 1 6 5 4 3 DC Electrical Characteristics (Continued) Note 5: Outputs in disabled or 3-STATE only. AC Electrical Characteristics Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Capacitance Symbol Parameter Conditions VCC TA = − 40° C to + 85° C Units (V) Min Max ICC Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 20 µ A 3.6V ≤ VI, VO ≤ 5.5V (Note 5) 2.3 − 3.6 ± 20 ∆ ICC Increase in ICC per Input VIH = VCC − 0.6V 2.3 − 3.6 500 µ A Symbol Parameter TA = − 40° C to + 85° C, RL = 500 Ω Units VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max tPHL Propagation Delay 1.5 5.2 1.5 6.0 1.5 6.2 ns tPLH An to Bn or Bn to An 1.5 5.2 1.5 6.0 1.5 6.2 tPHL Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8 ns tPLH LEBAn to An or LEABn to Bn 1.5 6.5 1.5 7.5 1.5 7.8 tPZL Output Enable Time tPZH OEBAn or OEABn to An or Bn 1.5 6.5 1.5 7.0 1.5 8.5 ns CEBAn or CEABn to An or Bn 1.5 6.5 1.5 7.0 1.5 8.5 tPLZ Output Disable Time tPHZ OEBAn or OEABn to An or Bn 1.5 6.5 1.5 7.0 1.5 7.8 ns CEBAn or CEABn to An or Bn 1.5 6.5 1.5 7.0 1.5 7.8 tS Setup Time, HIGH or LOW, 2.5 2.5 3.0 ns Data to LEXXn tH Hold Time, HIGH or LOW, 1.5 1.5 2.0 ns Data to LEXXn tW Pulse Width, Latch Enable, LOW 3.0 3.0 3.5 ns tOSHL Output to Output Skew (Note 6) 1.0 ns tOSLH 1.0 Symbol Parameter Conditions VCC TA = 25° C Units (V) Typical VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 − 0.8 V CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 − 0.6 Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC = Open, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF

Page 8

www.fairchildsemi.com 6 7 4 L C X 1 6 5 4 3 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and trec Waveforms 3-STATE Output Low Enable and Disable Times for Logic 3-STATE Output High Enable and Disable Times for Logic Setup Time, Hold Time and Recovery Time for Logic trise and tfall FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH,tPHZ GND Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V

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7 www.fairchildsemi.com 7 4 L C X 1 6 5 4 3 Schematic Diagram Generic for LCX Family

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www.fairchildsemi.com 8 7 4 L C X 1 6 5 4 3 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A

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