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Part Number 74LVT16245MTDX
Manufacturer Fairchild/ON Semiconductor
Datasheet 74LVT16245MTDX Datasheet
Package 48-TFSOP (0.240", 6.10mm Width)
In Stock 27,106 piece(s)
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Part Number # 74LVT16245MTDX (Logic - Buffers, Drivers, Receivers, Transceivers) is manufactured by Fairchild/ON Semiconductor and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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74LVT16245MTDX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74LVT16245MTDXDatasheet
Package48-TFSOP (0.240", 6.10mm Width)
Logic TypeBuffer, Non-Inverting
Number of Elements2
Number of Bits per Element8
Input Type-
Output TypePush-Pull
Current - Output High, Low32mA, 64mA
Voltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case48-TFSOP (0.240", 6.10mm Width)
Supplier Device Package48-TSSOP

74LVT16245MTDX Datasheet

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© 2005 Fairchild Semiconductor Corporation DS500152 January 1999 Revised June 2005 7 4 L V T 1 6 2 4 5 • 7 4 L V T H 1 6 2 4 5 L o w V o lta g e 1 6 -B it T ra n s c e iv e r w ith 3 -S T A T E O u tp u ts 74LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs General Description The LVT16245 and LVTH16245 contain sixteen non-invert- ing bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVTH16245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low-volt- age (3.3V) VCC applications, but with the capability to pro- vide a TTL interface to a 5V environment. The LVT16245 and LVTH16245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Features ■ Input and output interface capability to systems at 5V VCC ■Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16245), also available without bushold feature (74LVT16245). ■Live insertion/extraction permitted ■Power Up/Down high impedance provides glitch-free bus loading ■Outputs source/sink 32 mA/64 mA ■Functionally compatible with the 74 series 16245 ■Latch-up performance exceeds 500 mA ■ESD performance: Human-body model !2000V Machine model !200V Charged-device !1000V ■Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Order Number Package Number Package Description 74LVT16245GX (Note 1) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 74LVT16245MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16245MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16245GX (Note 1) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 74LVTH16245MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16245MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Page 3 2 7 4 L V T 1 6 2 4 5 • 7 4 L V T H 1 6 2 4 5 Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) Pin Descriptions FBGA Pin Assignments Truth Tables H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Pin Names Description OEn Output Enable Input (Active LOW) T/Rn Transmit/Receive Input A0–A15 Side A Inputs/3-STATE Outputs B0–B15 Side B Inputs/3-STATE Outputs NC No Connect 1 2 3 4 5 6 A B0 NC T/R1 OE1 NC A0 B B2 B1 NC NC A1 A2 C B4 B3 VCC VCC A3 A4 D B6 B5 GND GND A5 A6 E B8 B7 GND GND A7 A8 F B10 B9 GND GND A9 A10 G B12 B11 VCC VCC A11 A12 H B14 B13 NC NC A13 A14 J B15 NC T/R2 OE2 NC A15 Inputs Outputs OE1 T/R1 L L Bus B0–B7 Data to Bus A0–A7 L H Bus A0–A7 Data to Bus B0–B7 H X HIGH–Z State on A0–A7,B0–B7 Inputs Outputs OE2 T/R2 L L Bus B8–B15 Data to Bus A8–A15 L H Bus A8–A15 Data to Bus B8–B15 H X HIGH–Z State on A8–A15,B8–B15

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3 7 4 L V T 1 6 2 4 5 • 7 4 L V T H 1 6 2 4 5 Functional Description The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Logic Diagrams Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Page 5 4 7 4 L V T 1 6 2 4 5 • 7 4 L V T H 1 6 2 4 5 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Ratings must be observed. DC Electrical Characteristics Symbol Parameter Value Conditions Units VCC Supply Voltage 0.5 to 4.6 V VI DC Input Voltage 0.5 to 7.0 V VO Output Voltage 0.5 to 7.0 Output in 3-STATE V 0.5 to 7.0 Output in HIGH or LOW State (Note 4) IIK DC Input Diode Current 50 VI  GND mA IOK DC Output Diode Current 50 VO  GND mA IO DC Output Current 64 Output at HIGH State, VO ! VCC mA 128 Output at LOW State, VO ! VCC ICC DC Supply Current per Supply Pin r64 mA IGND DC Ground Current per Ground Pin r128 mA TSTG Storage Temperature Range 65 to 150 qC Symbol Parameter Min Max Units VCC Supply Voltage 2.7 3.6 V VI Input Voltage 0 5.5 V IOH HIGH-Level Output Current 32 mA IOL LOW-Level Output Current 64 mA TA Free-Air Operating Temperature 40 85 qC 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 0 10 ns/V Symbol Parameter VCC TA 40qC to 85qC Units Conditions (V) Min Max VIK Input Clamp Diode Voltage 2.7 1.2 V II 18 mA VIH Input HIGH Voltage 2.7–3.6 2.0 V VO d 0.1V or VIL Input LOW Voltage 2.7–3.6 0.8 V VO t VCC  0.1V VOH Output HIGH Voltage 2.7–3.6 VCC  0.2 V IOH 100 PA 2.7 2.4 IOH 8 mA 3.0 2.0 IOH 32 mA VOL Output LOW Voltage 2.7 0.2 V IOL 100 PA 2.7 0.5 IOL 24 mA 3.0 0.4 IOL 16 mA 3.0 0.5 IOL 32 mA 3.0 0.55 IOL 64 mA II(HOLD) Bushold Input Minimum Drive 3.0 75 PA VI 0.8V (Note 5) 75 VI 2.0V II(OD) Bushold Input Over-Drive 3.0 500 PA (Note 6) (Note 5) Current to Change State 500 (Note 7) II Input Current 3.6 10 PA VI 5.5V Control Pins 3.6 r1 VI 0V or VCC Data Pins 3.6 5 VI 0V 1 VI VCC IOFF Power Off Leakage Current 0 r100 PA 0V d VI or VO d 5.5V IPU/PD Power Up/Down 3-STATE 0–1.5 r100 PA VO 0.5V to 3.0V Output Current VI GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.0V (Note 5)

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5 7 4 L V T 1 6 2 4 5 • 7 4 L V T H 1 6 2 4 5 DC Electrical Characteristics (Continued) Note 5: Applies to bushold versions only (74LVTH16245). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics (Note 9) Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance (Note 12) Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012. Symbol Parameter VCC TA 40qC to 85qC Units Conditions (V) Min Max IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.6V (Note 5) IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC  VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5.0 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d VO d 5.5V, Outputs Disabled 'ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC  0.6V (Note 8) Other Inputs at VCC or GND Symbol Parameter VCC TA 25qC Units Conditions (V) Min Typ Max CL 50 pF, RL 500: VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Symbol Parameter TA 40qC to 85qC Units CL 50 pF, RL 500: VCC 3.3V r 0.3V VCC 2.7V Min Max Min Max tPLH Propagation Delay Data to Output 1.5 3.5 1.5 3.9 ns tPHL 1.3 3.5 1.3 3.9 tPZH Output Enable Time 1.5 4.5 1.5 5.3 ns tPZL 1.6 5.3 1.6 6.9 tPHZ Output Disable Time 2.3 5.4 2.3 6.1 ns tPLZ 2.2 5.1 2.2 5.4 tOSHL Output to Output Skew 1.0 1.0 ns tOSLH (Note 11) Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC 0V, VI 0V or VCC 4 pF CI/O Input/Output Capacitance VCC 3.0V, VO 0V or VCC 8 pF

Page 7 6 7 4 L V T 1 6 2 4 5 • 7 4 L V T H 1 6 2 4 5 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary

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7 7 4 L V T 1 6 2 4 5 • 7 4 L V T H 1 6 2 4 5 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A

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July 17, 2020

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July 8, 2020

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June 9, 2020

Fast delivery well packed and as described.

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