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AD5628ACPZ-2-RL7

AD5628ACPZ-2-RL7

AD5628ACPZ-2-RL7

For Reference Only

Part Number AD5628ACPZ-2-RL7
Manufacturer Analog Devices Inc.
Description IC DAC 12BIT OCT 2.5V 16FCSP
Datasheet AD5628ACPZ-2-RL7 Datasheet
Package 16-WQFN Exposed Pad, CSP
In Stock 469 piece(s)
Unit Price $ 10.4139 *
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AD5628ACPZ-2-RL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD5628ACPZ-2-RL7 Datasheet
Package16-WQFN Exposed Pad, CSP
SeriesdenseDAC
Number of Bits12
Number of D/A Converters8
Settling Time7µs
Output TypeVoltage - Buffered
Differential OutputNo
Data InterfaceSPI, DSP
Reference TypeExternal, Internal
Voltage - Supply, Analog2.7 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
INL/DNL (LSB)±0.5, ±0.25 (Max)
ArchitectureString DAC
Operating Temperature-40°C ~ 105°C
Package / Case16-WQFN Exposed Pad, CSP
Supplier Device Package16-LFCSP-WQ (4x4)

AD5628ACPZ-2-RL7 Datasheet

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Octal, 12-/14-/16-Bit, SPI Voltage Output denseDAC with 5 ppm/°C, On-Chip Reference Data Sheet AD5628/AD5648/AD5668 Rev. J Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Low power, small footprint, pin-compatible octal DACs AD5668: 16 bits AD5648: 14 bits AD5628: 12 bits 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-ball WLCSP On-chip 1.25 V/2.5 V, 5 ppm/°C reference Power down to 400 nA at 5 V, 200 nA at 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale or midscale 3 power-down functions Hardware LDAC and LDAC override function CLR function to programmable code Rail-to-rail operation APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAM INTERFACE LOGIC INPUT REGISTER DIN LDAC GND VOUTH VDD LDAC1 VREFIN/VREFOUT SYNC SCLK AD5628/AD5648/AD5668 CLR1 1RU-16 AND WLCSP PACKAGE ONLY. 1.25V/2.5V REF VOUTA VOUTB VOUTC VOUTD VOUTE VOUTF VOUTG DAC REGISTER STRING DAC A BUFFER INPUT REGISTER DAC REGISTER STRING DAC B BUFFER INPUT REGISTER DAC REGISTER STRING DAC C BUFFER INPUT REGISTER DAC REGISTER STRING DAC D BUFFER INPUT REGISTER DAC REGISTER STRING DAC E BUFFER INPUT REGISTER DAC REGISTER STRING DAC F BUFFER INPUT REGISTER DAC REGISTER STRING DAC G BUFFER INPUT REGISTER DAC REGISTER STRING DAC H BUFFER POWER-DOWN LOGIC POWER-ON RESET 05 30 2- 00 1 Figure 1. GENERAL DESCRIPTION The AD5628/AD5648/AD5668 devices are low power, octal, 12-/14-/16-bit, buffered voltage-output DACs. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The AD5668 and AD5628 are available in both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while the AD5648 is available in both a 14-lead and 16-lead TSSOP. The AD5628/AD5648/AD5668 have an on-chip reference with an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have a 1.25 V 5 ppm/°C reference, giving a full-scale output range of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1, AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) and remains powered up at this level until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 400 nA at 5 V and provides software- selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simul- taneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that updates all DACs to a user- programmable code—zero scale, midscale, or full scale. The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing. PRODUCT HIGHLIGHTS 1. Octal, 12-/14-/16-bit DAC. 2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. 3. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-ball WLCSP. 4. Power-on reset to 0 V or midscale. 5. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V.

Page 3

AD5628/AD5648/AD5668 Data Sheet Rev. J | Page 2 of 30 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Revision History ............................................................................... 2  Specifications ..................................................................................... 4  AC Characteristics ........................................................................ 7  Timing Characteristics ................................................................ 8  Absolute Maximum Ratings ............................................................ 9  Thermal Resistance ...................................................................... 9  ESD Caution .................................................................................. 9  Pin Configurations and Function Descriptions ......................... 10  Typical Performance Characteristics ........................................... 12  Terminology .................................................................................... 20  Theory of Operation ...................................................................... 22  DAC Section ................................................................................ 22  Resistor String ............................................................................. 22  Internal Reference ...................................................................... 22  Output Amplifier ........................................................................ 23  Serial Interface ............................................................................ 23  Input Shift Register .................................................................... 24  SYNC Interrupt .......................................................................... 24  Internal Reference Register ....................................................... 25  Power-On Reset .......................................................................... 25  Power-Down Modes .................................................................. 25  Clear Code Register ................................................................... 25  LDAC Function .......................................................................... 27  Power Supply Bypassing and Grounding ................................ 27  Outline Dimensions ....................................................................... 28  Ordering Guide .......................................................................... 30  REVISION HISTORY 1/2017—Rev. I to Rev. J Changes to Table 5 ............................................................................ 9 Added Thermal Resistance Section and Table 6; Renumbered Sequentially ....................................................................................... 9 Changes to Figure 3 ........................................................................ 10 11/2014—Rev. H to Rev. I Changes to Ordering Guide .......................................................... 29 2/2014—Rev. G to Rev. H Changes to Figure 1 .......................................................................... 1 Change to Figure 6 ......................................................................... 10 Change to Table 7 ........................................................................... 10 Changes to Figure 45, Figure 46, and Figure 47 ......................... 17 Changes to Ordering Guide .......................................................... 29 1/2013—Rev. F to Rev. G Added WLCSP Reference TC of 15 ppm/°C, Table 2 .................. 5 Changes to Ordering Guide .......................................................... 29 8/2011—Rev. E to Rev. F Added 16-Ball WLCSP ...................................................... Universal Added Figure 6 and Table 7; Renumbered Sequentially ........... 10 Changes to Figure 32 and Figure 33............................................. 15 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 28 1/2011—Rev. D to Rev. E Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset Error, and Reference TC Parameters, Table 1 ................................ 3 Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset Error, and Reference TC Parameters, Table 2 ................................ 5 Changes to Output Voltage Settling Time, Table 3 ....................... 6 Added Figure 53; Renumbered Sequentially .............................. 17 Change to Output Amplifier Section ........................................... 21 Changes to Ordering Guide .......................................................... 28

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Data Sheet AD5628/AD5648/AD5668 Rev. J | Page 3 of 30 9/2010—Rev. C to Rev. D Change to Title .................................................................................. 1 Added 16-Lead LFCSP Throughout ................................ Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Deleted SnPb from Table 5............................................................... 8 Added Figure 5; Renumbered Sequentially ................................... 9 Changes to Table 6 ............................................................................ 9 Replaced Typical Performance Characteristics Section ............. 10 Changes to Power-On Reset Section ............................................ 23 Updated Outline Dimensions ........................................................ 26 Changes to Ordering Guide ........................................................... 28 1/2010—Rev. B to Rev. C Changes to Figure 3 ........................................................................ 10 Changes to Ordering Guide ........................................................... 28 2/2009—Rev. A to Rev. B Changes to Reference Current Parameter, Table 1 and IDD (Normal Mode) Parameter, Table 1 ................................................ 3 Changes to Reference Current Parameter, Table 2 and IDD (Normal Mode) Parameter, Table 2 ................................................ 5 11/2005—Rev. 0 to Rev. A Change to Specifications .................................................................. 3 10/2005—Revision 0: Initial Version

Page 5

AD5628/AD5648/AD5668 Data Sheet Rev. J | Page 4 of 30 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 1. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 AD5628 Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 12) AD5648 Resolution 14 14 Bits Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8 Differential Nonlinearity ±0.5 ±0.5 LSB Guaranteed monotonic by design (see Figure 11) AD5668 Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 10) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection Ratio –80 –80 dB VDD ± 10% DC Crosstalk (External Reference) 10 10 μV Due to full-scale output change, RL = 2 kΩ to GND or VDD 5 5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 25 μV Due to full-scale output change, RL = 2 kΩ to GND or VDD 10 10 μV/mA Due to load current change OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 μs Coming out of power-down mode, VDD = 5 V REFERENCE INPUTS Reference Current 40 55 40 55 μA VREF = VDD = 5.5 V (per DAC channel) Reference Input Range 0 VDD 0 VDD V Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT Output Voltage AD5628-2/AD5648-2/ AD5668-2, AD5668-3 2.495 2.505 2.495 2.505 V At ambient Reference TC3 5 10 5 10 ppm/°C TSSOP 15 5 10 ppm/°C LFCSP Reference Output Impedance 7.5 7.5 kΩ

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Data Sheet AD5628/AD5648/AD5668 Rev. J | Page 5 of 30 A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS3 Input Current ±3 ±3 µA All digital inputs Input Low Voltage, VINL 0.8 0.8 V VDD = 5 V Input High Voltage, VINH 2 2 V VDD = 5 V Pin Capacitance 3 3 pF POWER REQUIREMENTS VDD 4.5 5.5 4.5 5.5 V All digital inputs at 0 or VDD, DAC active, excludes load current IDD (Normal Mode)4 VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 1.0 1.5 1.0 1.5 mA Internal reference off VDD = 4.5 V to 5.5 V 1.8 2.25 1.7 2.25 mA Internal reference on IDD (All Power-Down Modes)5 VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16,256), and AD5668 (Code 512 to 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down.

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AD5628/AD5648/AD5668 Data Sheet Rev. J | Page 6 of 30 VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 AD5628 Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 12) AD5648 Resolution 14 14 Bits Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8 Differential Nonlinearity ±0.5 ±0.5 LSB Guaranteed monotonic by design (see Figure 11) AD5668 Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 10) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26) Zero-Code Error Drift ±2 ±2 µV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection Ratio3 –80 –80 dB VDD ± 10% DC Crosstalk3 (External Reference) 10 10 µV Due to full-scale output change, RL = 2 kΩ to GND or VDD 5 5 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) DC Crosstalk3 (Internal Reference) 25 25 µV Due to full-scale output change, RL = 2 kΩ to GND or VDD 10 10 µV/mA Due to load current change OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 3 V Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 3 V REFERENCE INPUTS Reference Current 40 55 40 55 µA VREF = VDD = 5.5 V (per DAC channel) Reference Input Range 0 VDD 0 VDD Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT Output Voltage AD5628/AD5648/AD5668-1 1.247 1.253 1.247 1.253 V At ambient Reference TC3 5 15 5 15 ppm/°C TSSOP 15 5 15 ppm/°C LFCSP 15 ppm/°C WLCSP Reference Output Impedance 7.5 7.5 kΩ

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Data Sheet AD5628/AD5648/AD5668 Rev. J | Page 7 of 30 A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS3 Input Current ±3 ±3 µA All digital inputs Input Low Voltage, VINL 0.8 0.8 V VDD = 3 V Input High Voltage, VINH 2 2 V VDD = 3 V Pin Capacitance 3 3 pF POWER REQUIREMENTS VDD 2.7 3.6 2.7 3.6 V All digital inputs at 0 or VDD, DAC active, excludes load current IDD (Normal Mode)4 VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off VDD = 2.7 V to 3.6 V 1.8 2.25 1.7 2.25 mA Internal reference on IDD (All Power-Down Modes)5 VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16256), and AD5668 (Code 512 to 65024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time 2.5 7 µs ¼ to ¾ scale settling to ±2 LSB (16-bit resolution) Slew Rate 1.2 V/µs Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB (16-bit resolution) change around major carry (see Figure 42) 19 nV-s From code 0xEA00 to code 0xE9FF (16-bit resolution) Digital Feedthrough 0.1 nV-s Digital Crosstalk 0.2 nV-s Analog Crosstalk 0.4 nV-s DAC-to-DAC Crosstalk 0.8 nV-s Multiplying Bandwidth 320 kHz VREF = 2 V ± 0.2 V p-p Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400(16-bit resolution), 1 kHz 100 nV/√Hz DAC code = 0x8400(16-bit resolution), 10 kHz Output Noise 12 μV p-p 0.1 Hz to 10 Hz, DAC code = 0x0000 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C.

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AD5628/AD5648/AD5668 Data Sheet Rev. J | Page 8 of 30 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter VDD = 2.7 V to 5.5 V Unit Test Conditions/Comments t11 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 13 ns min SYNC to SCLK falling edge set-up time t5 4 ns min Data set-up time t6 4 ns min Data hold time t7 0 ns min SCLK falling edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 13 ns min SYNC rising edge to SCLK fall ignore t10 0 ns min SCLK falling edge to SYNC fall ignore t11 10 ns min LDAC pulse width low t12 15 ns min SCLK falling edge to LDAC rising edge t13 5 ns min CLR pulse width low t14 0 ns min SCLK falling edge to LDAC falling edge t15 300 ns typ CLR pulse activation time 1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. 05 30 2- 00 2 t4 t3 SCLK SYNC DIN t1 t2 t5 t6 t7t8 DB31 t9 t10 t11 t12 LDAC1 LDAC2 t14 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. CLR t13 t15VOUT DB0 Figure 2. Serial Write Operation

Page 10

Data Sheet AD5628/AD5648/AD5668 Rev. J | Page 9 of 30 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter Rating VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V VOUT to GND −0.3 V to VDD + 0.3 V VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ MAX) 150°C Reflow Soldering Peak Temperature Pb Free 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 6. Thermal Resistance Package Type θJA θJC Unit RU-141 121 35 °C/W RU-161 113.5 35 °C/W CP-16-172 50.6 30 °C/W CB-16-161 45 °C/W 1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test board. See JEDEC JESD51. 2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with nine thermal vias. See JEDEC JESD51. ESD CAUTION

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