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AD9516-4BCPZ-REEL7

hotAD9516-4BCPZ-REEL7

AD9516-4BCPZ-REEL7

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Part Number AD9516-4BCPZ-REEL7
Manufacturer Analog Devices Inc.
Description IC CLOCK GEN 1.8GHZ VCO 64-LFCSP
Datasheet AD9516-4BCPZ-REEL7 Datasheet
Package 64-VFQFN Exposed Pad, CSP
In Stock 276 piece(s)
Unit Price $ 10.8460 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jan 24 - Jan 29 (Choose Expedited Shipping)
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Part Number # AD9516-4BCPZ-REEL7 (Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD9516-4BCPZ-REEL7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet AD9516-4BCPZ-REEL7Datasheet
Package64-VFQFN Exposed Pad, CSP
Series-
TypeClock Generator, Fanout Distribution
PLLYes
InputClock
OutputCMOS, LVDS, LVPECL
Number of Circuits1
Ratio - Input:Output1:14
Differential - Input:OutputYes/Yes
Frequency - Max2.95GHz
Divider/MultiplierYes/No
Voltage - Supply3.135 V ~ 3.465 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case64-VFQFN Exposed Pad, CSP
Supplier Device Package64-LFCSP-VQ (9x9)

AD9516-4BCPZ-REEL7 Datasheet

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14-Output Clock Generator with Integrated 1.6 GHz VCO Data Sheet AD9516-4 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.45 GHz to 1.80 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 6 pairs of 1.6 GHz LVPECL outputs Each output pair shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of <10 ps 4 pairs of 800 MHz LVDS clock outputs Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay Additive output jitter: 275 fs rms Fine delay adjust (Δt) on each LVDS output Each LVDS output can be reconfigured as two 250 MHz CMOS outputs Automatic synchronization of all outputs on power-up Manual output synchronization available 64-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation GENERAL DESCRIPTION The AD9516-41 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on- chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz to 1.80 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. The AD9516-4 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. FUNCTIONAL BLOCK DIAGRAM REFIN REF1 REF2 CLK LF SW IT C H O VE R A N D M O N IT O R PL L DIVIDER AND MUXs CP VCO STATUS MONITOR LVPECL LVPECL LVPECL LVDS/CMOS LVDS/CMOS SERIAL CONTROL PORT AND DIGITAL LOGIC AD9516-4 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ DIV/Φ Δt Δt Δt Δt 06 42 3- 00 1 Figure 1. The AD9516-4 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz. Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions, up to a maximum of 1024. The AD9516-4 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal). The AD9516-4 is specified for operation over the industrial range of −40°C to +85°C. 1 AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-4 is used, it refers to that specific member of the AD9516 family.

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AD9516-4 Data Sheet Rev. C | Page 2 of 80 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 6 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 8 Clock Output Absolute Phase Noise (Internal VCO Used) .... 9 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ............................................................................. 10 Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO) ............................................................................. 10 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ......................................................................... 10 Clock Output Additive Time Jitter (VCO Divider Not Used) ....................................................................................................... 11 Clock Output Additive Time Jitter (VCO Divider Used) ..... 11 Delay Block Additive Time Jitter .............................................. 12 Serial Control Port ..................................................................... 12 PD, RESET, and SYNC Pins ..................................................... 13 LD, STATUS, and REFMON Pins ............................................ 13 Power Dissipation ....................................................................... 14 Timing Diagrams ............................................................................ 15 Absolute Maximum Ratings .......................................................... 16 Thermal Resistance .................................................................... 16 ESD Caution................................................................................ 16 Pin Configuration and Function Descriptions ........................... 17 Typical Performance Characteristics ........................................... 19 Terminology .................................................................................... 25 Detailed Block Diagram ................................................................ 26 Theory of Operation ...................................................................... 27 Operational Configurations ...................................................... 27 Digital Lock Detect (DLD) ....................................................... 36 Clock Distribution ..................................................................... 40 Reset Modes ................................................................................ 48 Power-Down Modes .................................................................. 49 Serial Control Port ......................................................................... 50 Serial Control Port Pin Descriptions ....................................... 50 General Operation of Serial Control Port ............................... 50 The Instruction Word (16 Bits) ................................................ 51 MSB/LSB First Transfers ........................................................... 51 Thermal Performance .................................................................... 54 Register Map Overview ................................................................. 55 Register Map Descriptions ............................................................ 59 Applications Information .............................................................. 77 Frequency Planning Using the AD9516 .................................. 77 Using the AD9516 Outputs for ADC Clock Applications .... 77 LVPECL Clock Distribution ..................................................... 78 LVDS Clock Distribution .......................................................... 78 CMOS Clock Distribution ........................................................ 79 Outline Dimensions ....................................................................... 80 Ordering Guide .......................................................................... 80

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Data Sheet AD9516-4 Rev. C | Page 3 of 80 REVISION HISTORY 2/13—Rev. B to Rev. C Changes to Register 0x140 to Register 0x143 Default Values; Table 52 ............................................................................................. 56 Changes to Register 0x140 to Register 0x143 Default Values; Table 57 ............................................................................................. 71 Updated Outline Dimensions ........................................................ 80 1/12—Rev. A to Rev. B Changes to 0x232 Description Column, Table 62 ...................... 76 12/10—Rev. 0 to Rev. A Changes to Features, Applications, and General Description ..... 1 Change to CPRSET Pin Resistor Parameter in Table 1 ................ 4 Change to P = 2 DM (2/3) Parameter in Table 2 .......................... 5 Changes to Table 4 ............................................................................ 6 Changes to VCP Supply Parameter in Table 17............................. 14 Change to θJA Value and Endnote in Table 19 ............................. 16 Added Exposed Paddle Notation to Figure 6; Changes to Table 20 ............................................................................................. 17 Added Figure 41; Renumbered Sequentially ............................... 24 Change to High Frequency Clock Distribution—CLK or External VCO > 1600 MHz Section; Change to Table 22 .......... 27 Changes to Table 24 ........................................................................ 29 Change to Configuration and Register Settings Section ............ 31 Change to Phase Frequency Detector (PFD) Section ................ 32 Changes to Charge Pump (CP), On-Chip VCO, PLL External Loop Filter, and PLL Reference Inputs Sections ......... 33 Change to Figure 47; Added Figure 48 ......................................... 33 Changes to Reference Switchover and VCXO/VCO Feedback Divider N—P, A, B, R Sections .................................... 34 Changes to Table 28 ........................................................................ 35 Change to Holdover Section .......................................................... 37 Changes to VCO Calibration Section ........................................... 39 Changes to Clock Distribution Section ........................................ 40 Added Endnote to Table 34 ........................................................... 41 Changes to Channel Dividers—LVDS/CMOS Outputs Section; Added Endnote to Table 39 ............................................ 43 Changes to Write Section ............................................................... 50 Change to the Instruction Word (16 Bits) Section ..................... 51 Change to Figure 65 ........................................................................ 52 Added Thermal Performance Section .......................................... 54 Changes to Register Address 0x003 in Table 52 .......................... 55 Changes to Table 53 ........................................................................ 59 Changes to Table 54 ........................................................................ 60 Changes to Table 55 ........................................................................ 66 Changes to Table 56 ........................................................................ 68 Changes to Table 57 ........................................................................ 71 Changes to Table 58 ........................................................................ 73 Changes to Table 59 ........................................................................ 74 Changes to Table 60 and Table 61 ................................................. 76 Added Frequency Planning Using the AD9516 Section ............ 77 Changes to Figure 71 and Figure 73; Added Figure 72 .............. 78 Changes to LVPECL Clock Distribution and LVDS Clock Distribution Sections ...................................................................... 78 Updated Outline Dimensions........................................................ 80 4/07—Revision 0: Initial Version

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AD9516-4 Data Sheet Rev. C | Page 4 of 80 SPECIFICATIONS Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments VS 3.135 3.3 3.465 V 3.3 V ± 5% VS_LVPECL 2.375 VS V Nominally 2.5 V to 3.3 V ± 5% VCP VS 5.25 V Nominally 3.3 V to 5.0 V ± 5% RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON-CHIP) Frequency Range 1450 1800 MHz See Figure 15 VCO Gain (KVCO) 50 MHz/V See Figure 10 Tuning Voltage (VT) 0.5 VCP − 0.5 V VCP ≤ VS when using internal VCO; outside of this range, the CP spurs may increase due to CP up/down mismatch Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise at 100 kHz Offset −109 dBc/Hz f = 1625 MHz Phase Noise at 1 MHz Offset −128 dBc/Hz f = 1625 MHz REFERENCE INPUTS Differential Mode (REFIN, REFIN) Differential mode (can accommodate single-ended input by ac grounding undriven input) Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) Input Sensitivity 250 mV p-p PLL figure of merit (FOM) increases with increasing slew rate; see Figure 14 Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN 1.30 1.50 1.60 V Self-bias voltage of REFIN1 Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN 4.4 5.3 6.4 kΩ Self-biased1 Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/µs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/µs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 µA Input Capacitance 2 pF Each pin, REFIN/REFIN (REF1/REF2) PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b 2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b 6.0 ns Register 0x017[1:0] = 10b

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Data Sheet AD9516-4 Rev. C | Page 5 of 80 Parameter Min Typ Max Unit Test Conditions/Comments CHARGE PUMP (CP) ICP Sink/Source Programmable High Value 4.8 mA With CPRSET = 5.1 kΩ Low Value 0.60 mA Absolute Accuracy 2.5 % CPV = VCP/2 CPRSET Range 2.7/10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < CPV < VCP − 0.5 V ICP vs. CPV 1.5 % 0.5 < CPV < VCP − 0.5 V ICP vs. Temperature 2 % CPV = VCP/2 PRESCALER (PART OF N DIVIDER) See the VCXO/VCO Feedback Divider N—P, A, B, R section Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P) PLL DIVIDER DELAYS Register 0x019: R, Bits[5:3], N, Bits[2:0]; see Table 54 000 Off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Is Within the LBW of the PLL) The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20log(N) (where N is the value of the N divider) At 500 kHz PFD Frequency −165 dBc/Hz At 1 MHz PFD Frequency −162 dBc/Hz At 10 MHz PFD Frequency −151 dBc/Hz At 50 MHz PFD Frequency −143 dBc/Hz PLL Figure of Merit (FOM) −220 dBc/Hz Reference slew rate > 0.25 V/ns; FOM + 10log (fPFD) is an approxi- mation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed loop, the phase noise, as observed at the VCO output, is increased by 20log(N) PLL DIGITAL LOCK DETECT WINDOW2 Signal available at LD, STATUS, and REFMON pins when selected by appropriate register settings Required to Lock (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4] Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b To Unlock After Lock (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b 1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. 2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

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AD9516-4 Data Sheet Rev. C | Page 6 of 80 CLOCK INPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK, CLK) Differential input Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 01 1.6 GHz Distribution only (VCO divider bypassed) Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Input Level, Differential 2 V p-p Larger voltage swings may turn on the protection diodes and may degrade jitter performance Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Differential (OUT, OUT) Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 25 for peak-to – peak differential amplitude Output High Voltage (VOH) VS − 1.12 VS − 0.98 VS − 0.84 V Output Low Voltage (VOL) VS − 2.03 VS − 1.77 VS − 1.49 V Output Differential Voltage (VOD) 550 790 980 mV VOH − VOL for each leg of a differential pair for default amplitude setting with driver not toggling; see Figure 25 for variation over frequency LVDS CLOCK OUTPUTS Differential termination 100 Ω at 3.5 mA OUT6, OUT7, OUT8, OUT9 Differential (OUT, OUT) Output Frequency 800 MHz The AD9516 outputs toggle at higher frequencies, but the output amplitude may not meet the VOD specification; see Figure 26 Differential Output Voltage (VOD) 247 360 454 mV VOH − VOL measurement across a differential pair at the default amplitude setting with output driver not toggling; see Figure 26 for variation over frequency Delta VOD 25 mV This is the absolute value of the difference between VOD when the normal output is high vs. when the complementary output is high Output Offset Voltage (VOS) 1.125 1.24 1.375 V (VOH + VOL)/2 across a differential pair Delta VOS 25 mV This is the absolute value of the difference between VOS when the normal output is high vs. when the complementary output is high Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND CMOS CLOCK OUTPUTS OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, OUT9B Single-ended; termination = 10 pF Output Frequency 250 MHz See Figure 27 Output Voltage High (VOH) VS − 0.1 V At 1 mA load Output Voltage Low (VOL) 0.1 V At 1 mA load

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Data Sheet AD9516-4 Rev. C | Page 7 of 80 TIMING CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 43 Clock Distribution Configuration 773 933 1090 ps See Figure 45 Variation with Temperature 0.8 ps/°C OUTPUT SKEW, LVPECL OUTPUTS1 LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps LVDS Termination = 100 Ω differential; 3.5 mA Output Rise Time, tRL 170 350 ps 20% to 80%, measured differentially2 Output Fall Time, tFL 160 350 ps 20% to 80%, measured differentially2 PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT Delay off on all outputs OUT6, OUT7, OUT8, OUT9 For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps CMOS Termination = open Output Rise Time, tRC 495 1000 ps 20% to 80%; CLOAD = 10 pF Output Fall Time, tFC 475 985 ps 80% to 20%; CLOAD = 10 pF PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT Fine delay off For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps DELAY ADJUST3 LVDS and CMOS Shortest Delay Range4 Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 101111b Zero Scale 50 315 680 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b Full Scale 540 880 1180 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b Longest Delay Range4 Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 000000b Zero Scale 200 570 950 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b Quarter Scale 1.72 2.31 2.89 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b Full Scale 5.7 8.0 10.1 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b Delay Variation with Temperature Short Delay Range5 Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C Long Delay Range5 Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to A for noninverting, and B for inverting. 3 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation.

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AD9516-4 Data Sheet Rev. C | Page 8 of 80 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 1 GHz Input slew rate > 1 V/ns Divider = 1 At 10 Hz Offset −109 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −130 dBc/Hz At 10 kHz Offset −139 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −146 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns Divider = 5 At 10 Hz Offset −120 dBc/Hz At 100 Hz Offset −126 dBc/Hz At 1 kHz Offset −139 dBc/Hz At 10 kHz Offset −150 dBc/Hz At 100 kHz Offset −155 dBc/Hz At 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1.6 GHz, Output = 800 MHz Input slew rate > 1 V/ns Divider = 2 At 10 Hz Offset −103 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −120 dBc/Hz At 10 kHz Offset −127 dBc/Hz At 100 kHz Offset −133 dBc/Hz At 1 MHz Offset −138 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz CLK = 1.6 GHz, Output = 400 MHz Input slew rate > 1 V/ns Divider = 4 At 10 Hz Offset −114 dBc/Hz At 100 Hz Offset −122 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −140 dBc/Hz At 100 kHz Offset −146 dBc/Hz At 1 MHz Offset −150 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 250 MHz Input slew rate > 1 V/ns Divider = 4 At 10 Hz Offset −110 dBc/Hz At 100 Hz Offset −120 dBc/Hz At 1 kHz Offset −127 dBc/Hz At 10 kHz Offset −136 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −147 dBc/Hz >10 MHz Offset −154 dBc/Hz

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Data Sheet AD9516-4 Rev. C | Page 9 of 80 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns Divider = 20 At 10 Hz Offset −124 dBc/Hz At 100 Hz Offset −134 dBc/Hz At 1 kHz Offset −142 dBc/Hz At 10 kHz Offset −151 dBc/Hz At 100 kHz Offset −157 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct to LVPECL output VCO = 1800 MHz; Output = 1800 MHz At 1 kHz Offset −47 dBc/Hz At 10 kHz Offset −82 dBc/Hz At 100 kHz Offset −106 dBc/Hz At 1 MHz Offset −125 dBc/Hz At 10 MHz Offset −142 dBc/Hz At 40 MHz Offset −146 dBc/Hz VCO = 1625 MHz; Output = 1625 MHz At 1 kHz Offset −55 dBc/Hz At 10 kHz Offset −85 dBc/Hz At 100 kHz Offset −109 dBc/Hz At 1 MHz Offset −128 dBc/Hz At 10 MHz Offset −143 dBc/Hz At 40 MHz Offset −147 dBc/Hz VCO = 1450 MHz; Output = 1450 MHz At 1 kHz Offset −61 dBc/Hz At 10 kHz Offset −90 dBc/Hz At 100 kHz Offset −113 dBc/Hz At 1 MHz Offset −131 dBc/Hz At 10 MHz Offset −144 dBc/Hz At 40 MHz Offset −148 dBc/Hz

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V150LT20BP V150LT20BP Littelfuse Inc., VARISTOR 229.5V 6.5KA DISC 20MM, Disc 20mm, - View
P51-300-S-AF-D-5V-000-000 P51-300-S-AF-D-5V-000-000 SSI Technologies Inc, SENSOR 300PSIS 9/16 UNF 5V, Cylinder, - View
RWR81SR422FSS73 RWR81SR422FSS73 Vishay Dale, RES 0.422 OHM 1W 1% WW AXIAL, Axial, - View
RW1S5CAR500JET RW1S5CAR500JET Ohmite, RES SMD 0.5 OHM 5% 1.5W J LEAD, 3916 J-Lead, - View
MCR25JZHF1101 MCR25JZHF1101 Rohm Semiconductor, RES SMD 1.1K OHM 1% 1/4W 1210, 1210 (3225 Metric), - View
FW-04-04-F-D-645-065 FW-04-04-F-D-645-065 Samtec Inc., .050'' BOARD SPACERS, -, - View
VI-BNT-EW-F1 VI-BNT-EW-F1 Vicor Corporation, CONVERTER MOD DC/DC 6.5V 100W, Full Brick, - View
VI-B2N-EW-F4 VI-B2N-EW-F4 Vicor Corporation, CONVERTER MOD DC/DC 18.5V 100W, Full Brick, - View
R05P215S/P R05P215S/P Recom Power, CONV DC/DC 2W 05VIN 15VOUT, 7-SIP Module, 4 Leads, - View
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AD9516-4BCPZ-REEL7

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