Contact Us
SalesDept@heisener.com +86-755-83210559 ext. 811

AD9709ASTZ

hotAD9709ASTZ

AD9709ASTZ

For Reference Only

Part Number AD9709ASTZ
Manufacturer Analog Devices Inc.
Description IC DAC 8BIT DUAL 125MSPS 48-LQFP
Datasheet AD9709ASTZ Datasheet
Package 48-LQFP
In Stock 10,582 piece(s)
Unit Price $ 11.5700 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 3 - Jun 8 (Choose Expedited Shipping)
Request for Quotation

Part Number # AD9709ASTZ (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For AD9709ASTZ specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add AD9709ASTZ with quantity into BOM. Heisener.com does NOT require any registration to request a quote of AD9709ASTZ.

AD9709ASTZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD9709ASTZDatasheet
Package48-LQFP
SeriesTxDAC+?
Number of Bits8
Number of D/A Converters2
Settling Time35ns (Typ)
Output TypeCurrent - Unbuffered
Differential OutputYes
Data InterfaceParallel
Reference TypeExternal, Internal
Voltage - Supply, Analog3 V ~ 5.5 V
Voltage - Supply, Digital2.7 V ~ 5.5 V
INL/DNL (LSB)±0.1, ±0.1
ArchitectureCurrent Source
Operating Temperature-40°C ~ 85°C
Package / Case48-LQFP
Supplier Device Package48-LQFP (7x7)
Mounting Type-

AD9709ASTZ Datasheet

Page 1

Page 2

8-Bit, 125 MSPS, Dual TxDAC+ Digital-to-Analog Converter AD9709 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved. FEATURES 8-bit dual transmit digital-to-analog converter (DAC) 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control Dual port or interleaved data On-chip 1.2 V reference Single 5 V or 3.3 V supply operation Power dissipation: 380 mW @ 5 V Power-down mode: 50 mW @ 5 V 48-lead LQFP APPLICATIONS Communications Base stations Digital synthesis Quadrature modulation 3D ultrasound FUNCTIONAL BLOCK DIAGRAM 1 LATCH 1 DAC BIAS GENERATOR SLEEP DIGITAL INTERFACE AD9709 PORT1 PORT2 WRT1/IQWRT WRT2/IQSEL CLK2/IQ RESETMODE 2 DAC 2 LATCH IOUTB2 IOUTA2 IOUTB1 IOUTA1 CLK1 DCOM1/ DCOM2 DVDD1/ DVDD2 AVDD ACOM GAINCTRL FSADJ2 FSADJ1 REFIO REFERENCE 00 60 6- 00 1 Figure 1. GENERAL DESCRIPTION The AD97091 is a dual-port, high speed, 2-channel, 8-bit CMOS DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP package. The AD9709 offers exceptional ac and dc performance while supporting update rates of up to 125 MSPS. The AD9709 has been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9709 to interface to two separate data ports, or to a single interleaved high speed data port. In inter- leaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature. The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single- ended or differential applications. Both DACs can be simultaneously updated and provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%. 1 Patent pending. The AD9709 is manufactured on an advanced low-cost CMOS process. It operates from a single supply of 3.3 V or 5 V and consumes 380 mW of power. PRODUCT HIGHLIGHTS 1. The AD9709 is a member of a pin-compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution. 2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 3. Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. 4. Low Power. Complete CMOS dual DAC function operates at 380 mW from a 3.3 V or 5 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V temperature-compensated band gap voltage reference. 6. Dual 8-Bit Inputs. The AD9709 features a flexible dual- port interface, allowing dual or interleaved input data.

Page 3

AD9709 Rev. B | Page 2 of 32 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Revision History ............................................................................... 2  Specifications ..................................................................................... 3  DC Specifications ......................................................................... 3  Dynamic Specifications ............................................................... 4  Digital Specifications ................................................................... 5  Absolute Maximum Ratings ............................................................ 6  Thermal Resistance ...................................................................... 6  ESD Caution .................................................................................. 6  Pin Configuration and Function Descriptions ............................. 7  Typical Performance Characteristics ............................................. 8  Terminology .................................................................................... 11  Theory of Operation ...................................................................... 12  Functional Description .............................................................. 12  Reference Operation .................................................................. 13  Gain Control Mode .................................................................... 13  Setting the Full-Scale Current ................................................... 13  DAC Transfer Function ............................................................. 14  Analog Outputs .......................................................................... 14  Digital Inputs .............................................................................. 15  DAC Timing ................................................................................ 15  Sleep Mode Operation ............................................................... 18  Power Dissipation....................................................................... 18  Applying the AD9709 .................................................................... 19  Output Configurations .............................................................. 19  Differential Coupling Using a Transformer ............................ 19  Differential Coupling Using an Op Amp ................................ 19  Single-Ended, Unbuffered Voltage Output ............................. 20  Single-Ended, Buffered Voltage Output Configuration ........ 20  Power and Grounding Considerations .................................... 20  Applications Information .............................................................. 22  Quadrature Amplitude Modulation (QAM) Using the AD9709 ........................................................................................ 22  CDMA ......................................................................................... 23  Evaluation Board ............................................................................ 24  General Description ................................................................... 24  Schematics ................................................................................... 24  Evaluation Board Layout ........................................................... 30  Outline Dimensions ....................................................................... 32  Ordering Guide .......................................................................... 32  REVISION HISTORY 9/09—Rev. A to Rev. B Changes to Power and Grounding Considerations Section ..... 20 Changes to Schematics Section ..................................................... 24 Changes to Evaluation Board Layout Section ............................. 30 1/08—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changed Single Supply Operation to 5 V or 3.3 V ........ Universal Changes to Figure 1 .......................................................................... 1 Added Timing Diagram Section .................................................... 5 Changes to Figure 3 and Table 6 ..................................................... 7 Change to Figure 12 ......................................................................... 9 Changes to Figure 18 to Figure 20 ................................................ 10 Changes to Functional Description Section ............................... 13 Changes to Reference Operation Section .................................... 13 Changes to Figure 23 and Figure 24 ............................................. 13 Changes to Gain Control Mode Section ...................................... 13 Replaced Reference Control Amplifier Section with Setting the Full-Scale Current Section ...................................................... 13 Changes to DAC Transfer Function Section............................... 14 Changes to Interleaved Mode Timing Section ........................... 16 Added Figure 28 ............................................................................. 16 Changes to Power and Grounding Considerations Section ..... 20 Changes to Figure 44 ...................................................................... 22 Deleted Figure 43 ............................................................................ 17 Changes to CDMA Section ........................................................... 23 Changes to Figure 45 Caption ...................................................... 23 Changes to Figure 46 ...................................................................... 24 Changes to Figure 48 ...................................................................... 26 Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 30 5/00—Revision 0: Initial Version

Page 4

AD9709 Rev. B | Page 3 of 32 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 8 Bits DC ACCURACY1 Integral Linearity Error (INL) −0.5 ±0.1 +0.5 LSB Differential Nonlinearity (DNL) −0.5 ±0.1 +0.5 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error Without Internal Reference −2 ±0.25 +2 % of FSR Gain Error with Internal Reference −5 +1 +5 % of FSR Gain Match TA = 25°C −0.3 ±0.1 +0.3 % of FSR TMIN to TMAX −1.6 +1.6 % of FSR TMIN to TMAX −0.14 +0.14 dB Full-Scale Output Current2 2.0 20.0 mA Output Compliance Range −1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V Reference Output Current3 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ Small-Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift Without Internal Reference ±50 ppm of FSR/°C Gain Drift with Internal Reference ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 3 5 5.5 V DVDD1, DVDD2 2.7 5 5.5 V Analog Supply Current (IAVDD) 71 75 mA Digital Supply Current (IDVDD)4 5 7 mA Digital Supply Current (IDVDD)5 15 mA Supply Current Sleep Mode (IAVDD) 8 12 mA Power Dissipation4 (5 V, IOUTFS = 20 mA) 380 410 mW Power Dissipation5 (5 V, IOUTFS = 20 mA) 420 450 mW Power Dissipation6 (5 V, IOUTFS = 20 mA) 450 mW Power Supply Rejection Ratio7—AVDD −0.4 +0.4 % of FSR/V Power Supply Rejection Ratio7—DVDD1, DVDD2 −0.025 +0.025 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz. 5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz. 6 Measured as unbuffered voltage output with IOUTFS = 20 mA and RLOAD = 50 Ω at IOUTA and IOUTB, fCLK = 100 MSPS, and fOUT = 40 MHz. 7 ±10% power supply variation.

Page 5

AD9709 Rev. B | Page 4 of 32 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLK) 125 MSPS Output Settling Time (tST) to 0.1%1 35 ns Output Propagation Delay (tPD) 1 ns Glitch Impulse 5 pV-s Output Rise Time (10% to 90%)1 2.5 ns Output Fall Time (90% to 10%)1 2.5 ns Output Noise (IOUTFS = 20 mA) 50 pA/√Hz Output Noise (IOUTFS = 2 mA) 30 pA/√Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLK = 100 MSPS, fOUT = 1.00 MHz 0 dBFS Output 63 68 dBc –6 dBFS Output 62 dBc –12 dBFS Output 56 dBc –18 dBFS Output 50 dBc fCLK = 65 MSPS, fOUT = 1.00 MHz 68 dBc fCLK = 65 MSPS, fOUT = 2.51 MHz 68 dBc fCLK = 65 MSPS, fOUT = 5.02 MHz 66 dBc fCLK = 65 MSPS, fOUT = 14.02 MHz 60 dBc fCLK = 65 MSPS, fOUT = 25 MHz 50 dBc fCLK = 125 MSPS, fOUT = 25 MHz 63 dBc fCLK = 125 MSPS, fOUT = 40 MHz 55 dBc Signal to Noise and Distortion Ratio fCLK = 50 MHz, fOUT = 1 MHz 50 dB Total Harmonic Distortion fCLK = 100 MSPS, fOUT = 1.00 MHz −67 −63 dBc fCLK = 50 MSPS, fOUT = 2.00 MHz −63 dBc fCLK = 125 MSPS, fOUT = 4.00 MHz −63 dBc fCLK = 125 MSPS, fOUT = 10.00 MHz −63 dBc Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz 0 dBFS Output 58 dBc –6 dBFS Output 51 dBc –12 dBFS Output 46 dBc –18 dBFS Output 41 dBc Channel Isolation fCLK = 125 MSPS, fOUT = 10 MHz 85 dBc fCLK = 125 MSPS, fOUT = 40 MHz 77 dBc 1 Measured single-ended into 50 Ω load.

Page 6

AD9709 Rev. B | Page 5 of 32 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V 3.5 5 V Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V 2.1 3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V 0 1.3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (tS) 2.0 ns Input Hold Time (tH) 1.5 ns Latch Pulse Width (tLPW, tCPW) 3.5 ns Timing Diagram See Table 3 and the DAC Timing section for more information about the timing specifications. DATA IN (WRT2) (WRT1/IQWRT) (CLK2) (CLK1/IQCLK) tPD IOUTA OR IOUTB 0 06 0 6- 0 0 2 tS tH tLPW tCPW Figure 2. Timing for Dual and Interleaved Modes

Page 7

AD9709 Rev. B | Page 6 of 32 ABSOLUTE MAXIMUM RATINGS Table 4. THERMAL RESISTANCE Parameter With Respect To Rating AVDD ACOM −0.3 V to +6.5 V DVDD1, DVDD2 DCOM1/DCOM2 −0.3 V to +6.5 V ACOM DCOM1/DCOM2 −0.3 V to +0.3 V AVDD DVDD1/DVDD2 −6.5 V to +6.5 V MODE, CLK1/IQCLK, CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL DCOM1/DCOM2 −0.3 V to DVDD1/ DVDD2 + 0.3 V Digital Inputs DCOM1/DCOM2 −0.3 V to DVDD1/ DVDD2 + 0.3 V IOUTA1/IOUTA2, IOUTB1/IOUTB2 ACOM −1.0 V to AVDD + 0.3 V REFIO, FSADJ1, FSADJ2 ACOM −0.3 V to AVDD + 0.3 V GAINCTRL, SLEEP ACOM −0.3 V to AVDD + 0.3 V Junction Temperature 150°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type θJA Unit 48-Lead LQFP 91 °C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Page 8

AD9709 Rev. B | Page 7 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 M O D E 47 A V D D 46 I O U T A 1 45 I O U T B 1 44 F S A D J1 43 R E F IO 42 G A IN C T R L 41 F S A D J2 40 I O U T B 2 39 I O U T A 2 38 A C O M 37 S L E E P 35 NC NC NC NC NC 34 DB0P2 (LSB) 33 DB1P2 30 DB4P2 31 DB3P2 32 DB2P2 36 NC 29 DB5P2 28 27 25 26 2 3 4 7 DB5P1 6 DB6P1 DB7P1 (MSB) 5 1 8 DB4P1 9 DB3P1 10 DB2P1 12 DB0P1 11 DB1P1 NC = NO CONNECT 13 N C 14 N C 15 D C O M 1 16 D V D D 1 17 W R T 1/ IQ W R T 18 C L K 1/ IQ C L K 19 C L K 2/ IQ R E S E T 20 W R T 2/ IQ S E L 21 D C O M 2 22 D V D D 2 23 D B 7P 2 (M S B ) 24 D B 6P 2 AD9709 TOP VIEW (Not to Scale) 0 06 06 -0 0 3 NC NC NC NC PIN 1 INDICATOR Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 to 8 DB7P1 to DB0P1 Data Bit Pins (Port 1) 9 to 14, 31 to 36 NC No Connection 15, 21 DCOM1, DCOM2 Digital Common 16, 22 DVDD1, DVDD2 Digital Supply Voltage 17 WRT1/IQWRT Input Write Signal for Port 1 (IQWRT in Interleaving Mode) 18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode) 19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode) 20 WRT2/IQSEL Input Write Signal for Port 2 (IQSEL in Interleaving Mode) 23 to 30 DB7P2 to DB0P2 Data Bit Pins (Port 2) 37 SLEEP Power-Down Control Input 38 ACOM Analog Common 39, 40 IOUTA2, IOUTB2 Port 2 Differential DAC Current Outputs 41 FSADJ2 Full-Scale Current Output Adjust for DAC2 42 GAINCTRL Master/Slave Resistor Control Mode. 43 REFIO Reference Input/Output 44 FSADJ1 Full-Scale Current Output Adjust for DAC1 45, 46 IOUTB1, IOUTA1 Port 1 Differential DAC Current Outputs 47 AVDD Analog Supply Voltage 48 MODE Mode Select (1 = dual port, 0 = interleaved)

Page 9

AD9709 Rev. B | Page 8 of 32 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.3 V or 5 V, DVDD = 3.3 V, IOUTFS = 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist, unless otherwise noted. 75 70 65 60 55 50 45 0.1 1 10 100 S F D R ( d B c) fOUT (MHz) fCLK = 5MSPS fCLK = 25MSPS fCLK = 65MSPS fCLK = 125MSPS 0 06 06 -0 05 Figure 4. SFDR vs. fOUT @ 0 dBFS 75 70 65 60 55 50 45 0 0.5 1.0 1.5 2.0 2.5 S F D R ( d B c) fOUT (MHz) 0dBFS –6dBFS –12dBFS 00 60 6- 0 06 Figure 5. SFDR vs. fOUT @ 5 MSPS 75 70 65 60 55 50 45 0 2 4 6 8 10 12 S F D R ( d B c) fOUT (MHz) 0dBFS –6dBFS –12dBFS 00 60 6- 0 07 Figure 6. SFDR vs. fOUT @ 25 MSPS 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 S F D R ( d B c) fOUT (MHz) –12dBFS 0dBFS –6dBFS 00 60 6 -0 0 8 Figure 7. SFDR vs. fOUT @ 65 MSPS 75 70 65 60 55 50 45 0 10 20 30 40 50 60 70 S F D R ( d B c) fOUT (MHz) –12dBFS 0dBFS –6dBFS 0 06 06 -0 0 9 Figure 8. SFDR vs. fOUT @ 125 MSPS 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 S F D R ( d B c) fOUT (MHz) IOUTFS = 5mA IOUTFS = 10mA IOUTFS = 20mA 00 60 6 -0 1 0 Figure 9. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS

Page 10

AD9709 Rev. B | Page 9 of 32 75 70 65 60 55 50 40 45 –25 –22 –19 –16 –13 –10 –7 –4 –1 2 S F D R ( d B c) 125MSPS/11.37MHz 65MSPS/5.91MHz 25MSPS/2.27MHz 5MSPS/0.46MHz 10MSPS/0.91MHz AOUT (dBFS) 00 60 6- 0 11 Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11 75 70 65 60 55 50 40 45 –25 –20 –15 –10 –5 0 S F D R ( d B c) 125MSPS/5.0MHz 65MSPS/13.0MHz 25MSPS/5.0MHz 5MSPS/1.0MHz 10MSPS/2.0MHz AOUT (dBFS) 00 60 6 -0 1 2 Figure 11. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5 75 70 65 60 55 50 40 45 –25 –20 –15 –10 –5 0 S F D R ( d B c) 0.965MHz/1.035MHz @ 7MSPS 8.8MHz/9.8MHz @ 65MSPS AOUT (dBFS) 16.9MHz/19.1MHz @ 125MSPS 00 60 6 -0 1 3 3.3MHz/3.4MHz @ 25MSPS Figure 12. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7 70 65 60 55 50 40 45 0 20 40 60 80 100 120 140 S IN A D ( d B c) IOUTFS = 5mA IOUTFS = 20mA IOUTFS = 10mA fCLK (MSPS) 0 06 06 -0 1 4 Figure 13. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS CODE 0.06 –0.10 –0.08 –0.06 –0.04 –0.02 0 0.02 0.04 0 32 64 96 160 224128 192 256 IN L ( L S B s) 00 60 6- 01 5 Figure 14. Typical INL 0.07 0.05 0.03 0.01 –0.01 0.06 0.04 0.02 0 0 50 100 150 200 250 D N L ( L S B s) CODE 00 60 6- 0 16 Figure 15. Typical DNL

AD9709ASTZ Reviews

Average User Rating
5 / 5 (69)
★ ★ ★ ★ ★
5 ★
62
4 ★
7
3 ★
0
2 ★
0
1 ★
0

Write a Review

Not Rated
Thanks for Your Review!

Cele*****Sant

May 27, 2020

The items I want are often in stock and available in small quantities.

Bren*****Santos

May 19, 2020

I tested some and all look good.

Hele*****ixon

May 6, 2020

You get the most update products online. You always give me the best choice.

Juli***** Potts

April 30, 2020

Various selection and thoughtful services! Prices are competitive as well. Thank you!

Ellen*****stensen

April 28, 2020

Great product at a good price. No complaints.

Tren*****Kurian

April 25, 2020

Excellent ! AD9709ASTZ item arrived very quickly and was packaged well, no issues.

Lail*****erry

April 18, 2020

The order process is easy and user friendly, very helpful customer service, always fast shipping.

Gary*****indo

April 16, 2020

I took the chance and used it and I worked fine for me.

Aspe*****binson

April 13, 2020

These function just as well. You do need to spend some time modifying the harness, but no big deal.

Rex *****tosh

April 12, 2020

Item came in time and looks as described.

AD9709ASTZ Guarantees

Service Guarantee

Service Guarantees

We guarantee 100% customer satisfaction.

Our experienced sales team and tech support team back our services to satisfy all our customers.

Quality Guarantee

Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

AD9709ASTZ Packaging

Verify Products
Customized Labels
Professional Packaging
Sealing
Packing
Insepction

AD9709ASTZ Related Products

3530N470J602LE 3530N470J602LE Knowles Novacap, CAP RADIAL 3530,47PF,6KV,5%,C0G, Radial, TxDAC+? View
06031C751GAT2A 06031C751GAT2A AVX Corporation, CAP CER 750PF 100V X7R 0603, 0603 (1608 Metric), TxDAC+? View
BAJ2CC0FP-E2 BAJ2CC0FP-E2 Rohm Semiconductor, IC REG LINEAR 12V 1A TO252-3, TO-252-3, DPak (2 Leads + Tab), SC-63, TxDAC+? View
APG66-35053-1 APG66-35053-1 Sensata Technologies/Airpax, CIRCUIT BREAKER MAG-HYDR LEVER, -, TxDAC+? View
LLE101101 LLE101101 Honeywell Sensing and Productivity Solutions, SENSOR LIQUID LEV TYPE1 -40-125C, -, TxDAC+? View
CPR15R1200JE10 CPR15R1200JE10 Vishay Dale, RES 0.12 OHM 15W 5% RADIAL, Radial, TxDAC+? View
Y1691V0032QT9L Y1691V0032QT9L Vishay Foil Resistors (Division of Vishay Precision Group), RES NTWRK 2 RES MULT OHM RADIAL, Radial - 3 Leads, TxDAC+? View
ESQT-116-02-L-Q-590 ESQT-116-02-L-Q-590 Samtec Inc., ELEVATED 2MM SOCKETS, -, TxDAC+? View
BCS-118-L-D-TE-014 BCS-118-L-D-TE-014 Samtec Inc., BOX CONNECTOR SOCKET STRIP, -, TxDAC+? View
MS3451L20-33P MS3451L20-33P Amphenol Aerospace Operations, CONN RCPT 11POS CBL MNT W/PINS, -, TxDAC+? View
GTS00A28-12P GTS00A28-12P Amphenol Industrial Operations, GT 26C 26#16 PIN RECP WALL, -, TxDAC+? View
D38999/24FB5AC D38999/24FB5AC TE Connectivity Deutsch Connectors, CONN RCPT HSNG MALE 5POS PNL MNT, -, TxDAC+? View
Payment Methods
Delivery Services

Quick Inquiry

AD9709ASTZ

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

View the Certificates

Do you have any question about AD9709ASTZ?

+86-755-83210559 ext. 811 SalesDept@heisener.com heisener007 2354944915 Send Message

AD9709ASTZ Tags

  • AD9709ASTZ
  • AD9709ASTZ PDF
  • AD9709ASTZ datasheet
  • AD9709ASTZ specification
  • AD9709ASTZ image
  • Analog Devices Inc.
  • Analog Devices Inc. AD9709ASTZ
  • buy AD9709ASTZ
  • AD9709ASTZ price
  • AD9709ASTZ distributor
  • AD9709ASTZ supplier
  • AD9709ASTZ wholesales

AD9709ASTZ is Available in