Contact Us
SalesDept@heisener.com +86-755-83210559 ext. 811

ADAU1361BCPZ

hotADAU1361BCPZ

ADAU1361BCPZ

For Reference Only

Part Number ADAU1361BCPZ
Manufacturer Analog Devices Inc.
Description IC CODEC 24B PLL 32LFCSP
Datasheet ADAU1361BCPZ Datasheet
Package 32-VFQFN Exposed Pad, CSP
In Stock 5,454 piece(s)
Unit Price $ 8.9700 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 1 - Jun 6 (Choose Expedited Shipping)
Request for Quotation

Part Number # ADAU1361BCPZ (Interface - CODECs) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For ADAU1361BCPZ specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add ADAU1361BCPZ with quantity into BOM. Heisener.com does NOT require any registration to request a quote of ADAU1361BCPZ.

ADAU1361BCPZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - CODECs
Datasheet ADAU1361BCPZDatasheet
Package32-VFQFN Exposed Pad, CSP
Series-
TypeAudio
Data InterfaceSerial
Resolution (Bits)24 b
Number of ADCs / DACs2 / 2
Sigma DeltaNo
S/N Ratio, ADCs / DACs (db) Typ-
Dynamic Range, ADCs / DACs (db) Typ-
Voltage - Supply, Analog1.8 V ~ 3.6 V
Voltage - Supply, Digital1.8 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case32-VFQFN Exposed Pad, CSP
Supplier Device Package32-LFCSP-VQ (5x5)

ADAU1361BCPZ Datasheet

Page 1

Page 2

Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL Data Sheet ADAU1361 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V 6 analog input pins, configurable for single-ended or differential inputs Flexible analog input/output mixers Stereo digital microphone input Analog outputs: 2 differential stereo, 2 single-ended stereo, 1 mono headphone output driver PLL supporting input clocks from 8 MHz to 27 MHz Analog automatic level control (ALC) Microphone bias reference voltage Analog and digital I/O: 1.8 V to 3.65 V I2C and SPI control interfaces Digital audio serial data I/O: stereo and time-division multiplexing (TDM) modes Software-controllable clickless mute Software power-down 32-lead, 5 mm × 5 mm LFCSP −40°C to +85°C operating temperature range APPLICATIONS Smartphones/multimedia phones Digital still cameras/digital video cameras Portable media players/portable audio players Phone accessories products GENERAL DESCRIPTION The ADAU1361 is a low power, stereo audio codec that supports stereo 48 kHz record and playback at 14 mW from a 1.8 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control. The ADAU1361 is ideal for battery-powered audio and telephony applications. The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1361 includes a stereo digital microphone input. The ADAU1361 includes five high power output drivers (two differential and three single-ended), supporting stereo head- phones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio. The serial control bus supports the I2C and SPI protocols. The serial audio bus is programmable for I2S, left-/right-justified, and TDM modes. A programmable PLL supports flexible clock generation for all standard integer rates and fractional master clocks from 8 MHz to 27 MHz. FUNCTIONAL BLOCK DIAGRAM HP JACK DETECTION REGULATOR INPUT MIXERS ALC MICROPHONE BIAS PLL LINN LINP LAUX JACKDET/MICIN RINP RINN RAUX MICBIAS LHP LOUTN LOUTP ADAU1361 RHP MONOOUT ROUTP ROUTN C M IO VD D D G N D D VD D O U T A G N D A VD D A VD D A G N D OUTPUT MIXERS DAC DIGITAL FILTERS ADC DIGITAL FILTERS DAC DACADC ADC SDA/ COUT I2C/SPI CONTROL PORT SERIAL DATA INPUT/OUTPUT PORTS MCLK ADC_SDATA B C LK SCL/CCLK ADDR1/ CDATA ADDR0/ CLATCH LR C LK DAC_SDATA 07 67 9- 00 1 Figure 1.

Page 3

ADAU1361 Data Sheet Rev. D | Page 2 of 80 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Analog Performance Specifications ........................................... 4 Power Supply Specifications........................................................ 7 Typical Current Consumption .................................................... 8 Typical Power Management Measurements ............................. 9 Digital Filters ............................................................................... 10 Digital Input/Output Specifications......................................... 10 Digital Timing Specifications ................................................... 11 Digital Timing Diagrams........................................................... 12 Absolute Maximum Ratings .......................................................... 14 Thermal Resistance .................................................................... 14 ESD Caution ................................................................................ 14 Pin Configuration and Function Descriptions ........................... 15 Typical Performance Characteristics ........................................... 17 System Block Diagrams ................................................................. 20 Theory of Operation ...................................................................... 23 Startup, Initialization, and Power ................................................. 24 Power-Up Sequence ................................................................... 24 Power Reduction Modes ............................................................ 24 Digital Power Supply .................................................................. 24 Input/Output Power Supply ...................................................... 24 Clock Generation and Management ........................................ 24 Clocking and Sampling Rates ....................................................... 26 Core Clock ................................................................................... 26 Sampling Rates ............................................................................ 26 PLL ............................................................................................... 27 Record Signal Path ......................................................................... 29 Input Signal Paths ....................................................................... 29 Analog-to-Digital Converters ................................................... 31 Automatic Level Control (ALC) ................................................... 32 ALC Parameters .......................................................................... 32 Noise Gate Function .................................................................. 33 Playback Signal Path ...................................................................... 35 Output Signal Paths ................................................................... 35 Headphone Output .................................................................... 36 Pop-and-Click Suppression ...................................................... 37 Line Outputs ............................................................................... 37 Control Ports ................................................................................... 38 Burst Mode Writing and Reading ............................................ 38 I2C Port ........................................................................................ 38 SPI Port ........................................................................................ 41 Serial Data Input/Output Ports .................................................... 42 Applications Information .............................................................. 44 Power Supply Bypass Capacitors .............................................. 44 GSM Noise Filter ........................................................................ 44 Grounding ................................................................................... 44 Exposed Pad PCB Design ......................................................... 44 Control Registers ............................................................................ 45 Control Register Details ............................................................ 46 Outline Dimensions ....................................................................... 79 Ordering Guide .......................................................................... 79

Page 4

Data Sheet ADAU1361 Rev. D | Page 3 of 80 REVISION HISTORY 8/2018—Rev. C to Rev. D Changed tSODM to tSOD, Table 7 ........................................................ 11 Changes to tSOD Parameter, Table 7 ............................................... 11 Changes to Figure 3 ......................................................................... 12 9/2010—Rev. B to Rev. C Changes to Figure 1 ........................................................................... 1 5/2010—Rev. A to Rev. B Changes to Burst Mode Writing and Reading Section .............. 38 Changes to Table 26 ........................................................................ 45 Change to Table 43 .......................................................................... 58 Added R67: Dejitter Control, 16,438 (0x4036) Section ............. 73 12/2009—Rev. 0 to Rev. A Changes to Features Section ............................................................ 1 Changes to General Description Section ....................................... 1 Changes to Table 1 ............................................................................ 6 Change to Table 5 ............................................................................ 10 Changes to Figure 6 ......................................................................... 13 Changes to Table 10 ........................................................................ 15 Changes to Captions of Figure 15, Figure 16, Figure 18, and Figure 19 ................................................................................... 18 Changes to Captions of Figure 21 and Figure 24 ........................ 19 Added Figure 22; Renumbered Sequentially ............................... 19 Change to Figure 25 ........................................................................ 20 Change to Figure 26 ........................................................................ 21 Change to Figure 27 ........................................................................ 22 Change to Theory of Operation Section ...................................... 23 Changes to Power Reduction Modes Section and Case 1: PLL Is Bypassed Section ................................................... 24 Changes to PLL Lock Acquisition Section ................................... 25 Changes to Core Clock Section ..................................................... 26 Changes to Input Signal Paths Section and Figure 31 ................ 29 Changes to Figure 32 and Figure 33 ............................................. 30 Changes to ADC Full-Scale Level Section ................................... 31 Change to Automatic Level Control (ALC) Section .................. 32 Changes to Output Signal Paths Section ...................................... 35 Changes to Headphone Output Section ....................................... 36 Changes to Jack Detection Section, Pop-and-Click Suppression Section, and Line Outputs Section ......................... 37 Changes to Control Ports Section and I2C Port Section ............ 38 Added Burst Mode Writing and Reading Section ...................... 38 Changes to SPI Port Section .......................................................... 41 Changes to Serial Data Input/Output Ports Section, Table 24, and Table 25 ..................................................................................... 42 Added Figure 56 .............................................................................. 42 Changes to Figure 60 and Figure 61 ............................................. 43 Changes to Table 26 ........................................................................ 45 Changes to R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) Section and Table 29 .......................................... 47 Changes to Table 35 ........................................................................ 52 Changes to Table 36 ........................................................................ 53 Changes to R15: Serial Port Control 0, 16,405 (0x4015) Section and Table 42 ....................................................................... 57 Change to Table 43 .......................................................................... 58 Changes to Table 44, R18: Converter Control 1, 16,408 (0x4018) Section, and Table 45 ..................................................... 59 Changes to Table 53, R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) Section, and Table 54... 65 Changes to Table 55, R29: Playback Headphone Left Volume Control, 16,419 (0x4023) Section, and Table 56 ......................... 66 Changes to R42: Jack Detect Pin Control, 16,433 (0x4031) Section and Table 69 ....................................................................... 73 1/2009—Revision 0: Initial Version

Page 5

ADAU1361 Data Sheet Rev. D | Page 4 of 80 SPECIFICATIONS Supply voltage (AVDD) = 3.3 V, TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V, unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG-TO-DIGITAL CONVERTERS ADC performance excludes mixers and PGA ADC Resolution All ADCs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB INPUT RESISTANCE Single-Ended Line Input −12 dB gain 83 kΩ 0 dB gain 21 kΩ 6 dB gain 10.5 kΩ PGA Inverting Inputs −12 dB gain 84.5 kΩ 0 dB gain 53 kΩ 35.25 dB gain 2 kΩ PGA Noninverting Inputs All gains 105 kΩ SINGLE-ENDED LINE INPUT Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 99 dB No Filter (RMS) AVDD = 1.8 V 91 dB AVDD = 3.3 V 96 dB Total Harmonic Distortion + Noise −1 dBFS AVDD = 1.8 V −88 dB AVDD = 3.3 V −90 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 94 dB AVDD = 3.3 V 99 dB No Filter (RMS) AVDD = 1.8 V 91 dB AVDD = 3.3 V 96 dB Gain per Step 3 dB Total Gain Range −12 +6 dB Mute Attenuation −87 dB Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Gain Error −12 % Interchannel Isolation 68 dB Power Supply Rejection Ratio CM capacitor = 20 μF 100 mV p-p @ 217 Hz 65 dB 100 mV p-p @ 1 kHz 67 dB

Page 6

Data Sheet ADAU1361 Rev. D | Page 5 of 80 Parameter Test Conditions/Comments Min Typ Max Unit PSEUDO-DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Total Harmonic Distortion + Noise −1 dBFS AVDD = 1.8 V −88 dB AVDD = 3.3 V −89 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Volume Control Step PGA gain 0.75 dB Volume Control Range PGA gain −12 +35.25 dB PGA Boost 20 dB Mute Attenuation −87 dB Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Gain Error −14 % Interchannel Isolation 83 dB Common-Mode Rejection Ratio 100 mV rms, 1 kHz 65 dB 100 mV rms, 20 kHz 65 dB FULL DIFFERENTIAL PGA INPUT Differential PGA inputs Full-Scale Input Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Dynamic Range 20 Hz to 20 kHz, −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Total Harmonic Distortion + Noise −1 dBFS AVDD = 1.8 V −70 dB AVDD = 3.3 V −78 dB Signal-to-Noise Ratio With A-Weighted Filter (RMS) AVDD = 1.8 V 92 dB AVDD = 3.3 V 98 dB No Filter (RMS) AVDD = 1.8 V 90 dB AVDD = 3.3 V 95 dB Volume Control Step PGA gain 0.75 dB Volume Control Range PGA gain −12 +35.25 dB PGA Boost 20 dB Mute Attenuation −87 dB Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Gain Error −14 %

Page 7

ADAU1361 Data Sheet Rev. D | Page 6 of 80 Parameter Test Conditions/Comments Min Typ Max Unit Interchannel Isolation 83 dB Common-Mode Rejection Ratio 100 mV rms, 1 kHz 65 dB 100 mV rms, 20 kHz 65 dB MICROPHONE BIAS MBIEN = 1 Bias Voltage 0.65 × AVDD AVDD = 1.8 V, MBI = 1 1.17 V AVDD = 3.3 V, MBI = 1 2.145 V 0.90 × AVDD AVDD = 1.8 V, MBI = 0 1.62 V AVDD = 3.3 V, MBI = 0 2.97 V Bias Current Source AVDD = 3.3 V, MBI = 0, MPERF = 1 3 mA Noise in the Signal Bandwidth AVDD = 3.3 V, 1 kHz to 20 kHz MBI = 0, MPERF = 0 42 nV/√Hz MBI = 0, MPERF = 1 85 nV/√Hz MBI = 1, MPERF = 0 25 nV/√Hz MBI = 1, MPERF = 1 37 nV/√Hz DIGITAL-TO-ANALOG CONVERTERS DAC performance excludes mixers and headphone amplifier DAC Resolution All DACs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB DAC TO LINE OUTPUT Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.50 (1.41) V rms (V p-p) AVDD = 3.3 V 0.92 (2.60) V rms (V p-p) Analog Volume Control Step Line output volume control 0.75 dB Analog Volume Control Range Line output volume control −57 1 +6 dB Mute Attenuation −87 dB Dynamic Range 20 Hz to 20 kHz, −60 dB input, line output mode With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 101 dB No Filter (RMS) AVDD = 1.8 V 93.5 dB AVDD = 3.3 V 98 dB Total Harmonic Distortion + Noise −1 dBFS, line output mode dB AVDD = 1.8 V −90 dB AVDD = 3.3 V −92 dB Signal-to-Noise Ratio Line output mode With A-Weighted Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 101 dB No Filter (RMS) AVDD = 1.8 V 93.5 dB AVDD = 3.3 V 98 dB Power Supply Rejection Ratio CM capacitor = 20 μF 100 mV p-p @ 217 Hz 56 dB 100 mV p-p @ 1 kHz 70 dB Gain Error 3 % Interchannel Gain Mismatch 0.005 dB Offset Error 0 mV Interchannel Isolation 1 kHz, 0 dBFS input signal 100 dB

Page 8

Data Sheet ADAU1361 Rev. D | Page 7 of 80 Parameter Test Conditions/Comments Min Typ Max Unit DAC TO HEADPHONE/EARPIECE OUTPUT PO = output power per channel Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.50 (1.41) V rms (V p-p) AVDD = 3.3 V 0.92 (2.60) V rms (V p-p) Total Harmonic Distortion + Noise −4 dBFS 16 Ω load AVDD = 1.8 V, PO = 6.4 mW −76 dB AVDD = 3.3 V, PO = 21.1 mW −82 dB 32 Ω load AVDD = 1.8 V, PO = 3.8 mW −82 dB AVDD = 3.3 V, PO = 10.6 mW −82 dB Power Supply Rejection Ratio CM capacitor = 20 μF 100 mV p-p @ 217 Hz 56 dB 100 mV p-p @ 1 kHz 67 dB Interchannel Isolation 1 kHz, 0 dBFS input signal, 32 Ω load, AVDD = 3.3 V Referred to GND 73 dB Referred to CM (capless headphone mode) 50 dB REFERENCE Common-Mode Reference Output CM pin AVDD/2 V POWER SUPPLY SPECIFICATIONS Table 2. Parameter Test Conditions/Comments Min Typ Max Unit SUPPLIES Voltage DVDDOUT 1.56 V AVDD 1.8 3.3 3.65 V IOVDD 1.63 3.3 3.65 V Digital I/O Current (IOVDD = 1.8 V) 20 pF capacitive load on all digital pins Slave Mode fS = 48 kHz 0.25 mA fS = 96 kHz 0.48 mA fS = 8 kHz 0.07 mA Master Mode fS = 48 kHz 0.62 mA fS = 96 kHz 1.23 mA fS = 8 kHz 0.11 mA Digital I/O Current (IOVDD = 3.3 V) 20 pF capacitive load on all digital pins Slave Mode fS = 48 kHz 0.48 mA fS = 96 kHz 0.9 mA fS = 8 kHz 0.13 mA Master Mode fS = 48 kHz 1.51 mA fS = 96 kHz 3 mA fS = 8 kHz 0.27 mA Analog Current (AVDD) See Table 3

Page 9

ADAU1361 Data Sheet Rev. D | Page 8 of 80 TYPICAL CURRENT CONSUMPTION Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS, DAC input @ 0 dBFS. For total power consumption, add the IOVDD current listed in Table 2. Table 3. Operating Voltage Audio Path Clock Generation Typical AVDD Current Consumption (mA) AVDD = IOVDD = 3.3 V Record stereo differential to ADC Direct MCLK 5.24 Integer PLL 6.57 DAC stereo playback to line output (10 kΩ) Direct MCLK 5.55 Integer PLL 6.90 DAC stereo playback to headphone (16 Ω) Direct MCLK 55.5 Integer PLL 56.8 DAC stereo playback to headphone (32 Ω) Direct MCLK 30.9 Integer PLL 32.25 DAC stereo playback to capless headphone (32 Ω) Direct MCLK 56.75 Integer PLL 58 Record aux stereo bypass to line output (10 kΩ) Direct MCLK 1.9 Integer PLL 3.3 AVDD = IOVDD = 1.8 V Record stereo differential to ADC Direct MCLK 4.25 Integer PLL 5.55 DAC stereo playback to line output (10 kΩ) Direct MCLK 4.7 Integer PLL 5.7 DAC stereo playback to headphone (16 Ω) Direct MCLK 30.81 Integer PLL 32 DAC stereo playback to headphone (32 Ω) Direct MCLK 18.3 Integer PLL 19.5 DAC stereo playback to capless headphone (32 Ω) Direct MCLK 32.6 Integer PLL 33.7 Record aux stereo bypass to line output (10 kΩ) Direct MCLK 1.9 Integer PLL 3.07

Page 10

Data Sheet ADAU1361 Rev. D | Page 9 of 80 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to line output with 10 kΩ load. ADC input @ −1 dBFS, DAC input @ 0 dBFS. In Table 4, the mixer boost and power management conditions are set for MXBIAS[1:0], ADCBIAS[1:0], HPBIAS[1:0], and DACBIAS[1:0]. RBIAS[1:0] and PBIAS[1:0] do not have an extreme power saving mode and are therefore set for power saving mode in the extreme power saving rows in Table 4. Table 4. Operating Voltage Power Management Setting Mixer Boost Setting Typical AVDD Current Consumption (mA) Typical ADC THD + N (dB) Typical Line Output THD + N (dB) AVDD = IOVDD = 3.3 V Normal (default) Normal operation 9.6 −91 −92.5 Boost Level 1 9.75 −91.5 −92.5 Boost Level 2 9.92 −91.5 −92.5 Boost Level 3 10.25 −91.5 −92.5 Extreme power saving Normal operation 7.09 −84.5 −87 Boost Level 1 7.19 −84.8 −87.1 Boost Level 2 7.29 −84.8 −87.1 Boost Level 3 7.49 −85 −87.1 Power saving Normal operation 7.67 −89.5 −90 Boost Level 1 7.77 −89.5 −90 Boost Level 2 7.86 −89.8 −90 Boost Level 3 8.07 −89.8 −90 Enhanced performance Normal operation 10.55 −91 −93.5 Boost Level 1 10.74 −91 −93.5 Boost Level 2 10.93 −91 −93.5 Boost Level 3 11.33 −91 −93.5 AVDD = IOVDD = 1.8 V Normal (default) Normal operation 8.1 −88 −91.2 Boost Level 1 8.26 −88 −91.2 Boost Level 2 8.41 −88 −91.2 Boost Level 3 8.73 −88 −91.2 Extreme power saving Normal operation 5.73 −85 −86 Boost Level 1 5.82 −85.4 −86 Boost Level 2 5.91 −85.5 −86 Boost Level 3 6.1 −85.5 −86 Power saving Normal operation 6.27 −86 −89.4 Boost Level 1 6.36 −86.1 −89.5 Boost Level 2 6.46 −86.3 −89.5 Boost Level 3 6.65 −86.3 −89.5 Enhanced performance Normal operation 9.01 −88 −91.5 Boost Level 1 9.2 −88 −91.5 Boost Level 2 9.38 −88 −91.5 Boost Level 3 9.76 −88 −91.5

ADAU1361BCPZ Reviews

Average User Rating
5 / 5 (127)
★ ★ ★ ★ ★
5 ★
114
4 ★
13
3 ★
0
2 ★
0
1 ★
0

Write a Review

Not Rated
Thanks for Your Review!

Nehe***** Sahni

May 14, 2020

Received Quickly. Excellent Communication. Capacitors Look Excellent.

Ele*****Hunt

May 1, 2020

This was a useful assortment of product that filled in a parts gap that I had on my electronic workbench. Thank you.

Aad*****Shan

April 25, 2020

Worked very well! I would highly recommend buying.

Mich*****Tata

April 25, 2020

The order has arrived ahead of time, we appreciate it very much!! Thanks

Javi*****tone

April 24, 2020

What I like was it was shipped fast and no damage.

Mina*****lish

April 14, 2020

Very easy to find and order what I wanted. Being able to add multiple items in various quantities from an online catalog page with a simple click.

Emer*****Conway

April 12, 2020

Great condition, super kind person, quick shipping! and great price too!

Uri*****Sheth

April 10, 2020

As I said before, your crew rock's keep up the fantastic work as we need you out there.

Zaide*****erson

April 10, 2020

Your technical assistance and professionalism cannot be complained!

Rau*****ood

April 9, 2020

Very Quick,no problems - Thank you.

ADAU1361BCPZ Guarantees

Service Guarantee

Service Guarantees

We guarantee 100% customer satisfaction.

Our experienced sales team and tech support team back our services to satisfy all our customers.

Quality Guarantee

Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

ADAU1361BCPZ Packaging

Verify Products
Customized Labels
Professional Packaging
Sealing
Packing
Insepction

ADAU1361BCPZ Related Products

353WB6A480R 353WB6A480R CTS-Frequency Controls, OSC SMD HCMOS VCXO 48MHZ 5V, 6-SMD, No Lead, - View
hotSMBT2907AE6327HTSA1 SMBT2907AE6327HTSA1 Infineon Technologies, TRANS PNP 60V 0.6A SOT-23, TO-236-3, SC-59, SOT-23-3, - View
U11P1YCGES U11P1YCGES C&K, SWITCH TOGGLE SPDT 5A 120V, -, - View
PB22G02FNS PB22G02FNS C&K, SWITCH PUSHBUTTON, -, - View
Y1365V0206BA0W Y1365V0206BA0W Vishay Foil Resistors (Division of Vishay Precision Group), RES ARRAY 4 RES MULT OHM 8SOIC, 8-SOIC (0.154", 3.90mm Width), - View
768203472GPTR13 768203472GPTR13 CTS Resistor Products, RES ARRAY 10 RES 4.7K OHM 20SOIC, 20-SOIC (0.220", 5.59mm Width), - View
DWM-27-58-L-S-250 DWM-27-58-L-S-250 Samtec Inc., .050" BOARD SPACERS, -, - View
DC12.1202.003 DC12.1202.003 Schurter Inc., PWR ENT MOD RCPT IEC320-C14 PNL, -, - View
D38999/24WG11SC D38999/24WG11SC Souriau, CONN RCPT 11POS JAM NUT W/SCKT, -, - View
RE96FSD RE96FSD Vector Electronics, CONN 96PIN DIN FEMALE SLDER TAIL, -, - View
74AC20SC 74AC20SC ON Semiconductor, IC GATE NAND 2CH 4-INP 14SOIC, 14-SOIC (0.154", 3.90mm Width), - View
BD15HA5MEFJ-LBH2 BD15HA5MEFJ-LBH2 Rohm Semiconductor, IC REG LIN 1.5V 500MA 8HTSOP-J, 8-SOIC (0.154", 3.90mm Width) Exposed Pad, - View
Payment Methods
Delivery Services

Quick Inquiry

ADAU1361BCPZ

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

View the Certificates

Do you have any question about ADAU1361BCPZ?

+86-755-83210559 ext. 811 SalesDept@heisener.com heisener007 2354944915 Send Message

ADAU1361BCPZ Tags

  • ADAU1361BCPZ
  • ADAU1361BCPZ PDF
  • ADAU1361BCPZ datasheet
  • ADAU1361BCPZ specification
  • ADAU1361BCPZ image
  • Analog Devices Inc.
  • Analog Devices Inc. ADAU1361BCPZ
  • buy ADAU1361BCPZ
  • ADAU1361BCPZ price
  • ADAU1361BCPZ distributor
  • ADAU1361BCPZ supplier
  • ADAU1361BCPZ wholesales

ADAU1361BCPZ is Available in