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ADF4113BRU

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ADF4113BRU

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Part Number ADF4113BRU
Manufacturer Analog Devices Inc.
Description IC SYNTH PLL RF 4.0GHZ 16-TSSOP
Datasheet ADF4113BRU Datasheet
Package 16-TSSOP (0.173", 4.40mm Width)
In Stock 3,866 piece(s)
Unit Price $ 5.5555 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jan 21 - Jan 26 (Choose Expedited Shipping)
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Part Number # ADF4113BRU (Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADF4113BRU Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet ADF4113BRUDatasheet
Package16-TSSOP (0.173", 4.40mm Width)
Series-
TypeClock/Frequency Synthesizer (RF)
PLLYes
InputCMOS, TTL
OutputClock
Number of Circuits1
Ratio - Input:Output2:1
Differential - Input:OutputYes/No
Frequency - Max4GHz
Divider/MultiplierYes/No
Voltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case16-TSSOP (0.173", 4.40mm Width)
Supplier Device Package16-TSSOP

ADF4113BRU Datasheet

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RF PLL Frequency Synthesizers Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz; ADF4113: 4.0 GHz 2.7 V to 5.5 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode APPLICATIONS Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications test equipment CATV equipment GENERAL DESCRIPTION The ADF4110 family of frequency synthesizers can be used to implement local oscillators in the upconversion and downcon- version sections of wireless receivers and transmitters. They consist of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM N = BP + A FUNCTION LATCH PRESCALER P/P +1 13-BIT B COUNTER 6-BIT A COUNTER 14-BIT R COUNTER 24-BIT INPUT REGISTER R COUNTER LATCH A, B COUNTER LATCH PHASE FREQUENCY DETECTOR AVDD SDOUT 19 13 14 22 SDOUT FROM FUNCTION LATCH DGNDAGNDCE RFINA RFINB LE DATA CLK REFIN CPGNDVPDVDDAVDD LOCK DETECT ADF4110/ADF4111 ADF4112/ADF41136 LOAD LOAD REFERENCE CHARGE PUMP M3 M2 M1 HIGH Z MUX MUXOUT CP RSET CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 CURRENT SETTING 1 03 49 6- 0- 00 1 Figure 1. Functional Block Diagram

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ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ..................................................................... 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Circuit Description ......................................................................... 12 Reference Input Section ............................................................. 12 RF Input Stage ............................................................................. 12 Prescaler (P/P + 1) ...................................................................... 12 A and B Counters ....................................................................... 12 R Counter .................................................................................... 12 Phase Frequency Detector (PFD) and Charge Pump ............ 13 Muxout and Lock Detect ........................................................... 13 Input Shift Register .................................................................... 13 Function Latch ............................................................................ 19 Initialization Latch ..................................................................... 20 Device Programming after Initial Power-Up ......................... 20 Resynchronizing the Prescaler Output .................................... 21 Applications ..................................................................................... 22 Local Oscillator for GSM Base Station Transmitter .............. 22 Using a D/A Converter to Drive the RSET Pin ......................... 23 Shutdown Circuit ....................................................................... 23 Wideband PLL ............................................................................ 23 Direct Conversion Modulator .................................................. 25 Interfacing ................................................................................... 26 PCB Design Guidelines for Chip Scale Package .................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide ............................................................................... 28 REVISION HISTORY 1/13—Rev. E to Rev. F Changes to Table 1 ............................................................................. 4 Changes to Ordering Guide ........................................................... 28 8/12—Rev. D to Rev. E Changed CP-20-1 to CP-20-6 ........................................... Universal Updated Outline Dimensions ........................................................ 28 Changes to Ordering Guide ........................................................... 28 5/12—Rev. C to Rev. D Changes to Figure 2 ........................................................................... 5 Changes to Figure 4 and Table 4 ...................................................... 7 Updated Outline Dimensions ........................................................ 28 Changes to Ordering Guide ........................................................... 28 3/04—Data sheet changed from Rev. B to Rev. C. Updated Format .................................................................. Universal Changes to Specifications ................................................................. 2 Changes to Figure 32 ....................................................................... 22 Changes to the Ordering Guide ..................................................... 28 3/03—Data sheet changed from Rev. A to Rev. B. Edits to Specifications ....................................................................... 2 Updated OUTLINE DIMENSIONS ............................................. 24 1/01—Data sheet changed from Rev. 0 to Rev. A. Changes to DC Specifications in B Version, B Chips, Unit, and Test Conditions/Comments Columns ..................... 2 Changes to Absolute Maximum Rating ......................................... 4 Changes to FRINA Function Test ..................................................... 5 Changes to Figure 8 ........................................................................... 7 New Graph Added—TPC 22 ........................................................... 9 Change to PD Polarity Box in Table V ......................................... 15 Change to PD Polarity Box in Table VI ........................................ 16 Change to PD Polarity Paragraph ................................................. 17 Addition of New Material (PCB Design Guidelines for Chip–Scale package) ................ 23 Replacement of CP-20 Outline with CP-20 [2] Outline ............ 24

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Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 3 of 28 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C. Table 1. Parameter B Version B Chips1 Unit Test Conditions/Comments RF CHARACTERISTICS (3 V) See Figure 29 for input circuit. RF Input Sensitivity −15/0 −15/0 dBm min/max RF Input Frequency ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure slew rate (SR) > 30 V/µs. ADF4110 50/550 50/550 MHz min/max Input level = −10 dBm. ADF4111 0.08/1.2 0.08/1.2 GHz min/max For lower frequencies, ensure SR > 30 V/µs. ADF4112 0.2/3.0 0.2/3.0 GHz min/max For lower frequencies, ensure SR > 75 V/µs. ADF4112 0.1/3.0 0.1/3.0 GHz min/max Input level = −10 dBm. ADF4113 0.2/3.7 0.2/3.7 GHz min/max Input level = −10 dBm. For lower frequencies, ensure SR > 130 V/µs. Maximum Allowable Prescaler Output Frequency2 165 165 MHz max RF CHARACTERISTICS (5 V) RF Input Sensitivity −10/0 −10/0 dBm min/max RF Input Frequency ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure SR > 50 V/µs. ADF4111 0.08/1.4 0.08/1.4 GHz min/max For lower frequencies, ensure SR > 50 V/µs. ADF4112 0.1/3.0 0.1/3.0 GHz min/max For lower frequencies, ensure SR > 75 V/µs. ADF4113 0.2/3.7 0.2/3.7 GHz min/max For lower frequencies, ensure SR > 130 V/µs. ADF4113 0.2/4.0 0.2/4.0 GHz min/max Input level = −5 dBm. Maximum Allowable Prescaler Output Frequency2 200 200 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 5/104 5/104 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs. Reference Input Sensitivity 0.4/AVDD 0.4/AVDD V p-p min/max AVDD = 3.3 V, biased at AVDD/2. See Note 3. 3.0/AVDD 3.0/AVDD V p-p min/max AVDD = 5 V, biased at AVDD/2. See Note 3. REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max PHASE DETECTOR FREQUENCY4 55 55 MHz max CHARGE PUMP ICP Sink/Source Programmable (see Table 9). High Value 5 5 mA typ With RSET = 4.7 kΩ. Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With RSET = 4.7 kΩ. RSET Range 2.7/10 2.7/10 kΩ typ See Table 9. ICP 3-State Leakage Current 1 1 nA typ Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V. ICP vs. VCP 1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V. ICP vs. Temperature 2 2 % typ VCP = VP/2. LOGIC INPUTS VINH, Input High Voltage 0.8 × DVDD 0.8 × DVDD V min VINL, Input Low Voltage 0.2 × DVDD 0.2 × DVDD V max IINH/IINL, Input Current ±1 ±1 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA. VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA.

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ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 4 of 28 Parameter B Version B Chips1 Unit Test Conditions/Comments POWER SUPPLIES AVDD 2.7/5.5 2.7/5.5 V min/V max DVDD AVDD AVDD VP AVDD/6.0 AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26. IDD5 (AIDD + DIDD) ADF4110 5.5 4.5 mA max 4.5 mA typical. ADF4111 5.5 4.5 mA max 4.5 mA typical. ADF4112 7.5 6.5 mA max 6.5 mA typical. ADF4113 11 8.5 mA max 8.5 mA typical. IP 0.5 0.5 mA max TA = 25°C. Low Power Sleep Mode 1 1 µA typ NOISE CHARACTERISTICS ADF4113 Normalized Phase Noise Floor6 −215 −215 dBc/Hz typ Phase Noise Performance7 @ VCO output. ADF4110: 540 MHz Output8 −91 −91 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4111: 900 MHz Output9 −87 −87 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4112: 900 MHz Output9 −90 −90 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 900 MHz Output9 −91 −91 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4111: 836 MHz Output10 −78 −78 dBc/Hz typ @ 300 Hz offset and 30 kHz PFD frequency. ADF4112: 1750 MHz Output11 −86 −86 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4112: 1750 MHz Output12 −66 −66 dBc/Hz typ @ 200 Hz offset and 10 kHz PFD frequency. ADF4112: 1960 MHz Output13 −84 −84 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 1960 MHz Output13 −85 −85 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 3100 MHz Output14 −86 −86 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency. Spurious Signals ADF4110: 540 MHz Output9 −97/−106 −97/−106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4111: 900 MHz Output9 −98/−110 −98/−110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4112: 900 MHz Output9 −91/−100 −91/−100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 900 MHz Output9 −100/−110 −100/−110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4111: 836 MHz Output10 −81/−84 −81/−84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD frequency. ADF4112: 1750 MHz Output11 −88/−90 −88/−90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4112: 1750 MHz Output12 −65/−73 −65/−73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD frequency. ADF4112: 1960 MHz Output13 −80/−84 −80/−84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 1960 MHz Output13 −80/−84 −80/−84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 3100 MHz Output14 −80/−82 −82/−82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency. 1The B chip specifications are given as typical values. 2This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 3AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit. 4Guaranteed by design. 5 TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN. 7 The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7). 8 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz. 9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz. 11 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz 12 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz. 13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz. 14 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.

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Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 5 of 28 TIMING CHARACTERISTICS Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 10 ns min DATA to CLOCK setup time t2 10 ns min DATA to CLOCK hold time t3 25 ns min CLOCK high duration t4 25 ns min CLOCK low duration t5 10 ns min CLOCK to LE setup time t6 20 ns min LE pulse width CLOCK DATA LE LE DB23 (MSB) DB22 DB2 DB1(CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 t2 t3 t4 t5 t6 03 49 6- 00 2 Figure 2. Timing Diagram

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ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Table 3. Parameter Rating AVDD to GND1 −0.3 V to +7 V AVDD to DVDD −0.3 V to +0.3 V VP to GND −0.3 V to +7 V VP to AVDD −0.3 V to +5.5 V Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V RFINA to RFINB ±320 mV Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOP θJA Thermal Impedance 150.4°C/W LFCSP θJA Thermal Impedance (Paddle Soldered) 122°C/W LFCSP θJA Thermal Impedance (Paddle Not Soldered) 216°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 GND = AGND = DGND = 0 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. TRANSISTOR COUNT 6425 (CMOS) and 303 (Bipolar). ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 7 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DVDD MUXOUT LE VP DATA CLK CE DGND RSET CP CPGND AGND RFINB RFINA AVDD REFIN TOP VIEW (Not to Scale) ADF4110 ADF4111 ADF4112 ADF4113 03 49 6- 0- 00 3 03 49 6- 0- 00 4 NOTES 1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND. 14 13 12 1 3 4 LE 15 MUXOUT DATA CLK 11 CE CPGND AGND 2AGND RFINB 5RFINA 7 A V D D 6 A V D D 8 R EF IN 9 D G N D 10 D G N D 19 R SE T 20 C P 18 V P 17 D V D D 16 D V D D ADF4110 ADF4111 ADF4112 ADF4113 TOP VIEW (Not to Scale) Figure 3. TSSOP Pin Configuration Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions TSSOP Pin No. LFCSP Pin No. Mnemonic Function 1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is SET maxCP R I 5.23= So, with RSET = 4.7 kΩ, ICPmax = 5 mA. 2 20 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 5 4 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 29. 6 5 RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO. 7 6, 7 AVDD Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. 8 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device depending on the status of the power- down Bit F2. 11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. 13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. 14 15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. 15 16, 17 DVDD Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. 16 18 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1 EPAD Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.

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ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Rev. F | Page 8 of 28 TYPICAL PERFORMANCE CHARACTERISTICS FREQ PARAM DATA KEYWORD IMPEDANCE –UNIT –TYPE –FORMAT –OHMS GHz S MA R 50 FREQ MAGS11 ANGS11 1.05 0.9512 –40.134 1.10 0.93458 –43.747 1.15 0.94782 –44.393 1.20 0.96875 –46.937 1.25 0.92216 –49.6 1.30 0.93755 –51.884 1.35 0.96178 –51.21 1.40 0.94354 –53.55 1.45 0.95189 –56.786 1.50 0.97647 –58.781 1.55 0.98619 –60.545 1.60 0.95459 –61.43 1.65 0.97945 –61.241 1.70 0.98864 –64.051 1.75 0.97399 –66.19 1.80 0.97216 –63.775 FREQ MAGS11 ANGS11 0.05 0.89207 –2.0571 0.10 0.8886 –4.4427 0.15 0.89022 –6.3212 0.20 0.96323 –2.1393 0.25 0.90566 –12.13 0.30 0.90307 –13.52 0.35 0.89318 –15.746 0.40 0.89806 –18.056 0.45 0.89565 –19.693 0.50 0.88538 –22.246 0.55 0.89699 –24.336 0.60 0.89927 –25.948 0.65 0.87797 –28.457 0.70 0.90765 –29.735 0.75 0.88526 –31.879 0.80 0.81267 –32.681 0.85 0.90357 –31.522 0.90 0.92954 –34.222 0.95 0.92087 –36.961 1.00 0.93788 –39.343 03 49 6- 0- 00 5 Figure 5. S-Parameter Data for the ADF4113 RF Input (up to 1.8 GHz) –35 –30 –25 –20 –15 –10 –5 0 R F IN PU T PO W ER (d B m ) 0 1 2 3 4 5 RF INPUT FREQUENCY (GHz) 03 49 6- 0- 00 6 VDD = 3V VP = 3V TA = +85°C TA = +25°C TA = –40°C Figure 6. Input Sensitivity (ADF4113) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 O U TP U T PO W ER (d B ) –2.0kHz –1.0kHz 900MHz 1.0kHz 2.0kHz FREQUENCY 03 49 6- 0- 00 7 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 s AVERAGES = 19 REFERENCE LEVEL = –4.2dBm –91.0dBc/Hz Figure 7. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 O U TP U T PO W ER (d B ) –2.0kHz –1.0kHz 900MHz 1.0kHz 2.0kHz FREQUENCY 03 49 6- 0- 00 8 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 s AVERAGES = 19 REFERENCE LEVEL = –4.2dBm –92.5dBc/Hz Figure 8. ADF4113 Phase Noise (900 MHz, 200kHz, 20 kHz) with DLY and SYNC Enabled –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 PH A SE N O IS E (d B c/ H z) FREQUENCY OFFSET FROM 900MHz CARRIER (Hz) 1k100 10k 100k 1M 03 49 6- 0- 00 9 RMS NOISE = 0.52° RL = –40dBc/Hz Figure 9. ADF4113 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 µs) –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 PH A SE N O IS E (d B c/ H z) FREQUENCY OFFSET FROM 900MHz CARRIER (Hz) 1k100 10k 100k 1M 03 49 6- 0- 01 0 RMS NOISE = 0.62° RL = –40dBc/Hz Figure 10. ADF4113 Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 µs)

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Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 9 of 28 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 O U TP U T PO W ER (d B ) –400kHz –200kHz 900MHz 200kHz 400kHz FREQUENCY 03 49 6- 0- 01 1 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5s AVERAGES = 30 REFERENCE LEVEL = –4.2dBm –90.2dBc/Hz Figure 11. ADF4113 Reference Spurs (900 MHz, 200 kHz, 20 kHz) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 O U TP U T PO W ER (d B ) –400kHz –200kHz 900MHz 200kHz 400kHz FREQUENCY 03 49 6- 0- 01 2 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 35kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5s AVERAGES = 30 REFERENCE LEVEL = –4.2dBm –89.3dBc/Hz Figure 12. ADF4113 (900 MHz, 200 kHz, 35 kHz) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 O U TP U T PO W ER (d B ) –400Hz –200Hz 1750MHz 200Hz 400Hz FREQUENCY 03 49 6- 0- 01 3 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 477ms AVERAGES = 10 REFERENCE LEVEL = –8.0dBm –75.2dBc/Hz Figure 13. ADF4113 Phase Noise (1750 MHz, 30 kHz, 3 kHz) –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 PH A SE N O IS E (d B c/ H z) FREQUENCY OFFSET FROM 1750MHz CARRIER (Hz) 1k100 10k 100k 1M 03 49 6- 0- 01 4 RMS NOISE = 1.6° RL = –40dBc/Hz Figure 14. ADF4113 Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 O U TP U T PO W ER (d B ) –80kHz –40kHz 1750MHz 40kHz 80kHz FREQUENCY 03 49 6- 0- 01 5 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 3Hz VIDEO BANDWIDTH = 3Hz SWEEP = 255s POSITIVE PEEK DETECT MODE REFERENCE LEVEL = –5.7dBm –79.6dBc/Hz Figure 15. ADF4113 Reference Spurs (1750 MHz, 30 kHz, 3 kHz) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 O U TP U T PO W ER (d B ) –2.0kHz –1.0kHz 3100MHz 1.0kHz 2.0kHz FREQUENCY 03 49 6- 0- 01 6 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9s AVERAGES = 45 REFERENCE LEVEL = –4.2dBm –86.6dBc/Hz Figure 16. ADF4113 Phase Noise (3100 MHz, 1 MHz, 100 kHz)

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