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ADM6320CZ29ARJZ-R7

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ADM6320CZ29ARJZ-R7

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Part Number ADM6320CZ29ARJZ-R7
Manufacturer Analog Devices Inc.
Description IC SUPERVISOR WATCHDOG SOT23-5
Datasheet ADM6320CZ29ARJZ-R7 Datasheet
Package SC-74A, SOT-753
In Stock 7,074 piece(s)
Unit Price $ 0.7090 *
Lead Time Can Ship Immediately
Estimated Delivery Time Nov 2 - Nov 7 (Choose Expedited Shipping)
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Part Number # ADM6320CZ29ARJZ-R7 (PMIC - Supervisors) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADM6320CZ29ARJZ-R7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - PMIC - Supervisors
Datasheet ADM6320CZ29ARJZ-R7Datasheet
PackageSC-74A, SOT-753
Series-
TypeSimple Reset/Power-On Reset
Number of Voltages Monitored1
OutputOpen Drain or Open Collector
ResetActive Low
Reset Timeout140 ms Minimum
Voltage - Threshold2.93V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / CaseSC-74A, SOT-753
Supplier Device PackageSOT-23-5

ADM6320CZ29ARJZ-R7 Datasheet

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Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23 Data Sheet ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 26 reset threshold options 2.5 V to 5 V in 100 mV increments 4 reset timeout options 1 ms, 20 ms, 140 ms, and 1120 ms (minimum) 4 watchdog timeout options 6.3 ms, 102 ms, 1600 ms, and 25.6 sec (typical) Manual reset input Reset output stages Push-pull active low Open-drain active low Push-pull active high Low power consumption: 5 µA Guaranteed reset output valid to VCC = 1 V Power supply glitch immunity Specified over industrial temperature range 5-lead SOT-23 package APPLICATIONS Microprocessor systems Computers Controllers Intelligent instruments Portable equipment FUNCTIONAL BLOCK DIAGRAMS ADM6316 VCC VCC MR GND WDI RESETRESETGENERATOR WATCHDOG DETECTOR DEBOUNCE VREF 04 53 3- 00 1 Figure 1. ADM6320 VCC MR GND WDI RESETRESETGENERATOR WATCHDOG DETECTOR DEBOUNCE VREF 04 53 3- 02 8 Figure 2. GENERAL DESCRIPTION The ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ ADM6321/ADM6322 are supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. As well as providing power-on reset signals, an on-chip watchdog timer can reset the micro- processor if it fails to strobe within a preset timeout period. A reset signal can also be asserted by an external push button through a manual reset input. The seven devices feature different combinations of watchdog input, manual reset input, and output stage configuration, as shown in Table 1. Each device is available in a choice of 26 reset threshold options ranging from 2.5 V to 5 V in 100 mV increments. There are also four reset timeout options of 1 ms, 20 ms, 140 ms, and 1120 ms (minimum) and four watchdog timeout options of 6.3 ms, 102 ms, 1600 ms, and 25.6 sec (typical). Not all device options are released for sale as standard models. See the Ordering Guide for details. The ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ ADM6321/ADM6322 are available in 5-lead SOT-23 packages and typically consume only 3 µA, making them suitable for use in low power portable applications. Table 1. Selection Table Part No. Watchdog Manual Reset Output Stage RESET RESET ADM6316 Yes Yes Push-pull No ADM6317 Yes Yes No Push-pull ADM6318 Yes No Push-pull Push-pull ADM6319 No Yes Push-pull Push-pull ADM6320 Yes Yes Open-drain No ADM6321 Yes No Open-drain Push-pull ADM6322 No Yes Open-drain Push-pull

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ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Data Sheet Rev. I | Page 2 of 14 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagrams ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description ........................................................................... 9 Reset Output ................................................................................. 9 Open-Drain RESET Output ........................................................9 Manual Reset Input .......................................................................9 Watchdog Input .............................................................................9 Applications Information .............................................................. 10 Watchdog Input Current ........................................................... 10 Negative Going VCC Transients ................................................. 10 Ensuring Reset Valid to VCC = 0 V ........................................... 10 Watchdog Software Considerations ......................................... 10 Device Model Options ................................................................... 11 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13 REVISION HISTORY 3/2018—Rev. H to Rev. I Changes to General Description Section ...................................... 1 Added Note 1, Table 2 ...................................................................... 3 Changed Model Options Section to Device Model Options Section .............................................................................................. 11 Changes to Device Model Options Section and Table 5 ........... 11 Deleted Table 8; Renumbered Sequentially ................................ 12 Changes to Ordering Guide .......................................................... 13 12/2015—Rev. G to Rev. H Added Endnote 1 and Endnote 2, Table 2 ..................................... 3 Change to Model Options Section Title ...................................... 11 Added Endnote 1, Table 5 ............................................................. 11 Changes to Table 8 .......................................................................... 12 Changes to Ordering Guide .......................................................... 14 1/2015—Rev. F to Rev. G Changes to Table 8 .......................................................................... 12 5/2013—Rev. E to Rev. F Changes to Table 8 .......................................................................... 12 Changes to Ordering Guide .......................................................... 13 10/2010—Rev. D to Rev. E Changes to Table 8 .......................................................................... 12 Updated Outline Dimensions ....................................................... 13 8/2008—Rev. C to Rev. D Change to Figure 18 ......................................................................... 9 4/2007—Rev. B to Rev. C Added Figure 2 ................................................................................... 1 Changes to Figure 23 ...................................................................... 13 Changes to Ordering Guide .......................................................... 13 1/2007—Rev. A to Rev. B Changes to Functional Block Diagram ........................................... 1 Changes to Figure 18 ...................................................................... 10 5/2006—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Functional Block Diagram ........................................... 1 Changes to Table 8 .......................................................................... 12 Changes to Figure 22 ...................................................................... 13 Changes to Ordering Guide .......................................................... 13 10/2004—Revision 0: Initial Version

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Data Sheet ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Rev. I | Page 3 of 14 SPECIFICATIONS VCC = full operating range, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VCC Operating Voltage Range 1 5.5 V Supply Current 10 20 µA VCC = 5.5 V 5 12 µA VCC = 3.6 V RESET THRESHOLD VOLTAGE1 VTH − 1.5% VTH VTH + 1.5% V TA = 25°C VTH − 2.5% VTH VTH + 2.5% V TA = −40°C to +85°C RESET THRESHOLD TEMPERATURE COEFFICIENT 40 ppm/°C RESET THRESHOLD HYSTERESIS 3 mV RESET TIMEOUT PERIOD1 ADM63xxA2 1 1.4 2 ms ADM63xxB2 20 28 40 ms ADM63xxC2 140 200 280 ms ADM63xxD2 1120 1600 2240 ms VCC TO RESET DELAY 40 µs VCC falling at 1 mV/µs PUSH-PULL OUTPUT (ADM6316, ADM6317, ADM6318, ADM6319, ADM6321, ADM6322) RESET Output Voltage 0.3 V VCC ≥ 1.0 V, ISINK = 50 µA 0.3 V VCC ≥ 1.2 V, ISINK = 100 µA 0.3 V VCC ≥ 2.7 V, ISINK = 1.2 mA 0.4 V VCC ≥ 4.5 V, ISINK = 3.2 mA 0.8 × VCC V VCC ≥ 2.7 V, ISOURCE = 500 µA VCC − 1.5 V VCC ≥ 4.5 V, ISOURCE = 800 µA RESET Rise Time 5 25 ns From 10% to 90% VCC, CL = 5 pF, VCC = 3.3 V RESET Output Voltage 0.3 V VCC ≥ 2.7 V, ISINK = 1.2 mA 0.4 V VCC ≥ 4.5 V, ISINK = 3.2 mA 0.8 × VCC V VCC ≥ 1.8 V, ISOURCE = 150 µA 0.8 × VCC V VCC ≥ 2.7 V, ISOURCE = 500 µA VCC − 1.5 V VCC ≥ 4.5 V, ISOURCE = 800 µA OPEN-DRAIN OUTPUT (ADM6320, ADM6321, ADM6322) RESET Output Voltage 0.3 V VCC ≥ 1.0 V, ISINK = 50 µA 0.3 V VCC ≥ 1.2 V, ISINK = 100 µA 0.3 V VCC ≥ 2.7 V, ISINK = 1.2 mA 0.4 V VCC ≥ 4.5 V, ISINK = 3.2 mA Open-Drain Reset Output Leakage Current 1 µA WATCHDOG INPUT (ADM6316, ADM6317, ADM6318, ADM6320, ADM6321) Watchdog Timeout Period1 ADM63xxxW3 4.3 6.3 9.3 ms ADM63xxxX3 71 102 153 ms ADM63xxxY3 1.12 1.6 2.4 sec ADM63xxxZ3 17.9 25.6 38.4 sec WDI Pulse Width 50 ns VIL = 0.3 × VCC, VIH = 0.7 × VCC WDI Input Threshold 0.3 × VCC 0.7 × VCC V WDI Input Current 120 160 µA VWDI = VCC, time average −20 −15 µA VWDI = 0, time average

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ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Data Sheet Rev. I | Page 4 of 14 Parameter Min Typ Max Unit Test Conditions/Comments MANUAL RESET INPUT (ADM6316, ADM6317, ADM6319, ADM6320, ADM6322) MR Input Threshold 0.8 2.0 V VTH > 4.0 V 0.3 × VCC 0.7 × VCC V VTH < 4.0 V MR Input Pulse Width 1 µs MR Glitch Rejection 100 ns MR Pull-Up Resistance 35 52 75 kΩ MR to Reset Delay 230 ns VCC = 5 V 1 Not all device options are released for sale as standard models. See the Ordering Guide for full details. 2 Complete the model code by replacing xx with a device generic number. 3 Complete the model code by replacing xxx with a device generic number and code for the reset timeout period.

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Data Sheet ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Rev. I | Page 5 of 14 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VCC −0.3 V to +6 V RESET (ADM6320, ADM6321, ADM6322) −0.3 V to +6 V All Other Pins −0.3 V to (VCC + 0.3 V) Output Current (RESET, RESET) 20 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C θJA Thermal Impedance, SOT-23 270°C/W Lead Temperature Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

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ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Data Sheet Rev. I | Page 6 of 14 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADM6316/ ADM6320 TOP VIEW (Not to Scale) RESET 1 GND 2 MR 3 VCC WDI 5 4 04 53 3- 00 2 Figure 3. ADM6316/ADM6320 Pin Configuration ADM6317 TOP VIEW (Not to Scale) RESET 1 GND 2 MR 3 VCC WDI 5 4 04 53 3- 00 3 Figure 4. ADM6317 Pin Configuration ADM6318/ ADM6321 TOP VIEW (Not to Scale) RESET 1 GND 2 RESET 3 VCC WDI 5 4 04 53 3- 00 4 Figure 5. ADM6318/ADM6321 Pin Configuration ADM6319/ ADM6322 TOP VIEW (Not to Scale) RESET 1 GND 2 RESET 3 VCC MR 5 4 04 53 3- 00 5 Figure 6. ADM6319/ADM6322 Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 RESET (ADM6316/ADM6318/ADM6319/ ADM6320/ADM6321/ADM6322) Active Low Reset Output. Asserted whenever VCC is below the reset threshold, VTH. Push-Pull Output Stage for the ADM6316/ADM6318/ADM6319. Open-Drain Output Stage for the ADM6320/ADM6321/ADM6322. RESET (ADM6317) Active High Push-Pull Reset Output. 2 GND (all models) Ground. 3 MR (ADM6316/ADM6317/ADM6320) Manual Reset Input. This is an active low input that when forced low for at least 1 µs, generates a reset. It features a 52 kΩ internal pull-up. RESET (ADM6318/ADM6319/ADM6321/ADM6322) Active High Push-Pull Reset Output. 4 WDI (ADM6316/ADM6317/ADM6318/ ADM6320/ADM6321) Watchdog Input. Generates a reset if the logic level on the pin remains low or high for the duration of the watchdog timeout. The timer is cleared if a logic transition occurs on this pin or if a reset is generated. Leave this pin floating to disable the watchdog timer. MR (ADM6319/ADM6322) Manual Reset Input. 5 VCC (all models) Power Supply Voltage Being Monitored.

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Data Sheet ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Rev. I | Page 7 of 14 TYPICAL PERFORMANCE CHARACTERISTICS TEMPERATURE (°C) –40 –20 0 20 40 60 80 I C C (µ A ) 10.0 9.0 9.5 8.0 7.5 8.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 VCC = 5V VCC = 3V VCC = 1.5V 04 53 3- 00 6 Figure 7. Supply Current vs. Temperature (ADM6316/ADM6317/ADM6318/ADM6320/ADM6321) VCC (V) 5.50 2.01.51.00.5 2.5 3.0 3.5 4.0 4.5 5.0 I C C (µ A ) 80 70 75 60 55 65 50 45 40 35 30 20 10 25 15 5 0 04 53 3- 00 7 Figure 8. Supply Current vs. Supply Voltage TEMPERATURE (°C) –40 40200–20 60 80 N O R M A LI ZE D R ES ET T H R ES H O LD 1.05 1.03 1.04 1.01 1.00 1.02 0.99 0.98 0.97 0.96 0.95 04 53 3- 00 8 Figure 9. Normalized Reset Threshold vs. Temperature TEMPERATURE (°C) –40 40200–20 60 80 V C C T O R ES ET D EL A Y (µ s) 100 80 90 60 50 70 40 30 20 10 0 04 53 3- 00 9 Figure 10. VCC Falling to Reset Propagation Delay vs. Temperature TEMPERATURE (°C) –40 40200–20 60 80 M A N U A L R ES ET T O R ES ET D EL A Y (n s) 340 300 320 260 240 280 220 200 180 160 140 120 100 04 53 3- 01 0 Figure 11. Manual Reset to Reset Propagation Delay vs. Temperature (ADM6316/ADM6317/ADM6319/ADM6320/ADM6322) TEMPERATURE (°C) –40 40200–20 60 80 N O R M A LI ZE D R ES ET T IM EO U T 1.20 1.10 1.15 1.00 0.95 1.05 0.90 0.85 0.80 04 53 3- 01 1 Figure 12. Normalized Reset Timeout Period vs. Temperature

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ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Data Sheet Rev. I | Page 8 of 14 TEMPERATURE (°C) –40 6040 80200–20 N O R M A LI ZE D W A TC H D O G T IM EO U T 1.20 1.15 1.10 1.05 1.00 0.95 0.90 04 53 3- 01 2 Figure 13. Normalized Watchdog Timeout Period vs. Temperature (ADM6316/ADM6317/ADM6318/ADM6320/ADM6321) OVERDRIVE VOLTAGE (mV) 100010 100 M A XI M U M T R A N SI EN T D U R A TI O N (µ s) 160 120 140 100 60 80 40 20 0 VTH = 4.63V VTH = 2.93V RESET OCCURS ABOVE CURVE 04 53 3- 01 3 Figure 14. Maximum VCC Transient Duration vs. Reset Threshold Overdrive TEMPERATURE (°C) –50 0 50 M R M IN IM U M P U LS E W ID TH (n s) 190 160 180 170 150 130 140 120 110 100 04 53 3- 01 4 Figure 15. Manual Reset Minimum Pulse Width vs. Temperature (ADM6316/ADM6317/ADM6319/ADM6320/ADM6322) TEMPERATURE (°C) –40 10 60 M IN IM U M P U LS E W ID TH (n s) 3.8 3.2 3.6 3.4 3.0 2.6 2.8 2.4 2.2 2.0 NEGATIVE PULSE POSITIVE PULSE 04 53 3- 01 5 Figure 16. Watchdog Input Minimum Pulse Width vs. Temperature (ADM6316/ADM6317/ADM6318/ADM6320/ADM6321)

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Data Sheet ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322 Rev. I | Page 9 of 14 CIRCUIT DESCRIPTION The ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ ADM6321/ADM6322 provide microprocessor supply voltage supervision by controlling the reset input of the microprocessor. Code execution errors are avoided during power-up, power-down, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. In addition, problems with microprocessor code execution can be monitored and corrected with a watchdog timer (ADM6316/ADM6317/ ADM6318/ADM6320/ADM6321). If the user detects a problem with the system’s operation, a manual reset input is available (ADM6316/ADM6317/ADM6319/ADM6320/ADM6322) to reset the microprocessor, for example, by means of an external push button. RESET OUTPUT The ADM6316 features an active low push-pull reset output, while the ADM6317/ADM6321/ADM6322 have active high push-pull reset outputs. The ADM6318/ADM6319 feature dual active low and active high push-pull reset outputs. For active low and active high outputs, the reset signal is guaranteed to be logic low and logic high, respectively, for VCC down to 1 V. The reset output is asserted when VCC is below the reset thresh- old (VTH), when MR is driven low, or when WDI is not serviced within the watchdog timeout period (tWD). Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold, after MR transitions from low to high, or after the watchdog timer times out. Figure 17 illustrates the behavior of the reset outputs. VCC 1V VCC 0V VCC 0V VTH VTH 0V VCC RESET RESET tRD tRD1V tRP tRP 0 4 5 3 3- 0 1 9 Figure 17. Reset Timing Diagram OPEN-DRAIN RESET OUTPUT The ADM6320/ADM6321/ADM6322 have an active low, open- drain reset output. This output structure requires an external pull-up resistor to connect the reset output to a voltage rail no higher than 6 V. The resistor must comply with the micro- processor’s logic low and logic high voltage level requirements while supplying input current and leakage paths on the RESET line. A 10 kΩ resistor is adequate in most situations. MANUAL RESET INPUT The ADM6316/ADM6317/ADM6319/ADM6320/ADM6322 feature a manual reset input (MR), which when driven low, asserts the reset output. When MR transitions from low to high, reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 52 kΩ, internal pull-up so that the input is always high when unconnected. An external push-button switch can be connected between MR and ground so that the user can generate a reset. Debounce circuitry for this purpose is integrated on chip. Noise immunity is provided on the MR input, and fast, negative going transients of up to 100 ns (typical) are ignored. A 0.1 μF capacitor between MR and ground provides additional noise immunity. WATCHDOG INPUT The ADM6316/ADM6317/ADM6318/ADM6320/ADM6321 feature a watchdog timer that monitors microprocessor activity. A timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI), which detects pulses as short as 50 ns. If the timer counts through the preset watchdog timeout period (tWD), reset is asserted. The micro- processor is required to toggle the WDI pin to avoid being reset. Failure of the microprocessor to toggle WDI within the timeout period, therefore, indicates a code execution error, and the reset pulse generated restarts the microprocessor in a known state. As well as logic transitions on WDI, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on VCC or due to MR being pulled low. When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. The watchdog timer can be disabled by leaving WDI floating or by three-stating the WDI driver. VCC 1V VCC 0V VCC 0V VTH 0V VCC WDI RESET tRP tRPtWD 0 45 3 3 -0 2 2 Figure 18. Watchdog Timing Diagram

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