Contact Us
SalesDept@heisener.com +86-755-83210559 ext. 811

ADSP-21489KSWZ-4A

hotADSP-21489KSWZ-4A

ADSP-21489KSWZ-4A

For Reference Only

Part Number ADSP-21489KSWZ-4A
Manufacturer Analog Devices Inc.
Description IC CCD SIGNAL PROCESSOR 100LQFP
Datasheet ADSP-21489KSWZ-4A Datasheet
Package 100-LQFP Exposed Pad
In Stock 274 piece(s)
Unit Price $ 23.8000 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 8 - Jun 13 (Choose Expedited Shipping)
Request for Quotation

Part Number # ADSP-21489KSWZ-4A (Embedded - DSP (Digital Signal Processors)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For ADSP-21489KSWZ-4A specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add ADSP-21489KSWZ-4A with quantity into BOM. Heisener.com does NOT require any registration to request a quote of ADSP-21489KSWZ-4A.

ADSP-21489KSWZ-4A Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Embedded - DSP (Digital Signal Processors)
Datasheet ADSP-21489KSWZ-4ADatasheet
Package100-LQFP Exposed Pad
SeriesSHARC?
TypeFloating Point
InterfaceEBI/EMI, DAI, I2C, SPI, SPORT, UART/USART
Clock Rate400MHz
Non-Volatile MemoryExternal
On-Chip RAM5Mbit
Voltage - I/O3.30V
Voltage - Core1.10V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case100-LQFP Exposed Pad
Supplier Device Package100-LQFP-EP (14x14)

ADSP-21489KSWZ-4A Datasheet

Page 1

Page 2

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC Processor ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip ROM Up to 450 MHz operating frequency Code compatible with all other members of the SHARC family The ADSP-2148x processors are available with unique audio- centric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more For complete ordering information, see Ordering Guide on Page 69 Qualified for automotive applications Figure 1. Functional Block Diagram Internal Memory I/F Block 0 RAM/ROM B0D 64-BIT Instruction Cache 5 Stage Sequencer PEx PEy PMD 64-BIT IOD0 32-BITEPD BUS 64-BIT Core Bus Cross Bar DAI Routing/Pins S/PDIF Tx/Rx PCG A-D DPI Routing/Pins SPI/B UART Block 1 RAM/ROM Block 2 RAM Block 3 RAM AMI SDRAM CTL EP External Port Pin MUX TIMER 1-0 SPORT 7-0 ASRC 3-0 PWM 3-0 DAG1/2 Core Timer PDAP/ IDP 7-0 TWI IOD0 BUS DTCP/ MTM PCG C-D PERIPHERAL BUS 32-BIT CORE FLAGS/ PWM3-1 JTAG Internal Memory DMD 64-BIT PMD 64-BIT CORE FLAGS IOD1 32-BIT PERIPHERAL BUS B1D 64-BIT B2D 64-BIT B3D 64-BIT DPI Peripherals DAI Peripherals Peripherals External Port SIMD Core S THERMAL DIODE FFT FIR IIR SPEP BUS DMD 64-BIT FLAGx/IRQx/ TMREXP WDT

Page 3

Rev. F | Page 2 of 70 | June 2018 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 TABLE OF CONTENTS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Family Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Family Peripheral Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I/O Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Related Signal Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 88-Lead LFCSP_VQ Lead Assignment . . . . . . . . . . . . . . . . . . . . . . . . . 58 100-Lead LQFP_EP Lead Assignment . . . . . . . . . . . . . . . . . . . . . . . . . 60 176-Lead LQFP_EP Lead Assignment . . . . . . . . . . . . . . . . . . . . . . . . . 62 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Surface-Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 REVISION HISTORY 6/2018—Rev. E to Rev. F Changes to Table 2, ADSP-2148x Family Features . . . . . . . . . . . .3 Added Junction Temperature Specification for 88-Lead LFCSP_VQ Package, Operating Conditions . . . . . . . . . . . . . . . . . . 18 Deleted Nonapplicable TJ Specification for 100-Lead LQFP_EP, Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Deleted Package Information from Specifications . . . . . . . . . . . 18 Added Table 55, Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 56 Added 88-Lead LFCSP_VQ Lead Assignment . . . . . . . . . . . . . . . . 58 Changes to Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Added Figure 54, Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 66 Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Page 4

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. F | Page 3 of 70 | June 2018 GENERAL DESCRIPTION The ADSP-2148x SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2148x pro- cessors are 32-bit/40-bit floating point processors optimized for high performance audio applications with large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). Table 1 shows performance benchmarks for the ADSP-2148x processors. Table 2 shows the features of the individual product offerings. Table 1. Processor Benchmarks Benchmark Algorithm Speed (at 400 MHz) Speed (at 450 MHz) 1024 Point Complex FFT (Radix 4, with Reversal) 23 μs 20.44 μs FIR Filter (per Tap)1 1.25 ns 1.1 ns IIR Filter (per Biquad)1 5 ns 4.43 ns Matrix Multiply (Pipelined) [3 × 3] × [3 × 1] [4 × 4] × [4 × 1] 11.25 ns 20 ns 10.0 ns 17.78 ns Divide (y/×) 7.5 ns 6.67 ns Inverse Square Root 11.25 ns 10.0 ns 1 Assumes two files in multichannel SIMD mode Table 2. ADSP-2148x Family Features Feature ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489 Maximum Instruction Rate 400 MHz 400 MHz 450 MHz 400 MHz 450 MHz RAM 3 Mbits 5 Mbits 2/3 Mbits1 5 Mbits ROM 4 Mbits No Audio Decoders in ROM2 Yes No Pulse-Width Modulation 4 Units (3 Units on 100-Lead Packages) DTCP Hardware Accelerator Contact Analog Devices External Port Interface (SDRAM, AMI)3 Yes (16-bit) AMI Only Yes (16-bit) Serial Ports 8 Direct DMA from SPORTs to External Port (External Memory) Yes FIR, IIR, FFT Accelerator Yes Watchdog Timer Yes (176-Lead Package Only) MediaLB Interface Automotive Models Only IDP/PDAP Yes UART 1 DAI (SRU)/DPI (SRU2) Yes S/PDIF Transceiver Yes SPI Yes TWI 1 SRC Performance4 –128 dB Thermal Diode Yes VISA Support Yes Package3 176-Lead LQFP EPAD 100-Lead LQFP EPAD 176-Lead LQFP EPAD 88-Lead LFCSP5 176-Lead LQFP EPAD 100-Lead LQFP EPAD 176-Lead LQFP EPAD 100-Lead LQFP EPAD5 88-Lead LFCSP5 1 See Ordering Guide on Page 69. 2 ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 3 The 100-lead and 88-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP Lead Assignment on page 62. 4 Some models have –140 dB performance. For more information, see Ordering Guide on page 69. 5 Only available up to 400 MHz. See Ordering Guide on Page 69 for details.

Page 5

Rev. F | Page 4 of 70 | June 2018 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 The diagram on Page 1 shows the two clock domains that make up the ADSP-2148x processors. The core clock domain contains the following features: • Two processing elements (PEx, PEy), each of which com- prises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting 2x64-bit data transfers between memory and the core at every core pro- cessor cycle • One periodic interval timer with pinout • On-chip SRAM (5 Mbit) and mask-programmable ROM (4 Mbit) • JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user break- points which allows flexible exception handling. The block diagram of the ADSP-2148x on Page 1 also shows the peripheral clock domain (also known as the I/O processor) which contains the following features: • IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers • Peripheral and external port buses for core connection • External port with an AMI and SDRAM controller • 4 units for PWM control • 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers • Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP) for serial and parallel interconnects, an S/PDIF receiver/transmitter, four asynchronous sample rate con- verters, eight serial ports, and a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes two timers, a 2-wire interface (TWI), one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG), pulse width modulation (PWM), and a flexible signal routing unit (DPI SRU2). As shown in the SHARC core block diagram on Page 5, the processor uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. With its SIMD computational hard- ware, the processors can perform 2.7 GFLOPS running at 450 MHz. FAMILY CORE ARCHITECTURE The ADSP-2148x is code compatible at the assembly level with the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2148x shares architectural features with the ADSP-2126x, ADSP- 2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the fol- lowing sections. SIMD Computational Engine The ADSP-2148x contains two computational processing ele- ments that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and reg- ister file. PEx is always active, and PEy may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. SIMD mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also dou- bles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or reg- ister file access. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle and are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both pro- cessing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision float- ing-point, and 32-bit fixed-point data formats. Timer The processor contains a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal. Data Register File Each processing element contains a general-purpose data regis- ter file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context Switch Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register.

Page 6

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. F | Page 5 of 70 | June 2018 Universal Registers These registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all peripheral registers (control/status). The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference. Single-Cycle Fetch of Instruction and Four Operands The ADSP-2148x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro- gram memory (PM) bus transfers both instructions and data. With the its separate program and data memory buses and on- chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second- ary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the processor can conditionally execute a multiply, an add, and a Figure 2. SHARC Core Block Diagram S SIMD Core CACHEINTERRUPT 5 STAGE PROGRAM SEQUENCER PM ADDRESS 32 DM ADDRESS 32 DM DATA 64 PM DATA 64 DAG1 16x32 MRF 80-BIT ALUMULTIPLIER SHIFTER RF Rx/Fx PEx 16x40-BIT JTAG DMD/PMD 64 PM DATA 48 ASTATx STYKx ASTATy STYKy TIMER RF Sx/SFx PEy 16x40-BIT MRB 80-BIT MSB 80-BIT MSF 80-BIT FLAG SYSTEM I/F USTAT 4x32-BIT PX 64-BIT DAG2 16x32 MULTIPLIER DATA SWAP PM ADDRESS 24 ALU SHIFTER

Page 7

Rev. F | Page 6 of 70 | June 2018 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory, all in a single instruction. Variable Instruction Set Architecture (VISA) In addition to supporting the standard 48-bit instructions from previous SHARC processors, the ADSP-2148x supports new instructions of 16 and 32 bits. This feature, called Variable Instruction Set Architecture (VISA), drops redundant/unused bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external SDRAM memory. This support is not extended to the asynchronous memory interface (AMI). Source modules need to be built using the VISA option, in order to allow code genera- tion tools to create these more efficient opcodes. On-Chip Memory The ADSP-21483 and the ADSP-21488 processors contain 3 Mbits of internal RAM (Table 3) and the ADSP-21486, ADSP-21487, and ADSP-21489 processors contain 5 Mbits of internal RAM (Table 4). Each memory block supports single- cycle, independent accesses by the core processor and I/O processor. The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively dou- bles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each mem- ory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The memory maps in Table 3 and Table 4 display the internal memory address space of the processors. The 48-bit space sec- tion describes what this address range looks like to an Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)1 IOP Registers 0x0000 0000–0x0003 FFFF Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9 Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0004 8000–0x0004 8FFF Reserved 0x0008 AAAA–0x0008 BFFF Reserved 0x0009 0000–0x0009 1FFF Reserved 0x0012 0000–0x0012 3FFF Block 0 SRAM 0x0004 9000–0x0004 CFFF Block 0 SRAM 0x0008 C000–0x0009 1554 Block 0 SRAM 0x0009 2000–0x0009 9FFF Block 0 SRAM 0x0012 4000–0x0013 3FFF Reserved 0x0004 D000–0x0004 FFFF Reserved 0x0009 1555–0x0009 FFFF Reserved 0x0009 A000–0x0009 FFFF Reserved 0x0013 4000–0x0013 FFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 Block 1 ROM (Reserved) 0x000A 0000–0x000A FFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0005 8000–0x0005 8FFF Reserved 0x000A AAAA–0x000A BFFF Reserved 0x000B 0000–0x000B 1FFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0005 9000–0x0005 CFFF Block 1 SRAM 0x000A C000–0x000B 1554 Block 1 SRAM 0x000B 2000–0x000B 9FFF Block 1 SRAM 0x0016 4000–0x0017 3FFF Reserved 0x0005 D000–0x0005 FFFF Reserved 0x000B 1555–0x000B FFFF Reserved 0x000B A000–0x000B FFFF Reserved 0x0017 4000–0x0017 FFFF Block 2 SRAM 0x0006 0000–0x0006 1FFF Block 2 SRAM 0x000C 0000–0x000C 2AA9 Block 2 SRAM 0x000C 0000–0x000C 3FFF Block 2 SRAM 0x0018 0000–0x0018 7FFF Reserved 0x0006 2000– 0x0006 FFFF Reserved 0x000C 2AAA–0x000D FFFF Reserved 0x000C 4000–0x000D FFFF Reserved 0x0018 8000–0x001B FFFF Block 3 SRAM 0x0007 0000–0x0007 1FFF Block 3 SRAM 0x000E 0000–0x000E 2AA9 Block 3 SRAM 0x000E 0000–0x000E 3FFF Block 3 SRAM 0x001C 0000–0x001C 7FFF Reserved 0x0007 2000–0x0007 FFFF Reserved 0x000E 2AAA–0x000F FFFF Reserved 0x000E 4000–0x000F FFFF Reserved 0x001C 8000–0x001F FFFF 1 Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales representative for additional details.

Page 8

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. F | Page 7 of 70 | June 2018 instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory. ROM Based Security The ADSP-2148x has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processor does not boot-load any external code, exe- cuting exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port will be assigned to each customer. The device will ignore a wrong key. Emulation features are available after the correct key is scanned. On-Chip Memory Bandwidth The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bits, CCLK speed) and the IOD0/1 buses (2 × 32-bit, PCLK speed). FAMILY PERIPHERAL ARCHITECTURE The ADSP-2148x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equip- ment, 3D graphics, speech recognition, motor control, imaging, and other applications. External Memory The external port interface supports access to the external mem- ory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be pro- grammed as either asynchronous or synchronous memory. The external ports are comprised of the following modules. • An Asynchronous Memory Interface which communicates with SRAM, FLASH, and other devices that meet the stan- dard asynchronous SRAM access protocol. The AMI supports 6M words of external memory in bank 0 and 8M words of external memory in bank 1, bank 2, and bank 3. • A SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. NOTE: This feature is not available on the ADSP-21486 product. Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)1 IOP Registers 0x0000 0000–0x0003 FFFF Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9 Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF Reserved 0x0004 8000–0x0004 8FFF Reserved 0x0008 AAAA–0x0008 BFFF Reserved 0x0009 0000–0x0009 1FFF Reserved 0x0012 0000–0x0012 3FFF Block 0 SRAM 0x0004 9000–0x0004 EFFF Block 0 SRAM 0x0008 C000–0x0009 3FFF Block 0 SRAM 0x0009 2000–0x0009 DFFF Block 0 SRAM 0x0012 4000–0x0013 BFFF Reserved 0x0004 F000–0x0004 FFFF Reserved 0x0009 4000–0x0009 FFFF Reserved 0x0009 E000–0x0009 FFFF Reserved 0x0013 C000–0x0013 FFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 Block 1 ROM (Reserved) 0x000A 0000–0x000A FFFF Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0005 8000–0x0005 8FFF Reserved 0x000A AAAA–0x000A BFFF Reserved 0x000B 0000–0x000B 1FFF Reserved 0x0016 0000–0x0016 3FFF Block 1 SRAM 0x0005 9000–0x0005 EFFF Block 1 SRAM 0x000A C000–0x000B 3FFF Block 1 SRAM 0x000B 2000–0x000B DFFF Block 1 SRAM 0x0016 4000–0x0017 BFFF Reserved 0x0005 F000–0x0005 FFFF Reserved 0x000B 4000–0x000B FFFF Reserved 0x000B E000–0x000B FFFF Reserved 0x0017 C000–0x0017 FFFF Block 2 SRAM 0x0006 0000–0x0006 3FFF Block 2 SRAM 0x000C 0000–0x000C 5554 Block 2 SRAM 0x000C 0000–0x000C 7FFF Block 2 SRAM 0x0018 0000–0x0018 FFFF Reserved 0x0006 4000– 0x0006 FFFF Reserved 0x000C 5555–0x000D FFFF Reserved 0x000C 8000–0x000D FFFF Reserved 0x0019 0000–0x001B FFFF Block 3 SRAM 0x0007 0000–0x0007 3FFF Block 3 SRAM 0x000E 0000–0x000E 5554 Block 3 SRAM 0x000E 0000–0x000E 7FFF Block 3 SRAM 0x001C 0000–0x001C FFFF Reserved 0x0007 4000–0x0007 FFFF Reserved 0x000E 5555–0x0000F FFFF Reserved 0x000E 8000–0x000F FFFF Reserved 0x001D 0000–0x001F FFFF 1 Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Please contact your Analog Devices sales representative for additional details.

Page 9

Rev. F | Page 8 of 70 | June 2018 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 • Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port. Non-SDRAM external memory address space is shown in Table 5. External Port The external port provides a high performance, glueless inter- face to a wide variety of industry-standard memory devices. The external port, available on the 176-lead LQFP, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-stan- dard synchronous DRAM devices while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired com- bination of synchronous and asynchronous device types. Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3 occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. SDRAM Controller The SDRAM controller provides an interface of up to four sepa- rate banks of industry-standard SDRAM devices at speeds up to fSDCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 4M bytes and 256M bytes of memory. SDRAM external memory address space is shown in Table 6. NOTE: this feature is not available on the ADSP-21486 model. A set of programmable timing parameters is available to config- ure the SDRAM banks to support slower memory devices. Note that 32-bit wide devices are not supported on the SDRAM and AMI interfaces. The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory sys- tems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. SIMD Access to External Memory The SDRAM controller on the processor supports SIMD access on the 64-bit EPD (external port data bus) which allows access to the complementary registers on the PEy unit in the normal word space (NW). This removes the need to explicitly access the complimentary registers when the data is in external SDRAM memory. VISA and ISA Access to External Memory The SDRAM controller on the ADSP-2148x processors sup- ports VISA code operation which reduces the memory load since the VISA instructions are compressed. Moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. Code execution from the tra- ditional ISA operation is also supported. Note that code execution is only supported from bank 0 regardless of VISA/ISA. Table 7 shows the address ranges for instruction fetch in each mode. Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave- forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs generating 16 PWM outputs in total. Each PWM group pro- duces two pairs of PWM signals on the four PWM outputs. Table 5. External Memory for Non-SDRAM Addresses Bank Size in Words Address Range Bank 0 6M 0x0020 0000–0x007F FFFF Bank 1 8M 0x0400 0000–0x047F FFFF Bank 2 8M 0x0800 0000–0x087F FFFF Bank 3 8M 0x0C00 0000–0x0C7F FFFF Table 6. External Memory for SDRAM Addresses Bank Size in Words Address Range Bank 0 62M 0x0020 0000–0x03FF FFFF Bank 1 64M 0x0400 0000–0x07FF FFFF Bank 2 64M 0x0800 0000–0x0BFF FFFF Bank 3 64M 0x0C00 0000–0x0FFF FFFF Table 7. External Bank 0 Instruction Fetch Access Type Size in Words Address Range ISA (NW) 4M 0x0020 0000–0x005F FFFF VISA (SW) 10M 0x0060 0000–0x00FF FFFF

Page 10

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Rev. F | Page 9 of 70 | June 2018 The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single-update mode or double-update mode. In single-update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetri- cal about the midpoint of the PWM period. In double-update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. PWM signals can be mapped to the external port address lines or to the DPI pins. MediaLB The automotive models of the ADSP-2148x processors have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin as well as 5-pin media local bus protocols. It supports speeds up to 1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. For a list of automotive models, see Automotive Products on Page 68. Digital Applications Interface (DAI) The digital applications interface (DAI) allows the connection of various peripherals to any of the DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be intercon- nected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. The DAI includes eight serial ports, four precision clock genera- tors (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisi- tion port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports (SPORTs) The ADSP-2148x features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame. Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA chan- nels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT pro- vides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes: • Standard serial mode • Multichannel (TDM) mode • I2S mode • Packed I2S mode • Left-justified mode S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF receiver/transmitter has no separate DMA chan- nels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, or the precision clock generators (PCGs), and are controlled by the SRU control registers. Asynchronous Sample Rate Converter (SRC) The asynchronous sample rate converter contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Input Data Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I2S, left-justified sample pair, or right-justified mode. The IDP also provides a parallel data acquisition port (PDAP), which can be used for receiving parallel data. The PDAP port has a clock input and a hold input. The data for the PDAP can be received from DAI pins or from the external port pins. The PDAP supports a maximum of 20-bit data and four different packing modes to receive the incoming data. Precision Clock Generators The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair.

ADSP-21489KSWZ-4A Reviews

Average User Rating
5 / 5 (138)
★ ★ ★ ★ ★
5 ★
124
4 ★
14
3 ★
0
2 ★
0
1 ★
0

Write a Review

Not Rated
Thanks for Your Review!

Kas*****ohra

May 25, 2020

Quality made product satisfied with my purchase. Thanks.

Alici*****wartz

May 25, 2020

The order has arrived ahead of time, we appreciate it very much!! Thanks

Emers*****whney

May 24, 2020

Very easy to co-operate with; they take care of orders promptly.

Nathan*****rdenas

May 24, 2020

To be honest, I think you are doing an outstanding job.

Ray*****Mody

May 22, 2020

I've had no issues. Good product, would buy again.

Den***** Apte

May 20, 2020

Quality electronic components plus fast response.Thank you.

Blak*****Wang

May 17, 2020

Used this on starter solenoid and works as expected.

Crys*****Manda

May 4, 2020

Order arrived to Estonia in 3 days. Item as described. Well packed.

Priscil*****chandran

April 25, 2020

Received Quickly. Excellent Communication. Capacitors Look Excellent.

Kamila*****abarti

April 10, 2020

I was able to make my list of needed parts and use suggested relative selection. The five stars represent the fact they show inventory quantity. So far i'm happy.

ADSP-21489KSWZ-4A Guarantees

Service Guarantee

Service Guarantees

We guarantee 100% customer satisfaction.

Our experienced sales team and tech support team back our services to satisfy all our customers.

Quality Guarantee

Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

ADSP-21489KSWZ-4A Packaging

Verify Products
Customized Labels
Professional Packaging
Sealing
Packing
Insepction

ADSP-21489KSWZ-4A Related Products

SIT8208AI-GF-18S-4.096000T SIT8208AI-GF-18S-4.096000T SiTIME, -40 TO 85C, 2520, 10PPM, 1.8V, 4, -, SHARC? View
T95S685M004LSSL T95S685M004LSSL Vishay Sprague, CAP TANT 6.8UF 4V 20% 1507, 1507 (3718 Metric), SHARC? View
MAL210159332E3 MAL210159332E3 Vishay BC Components, CAP ALUM 3300UF 20% 100V SCREW, Radial, Can - Screw Terminals, SHARC? View
1711323 1711323 Phoenix Contact, TERM BLOCK PLUG 8POS STR 10.16MM, -, SHARC? View
609177002027100 609177002027100 AVX Corporation, CONN CAP WHT 9177 SERIES CONTACT, -, SHARC? View
20021311-00014T8LF 20021311-00014T8LF Amphenol FCI, CONN RCPT 14POS T/H GOLD, -, SHARC? View
09185267901 09185267901 HARTING, CONN HEADER 26POS T/H R/A, -, SHARC? View
TVP00RW-19-88SC-S15 TVP00RW-19-88SC-S15 Amphenol Aerospace Operations, CONN RCPT FMALE 88POS GOLD SLDR, -, SHARC? View
D38999/24WG39PN-LC D38999/24WG39PN-LC TE Connectivity Deutsch Connectors, CONN RCPT HSNG MALE 39POS PNL MT, -, SHARC? View
RMM18DTAH-S189 RMM18DTAH-S189 Sullins Connector Solutions, CONN EDGE DUAL FMALE 36POS 0.156, -, SHARC? View
VI-JWT-EY-B1 VI-JWT-EY-B1 Vicor Corporation, CONVERTER MOD DC/DC 6.5V 50W, Half Brick, SHARC? View
MB39C338PW-G-EFE1 MB39C338PW-G-EFE1 Cypress Semiconductor Corp, IC ANALOG 64WLCSP, -, SHARC? View
Payment Methods
Delivery Services

Quick Inquiry

ADSP-21489KSWZ-4A

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

View the Certificates

Do you have any question about ADSP-21489KSWZ-4A?

+86-755-83210559 ext. 811 SalesDept@heisener.com heisener007 2354944915 Send Message

ADSP-21489KSWZ-4A Tags

  • ADSP-21489KSWZ-4A
  • ADSP-21489KSWZ-4A PDF
  • ADSP-21489KSWZ-4A datasheet
  • ADSP-21489KSWZ-4A specification
  • ADSP-21489KSWZ-4A image
  • Analog Devices Inc.
  • Analog Devices Inc. ADSP-21489KSWZ-4A
  • buy ADSP-21489KSWZ-4A
  • ADSP-21489KSWZ-4A price
  • ADSP-21489KSWZ-4A distributor
  • ADSP-21489KSWZ-4A supplier
  • ADSP-21489KSWZ-4A wholesales

ADSP-21489KSWZ-4A is Available in