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CY7C141-25JC

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CY7C141-25JC

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Part Number CY7C141-25JC
Manufacturer Cypress Semiconductor Corp
Description IC SRAM 8KBIT 25NS 52PLCC
Datasheet CY7C141-25JC Datasheet
Package 52-LCC (J-Lead)
In Stock 4,204 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # CY7C141-25JC (Memory) is manufactured by Cypress Semiconductor Corp and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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CY7C141-25JC Specifications

ManufacturerCypress Semiconductor Corp
CategoryIntegrated Circuits (ICs) - Memory
Datasheet CY7C141-25JCDatasheet
Package52-LCC (J-Lead)
Series-
Memory TypeVolatile
Memory FormatSRAM
TechnologySRAM - Dual Port, Asynchronous
Memory Size8Kb (1K x 8)
Memory InterfaceParallel
Clock Frequency-
Write Cycle Time - Word, Page25ns
Access Time25ns
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case52-LCC (J-Lead)
Supplier Device Package52-PLCC (19.13x19.13)

CY7C141-25JC Datasheet

Page 1

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1K x 8 Dual-Port Static Ram fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 1989 – Revised March 27, 1997 1CY7C140 Features • True Dual-Ported memory cells which allow simulta- neous reads of the same memory location • 1K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns • Low operating power: ICC = 90 mA (max.) • Fully asynchronous operation • Automatic power-down • Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141 • BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141 • INT flag for port-to-port communication • Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and 52-pin TQFP • Pin-compatible and functionally equivalent to IDT7130/IDT7140 Functional Description The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave du- al-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being ac- cessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C130 and CY7C140 are available in 48-pin DIP. The CY7C131 and CY7C141 are available in 52-pin PLCC and PQFP. s Notes: 1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor CY7C140/CY7C141 (Slave): BUSY is input. 2. Open drain outputs: pull-up resistor required Logic Block Diagram Pin Configurations C130-1 C130-2 13 14 15 16 17 18 19 20 21 22 23 26 27 28 32 31 30 29 33 36 35 34 24 25GND 1 2 3 4 5 6 7 8 9 10 11 38 39 40 44 43 42 41 45 48 47 46 12 37 R/W L CEL BUSY L INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L CER R/WR BUSYR INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R VCC DIP Top View 7C130 7C140 R/WL BUSYL CEL OEL A 9L A 0L A 0R A 9R R/WR CER OER CER OER CEL OEL R/WL R/WR I/O7L I/O0L I/O7R I/O0R BUSYR INTL INTR ARBITRATION LOGIC (7C130/7C131 ONLY) AND INTERRUPT LOGIC CONTROL I/O CONTROL I/O MEMORY ARRAY ADDRESS DECODER ADDRESS DECODER [1] [2] [2]

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CY7C130/CY7C131 CY7C140/CY7C141 2 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 48 to Pin 24) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –3.5V to +7.0V Output Current into Outputs (LOW) .............................20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Notes: 3. 15 and 25-ns version available only in PLCC/PQFP packages. 4. Shaded area contains preliminary information. 5. TA is the “instant on” case temperature Pin Configuration (continued) 1 Top View PLCC OER A0R 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L C130-3 7C131 7C141 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 52 5150 49 48 47 45 44 43 42 41 40 Top View PQFP OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L C130-4 7C131 7C141 Selection Guide 7C131-15[3,4] 7C141-15 7C131-25[3] 7C141-25 7C130-30 7C131-30 7C140-30 7C141-30 7C130-35 7C131-35 7C140-35 7C141-35 7C130-45 7C131-45 7C140-45 7C141-45 7C130-55 7C131-55 7C140-55 7C141-55 Maximum Access Time (ns) 15 25 30 35 45 55 Maximum Operating Current (mA) Com’l/Ind 190 170 170 120 90 90 Military 170 120 120 Maximum Standby Current (mA) Com’l/Ind 75 65 65 45 35 35 Military 65 45 45 Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Industrial –40°C to +85°C 5V ± 10% Military[5] –55°C to +125°C 5V ± 10%

Page 4

CY7C130/CY7C131 CY7C140/CY7C141 3 ] Electrical Characteristics Over the Operating Range[6] 7C131-15[3,4] 7C141-15 7C130-30[3] 7C131-25,30 7C140-30 7C141-25,30 7C130-35 7C131-35 7C140-35 7C141-35 7C130-45,55 7C131-45,55 7C140-45,55 7C141-45,55 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 2.4 V VOL Output LOW Voltage IOL = 4.0 mA 0.4 0.4 0.4 0.4 V IOL = 16.0 mA [7] 0.5 0.5 0.5 0.5 VIH Input HIGH Voltage 2.2 2.2 2.2 2.2 V VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V IIX Input Leakage Current GND < VI < VCC –5 +5 –5 +5 –5 +5 –5 +5 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –5 +5 –5 +5 –5 +5 –5 +5 µA IOS Output Short Circuit Current[8, 9] VCC = Max., VOUT = GND –350 –350 –350 –350 mA ICC VCC Operating Supply Current CE = VIL, Outputs Open, f = fMAX [10] Com’l 190 170 120 90 mA Mil 170 120 ISB1 Standby Current Both Ports, TTL Inputs CEL and CER > VIH, f = fMAX [10] Com’l 75 65 45 35 mA Mil 65 45 ISB2 Standby Current One Port, TTL Inputs CEL or CER > VIH, Active Port Out- puts Open, f = fMAX [10] Com’l 135 115 90 75 mA Mil 115 90 ISB3 Standby Current Both Ports, CMOS Inputs Both Ports CEL and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0 Com’l 15 15 15 15 mA Mil 15 15 ISB4 Standby Current One Port, CMOS Inputs One Port CEL or CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX [10] Com’l 125 105 85 70 mA Mil 105 85 Notes: 6. See the last page of this specification for Group A subgroup testing information. 7. BUSY and INT pins only. 8. Duration of the short circuit should not exceed 30 seconds. 9. This parameter is guaranteed but not tested. 10. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V. Capacitance[9] Parameter Description Test Conditions Max. Unit CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 15 pF COUT Output Capacitance 10 pF

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CY7C130/CY7C131 CY7C140/CY7C141 4 AC Test Loads and Waveforms Switching Characteristics Over the Operating Range[6,11] 7C131-15[3,4] 7C141-15 7C130-25[3] 7C131-25 7C140-25 7C141-25 7C130-30 7C131-30 7C140-30 7C141-30 Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 25 30 ns tAA Address to Data Valid [12] 15 25 30 ns tOHA Data Hold from Address Change 0 0 0 ns tACE CE LOW to Data Valid [12] 15 25 30 ns tDOE OE LOW to Data Valid [12] 10 15 20 ns tLZOE OE LOW to Low Z [9,13, 14] 3 3 3 ns tHZOE OE HIGH to High Z [9,13, 14] 10 15 15 ns tLZCE CE LOW to Low Z [9,13, 14] 3 5 5 ns tHZCE CE HIGH to High Z [9,13, 14] 10 15 15 ns tPU CE LOW to Power-Up [9] 0 0 0 ns tPD CE HIGH to Power-Down [9] 15 25 25 ns WRITE CYCLE[15] tWC Write Cycle Time 15 25 30 ns tSCE CE LOW to Write End 12 20 25 ns tAW Address Set-Up to Write End 12 20 25 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE R/W Pulse Width 12 15 25 ns tSD Data Set-Up to Write End 10 15 15 ns tHD Data Hold from Write End 0 0 0 ns tHZWE R/W LOW to High Z [14] 10 15 15 ns tLZWE R/W HIGH to Low Z [14] 0 0 0 ns Notes: 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30-pF load capacitance. 12. AC Test Conditions use VOH = 1.6V and VOL = 1.4V. 13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write 3.0V 5V OUTPUT R1 893Ω R2 347Ω 30 pF INCLUDING JIGAND SCOPE GND 90% 90% 10% ≤ 5 ns ≤5ns 5V OUTPUT R1 893Ω R2 347Ω 5 pF INCLUDING JIGAND SCOPE(a) (b) OUTPUT 1.40V Equivalent to: THÉVENIN EQUIVALENT 5V 281Ω 30 pF BUSY OR INT BUSY Output Load (CY7C130/CY7C131 ONLY) 10% C130-5 C130-6 ALL INPUT PULSES 250Ω

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CY7C130/CY7C131 CY7C140/CY7C141 5 BUSY/INTERRUPT TIMING tBLA BUSY LOW from Address Match 15 20 20 ns tBHA BUSY HIGH from Address Mismatch [16] 15 20 20 ns tBLC BUSY LOW from CE LOW 15 20 20 ns tBHC BUSY HIGH from CE HIGH [16] 15 20 20 ns tPS Port Set Up for Priority 5 5 5 ns tWB [17] R/W LOW after BUSY LOW 0 0 0 ns tWH R/W HIGH after BUSY HIGH 13 20 30 ns tBDD BUSY HIGH to Valid Data 15 25 30 ns tDDD Write Data Valid to Read Data Valid Note 18 Note 18 Note 18 ns tWDD Write Pulse to Data Delay Note 18 Note 18 Note 18 ns INTERRUPT TIMING tWINS R/W to INTERRUPT Set Time 15 25 25 ns tEINS CE to INTERRUPT Set Time 15 25 25 ns tINS Address to INTERRUPT Set Time 15 25 25 ns tOINR OE to INTERRUPT Reset Time [16] 15 25 25 ns tEINR CE to INTERRUPT Reset Time [16] 15 25 25 ns tINR Address to INTERRUPT Reset Time [16] 15 25 25 ns Notes: 16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 17. CY7C140/CY7C141 only. 18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address is toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. Switching Characteristics Over the Operating Range[6,11] 7C130-35 7C131-35 7C140-35 7C141-35 7C130-45 7C131-45 7C140-45 7C141-45 7C130-55 7C131-55 7C140-55 7C141-55 Parameter Description Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 45 55 ns tAA Address to Data Valid [12] 35 45 55 ns tOHA Data Hold from Address Change 0 0 0 ns tACE CE LOW to Data Valid [12] 35 45 55 ns tDOE OE LOW to Data Valid [12] 20 25 25 ns tLZOE OE LOW to Low Z [9,13, 14] 3 3 3 ns tHZOE OE HIGH to High Z [9,13, 14] 20 20 25 ns tLZCE CE LOW to Low Z [9,13, 14] 5 5 5 ns tHZCE CE HIGH to High Z [9,13, 14] 20 20 25 ns tPU CE LOW to Power-Up [9] 0 0 0 ns tPD CE HIGH to Power-Down [9] 35 35 35 ns Switching Characteristics Over the Operating Range[6,11] (continued) 7C131-15[3,4] 7C141-15 7C130-25[3] 7C131-25 7C140-25 7C141-25 7C130-30 7C131-30 7C140-30 7C141-30 Parameter Description Min. Max. Min. Max. Min. Max. Unit

Page 7

CY7C130/CY7C131 CY7C140/CY7C141 6 WRITE CYCLE[15] tWC Write Cycle Time 35 45 55 ns tSCE CE LOW to Write End 30 35 40 ns tAW Address Set-Up to Write End 30 35 40 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE R/W Pulse Width 25 30 30 ns tSD Data Set-Up to Write End 15 20 20 ns tHD Data Hold from Write End 0 0 0 ns tHZWE R/W LOW to High Z [14] 20 20 25 ns tLZWE R/W HIGH to Low Z [14] 0 0 0 ns BUSY/INTERRUPT TIMING tBLA BUSY LOW from Address Match 20 25 30 ns tBHA BUSY HIGH from Address Mismatch [16] 20 25 30 ns tBLC BUSY LOW from CE LOW 20 25 30 ns tBHC BUSY HIGH from CE HIGH [16] 20 25 30 ns tPS Port Set Up for Priority 5 5 5 ns tWB [17] R/W LOW after BUSY LOW 0 0 0 ns tWH R/W HIGH after BUSY HIGH 30 35 35 ns tBDD BUSY HIGH to Valid Data 35 45 45 ns tDDD Write Data Valid to Read Data Valid Note 18 Note 18 Note 18 ns tWDD Write Pulse to Data Delay Note 18 Note 18 Note 18 ns INTERRUPT TIMING tWINS R/W to INTERRUPT Set Time 25 35 45 ns tEINS CE to INTERRUPT Set Time 25 35 45 ns tINS Address to INTERRUPT Set Time 25 35 45 ns tOINR OE to INTERRUPT Reset Time [16] 25 35 45 ns tEINR CE to INTERRUPT Reset Time [16] 25 35 45 ns tINR Address to INTERRUPT Reset Time [16] 25 35 45 ns Switching Characteristics Over the Operating Range[6,11] (continued) 7C130-35 7C131-35 7C140-35 7C141-35 7C130-45 7C131-45 7C140-45 7C141-45 7C130-55 7C131-55 7C140-55 7C141-55 Parameter Description Min. Max. Min. Max. Min. Max. Unit Switching Waveforms Notes: 19. R/W is HIGH for read cycle. 20. Device is continuously selected, CE = VIL and OE = VIL. Read Cycle No.1 tRC tAA tOHA DATA VALIDPREVIOUS DATA VALIDDATA OUT ADDRESS C130-7 Either Port Address Access [19, 20]

Page 8

CY7C130/CY7C131 CY7C140/CY7C141 7 Notes: 21. Address valid prior to or coincident with CE transition LOW. 22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. Switching Waveforms (continued) tACE tLZOE tDOE tHZOE tHZCE DATA VALIDDATA OUT CE OE tLZCE tPU ICC ISB tPD Read Cycle No. 2 tBHA tBDD VALID tDDD tWDD ADDRESS MATCH ADDRESS MATCH R/WR ADDRESSR DINR ADDRESSL BUSYL DOUTL Read Cycle No.3 Write Cycle No.1 (OE Three-States Data I/Os - Either Port) tAW tWC DATA VALID HIGH IMPEDANCE tSCE tSA tPWE tHDtSD tHA CE R/W ADDRESS tHZOE OE DOUT DATAIN Either Port CE/OE Access Either Port C130-8 C130-9 C130-10 tPS tBLA Read with BUSY, Master: CY7C130 and CY7C131 tRC tPWE VALID tHD [19, 21] [20] [15, 22]

Page 9

CY7C130/CY7C131 CY7C140/CY7C141 8 Note: 23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state Switching Waveforms (continued) Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port) tAW tWC tSCE tSA tPWE tHDtSD tHZWE Either Port tHA HIGH IMPEDANCE ADDRESS MATCH tPS Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: tBLC tBHC ADDRESS MATCH tPS tBLC tBHC CER Valid First: DATA VALID tLZWE C130-11 C130-12 C130-13 ADDRESS CE R/W DATAOUT DATAIN ADDRESSL,R BUSYR CEL CER BUSYL CER CEL ADDRESSL,R [16, 23]

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CY7C130/CY7C131 CY7C140/CY7C141 9 Switching Waveforms (continued) Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: ADDRESS MATCH tPS ADDRESSL BUSYR ADDRESS MISMATCH tRC or tWC tBLA tBHA ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL BUSYL tRC or tWC tBLA tBHA ADDRESSR Right Address Valid First: tPWE tWB tWH Busy Timing Diagram No. 3 Write with BUSY (Slave:CY7C140/CY7C141) C130-14 C130-15 C130-16 BUSY R/W CE

CY7C141-25JC Reviews

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Ande*****hankar

July 4, 2020

Work Great. Would recommend. Only used 2. So I have 248 extras. Best deal by far that's why I got these.

Aida*****lson

July 4, 2020

Very user friendly to find part and specs. Easy to deal with the transaction for different payment types. Thanks!

Ede*****utton

July 2, 2020

Received the parts, and all parts are in tight packaging without any problems, professional seller.

Char*****Chand

July 2, 2020

Diodes okay. Shipped quick and received with well - packed

Alla*****rray

July 1, 2020

The products are good, the amount is correct. The values are correct.

Elija*****ilton

June 29, 2020

All of the components worked, and are still working. So even though the price is amazingly low, the diodes really do work!

Ally*****Palmer

June 27, 2020

Went well this time Now have the IC and very pleased.

Adrie*****aldwell

June 24, 2020

Items as described, quick dispatch, took a while with shipment.

Kevi*****ntana

June 16, 2020

They are components and they work. Wasn’t expecting anything more or anything less.

Lill*****Butler

June 2, 2020

Great kit, cost half the price of other stores. Includes most items that someone would need.

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