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DS3150QC1+

DS3150QC1+

DS3150QC1+

For Reference Only

Part Number DS3150QC1+
Manufacturer Maxim Integrated
Description IC LIU DS3/E3/STS-1 28-PLCC
Datasheet DS3150QC1+ Datasheet
Package 28-LCC (J-Lead)
In Stock 333 piece(s)
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DS3150QC1+

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DS3150QC1+ Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Interface - Telecom
Datasheet DS3150QC1+ Datasheet
Package28-LCC (J-Lead)
Series-
FunctionLine Interface Unit (LIU)
InterfaceLIU
Number of Circuits1
Voltage - Supply3.135 V ~ 3.465 V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case28-LCC (J-Lead)
Supplier Device Package28-PLCC (11.51x11.51)

DS3150QC1+ Datasheet

Page 1

Page 2

1 of 28 REV: 071305 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The receiver performs clock and data recovery, B3ZS/HDB3 decoding, and loss-of-signal monitoring. The transmitter encodes outgoing data and drives standards-compliant waveforms onto 75Ω coaxial cable. The jitter attenuator can be mapped into the receive path or the transmit path. APPLICATIONS SONET/SDH and PDH Multiplexers Digital Cross-Connects Access Concentrators ATM and Frame Relay Equipment Routers PBXs DSLAMs CSUs/DSUs ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS3150QN -40C to +85C 28 PLCC DS3150Q 0C to +70C 28 PLCC DS3150TN -40C to +85C 48 TQFP DS3150T 0C to +70C 48 TQFP FUNCTIONAL DIAGRAM FEATURES Integrated Transmitter, Receiver, and Jitter Attenuator for DS3, E3, and STS-1 Performs Receive Clock/Data Recovery and Transmit Waveshaping Jitter Attenuator Can Be Placed in the Receive Path or the Transmit Path AGC/Equalizer Block Handles from 0dB to 15dB of Cable Loss Interfaces to 75 Coaxial Cable at Lengths Up to 380m (DS3), 440m (E3), or 360m (STS-1) Interfaces Directly to a DSX Monitor Signal (20dB Flat Loss) Using Built-In Preamp Built-In B3ZS and HDB3 Encoder/Decoder Bipolar and NRZ Interfaces Local and Remote Loopbacks On-Board 215 - 1 and 223 - 1 Pseudorandom Bit Sequence (PRBS) Generator and Detector Line Build-Out (LBO) Control Transmit Line-Driver Monitor Checks for a Faulty Transmitter or a Shorted Output Complete DS3 AIS Generator (ANSI T1.107) Unframed All-Ones Generator (E3 AIS) Clock Inversion for Glueless Interfacing Tri-State Line Driver for Low-Power Mode and Protection Switching Applications Loss-of-Signal (LOS) Detector (ANSI T1.231 and ITU G.775) Automatic Data Squelching During LOS Requires Minimal External Components Drop-In Replacement for TDK 78P2241/B and 78P7200L (Refer to Application Note 362) Pin Compatible with TDK 78P7200 3.3V Operation (5V Tolerant I/O), 110mA (max) Industrial Temperature Range: -40C to +85C Small Packaging: 28-Pin PLCC and 48-Pin TQFP Pin Configurations appear at end of data sheet. DS3150 3.3V, DS3/E3/STS-1 Line Interface Unit www.maxim-ic.com DEMO KIT AVAILABLE Rx+ Rx- Tx+ Tx- RCLKLINE IN DS3, E3, STS-1 LINE OUT DS3, E3, STS-1 DS3150 LIU RPOS RNEG TCLK TPOS TNEG RECEIVE CLOCK AND DATA TRANSMIT CLOCK AND DATA

Page 3

DS3150 2 of 28 TABLE OF CONTENTS 1. DETAILED DESCRIPTION.................................................................................................4 1.1 RECEIVER.................................................................................................................................... 7 1.2 TRANSMITTER .............................................................................................................................10 1.3 DIAGNOSTICS..............................................................................................................................15 1.4 JITTER ATTENUATOR ...................................................................................................................16 2. PIN DESCRIPTIONS ........................................................................................................17 3. ELECTRICAL CHARACTERISTICS ................................................................................21 4. PIN CONFIGURATIONS ..................................................................................................25 5. PACKAGE INFORMATION..............................................................................................26 6. REVISION HISTORY........................................................................................................28

Page 4

DS3150 3 of 28 LIST OF FIGURES Figure 1-1. Block Diagram ...........................................................................................................4 Figure 1-2. External Connections.................................................................................................6 Figure 1-3. Receiver Jitter Tolerance...........................................................................................9 Figure 1-4. E3 Waveform Template ...........................................................................................13 Figure 1-5. DS3 AIS Structure ...................................................................................................14 Figure 1-6. PRBS Output with Normal RCLK Operation ............................................................15 Figure 1-7. PRBS Output with Inverted RCLK Operation...........................................................15 Figure 1-8. Jitter Attenuation and Jitter Transfer........................................................................16 Figure 3-1. Framer Interface Timing Diagram............................................................................22 LIST OF TABLES Table 1-A. Applicable Telecommunications Standards................................................................5 Table 1-B. Transformer Recommendations .................................................................................6 Table 1-C. DS3 Waveform Template .........................................................................................11 Table 1-D. DS3 Waveform Test Parameters and Limits ............................................................11 Table 1-E. STS-1 Waveform Template ......................................................................................12 Table 1-F. STS-1 Waveform Test Parameters and Limits .........................................................12 Table 1-G. E3 Waveform Test Parameters and Limits...............................................................13 Table 2-A. Pin Descriptions........................................................................................................17 Table 2-B. Transmit Data Selection ...........................................................................................20 Table 2-C. RMON and TTS Signal Decode................................................................................20

Page 5

DS3150 4 of 28 1. DETAILED DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The device has independent receive and transmit paths and a built-in jitter attenuator (Figure 1-1). The receiver performs clock and data recovery from a B3ZS- or HDB3-coded alternate mark inversion (AMI) signal and monitors for loss-of-signal. The receiver optionally performs B3ZS/HDB3 decoding and outputs the recovered data in either NRZ or bipolar format. The transmitter accepts data in either NRZ or bipolar format, optionally performs B3ZS/HDB3 encoding, and drives standards-compliant waveforms onto the outgoing 75Ω coaxial cable. The jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path, or disabled. The DS3150 conforms to the telecommunication standards listed in Table 1-A. Figure 1-2 shows the external components required for proper operation. Figure 1-1. Block Diagram Analog Loopback Pre Amp Filter/ Equalizer (Analog Loss Of Signal Detect) Clock & Data Recovery Line Driver Wave- Shaping Clock Invert Clock Invert RX+ RX- TX+ TX- TTS PRBS LBO ZCSE ICE TPOS/TNRZ TCLK TNEG TESS RNEG/RLCV RCLK RPOS/RNRZ LOSMCLK RMON Remote Loopback EFEVDD VSS Power Connections Test Functions TDS0 TDS1 B3ZS/ HDB3 Encoder AIS/ 1010.../ PRBS Generation M u x M u x m u x PRBS Detector B3ZS/HDB3 Decoder Digital Loss Of Signal Detector Squelch Ji tt e r A tt e n u a to r (c a n b e p la ce d in e ith e r th e r e ce iv e p a th o r th e t ra n sm it p a th ) Driver Monitor Output Decode Loopback Control DM LBKS DS3150

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DS3150 5 of 28 Table 1-A. Applicable Telecommunications Standards SPECIFICATION SPECIFICATION TITLE ANSI T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.107-1995 Digital Hierarchy—Formats Specification T1.231-1997 Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring T1.404-1994 Network-to-Customer Installation—DS3 Metallic Interface Specification ITU-T G.703 Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991 G.751 Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, 1993 G.775 Loss-of-Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria, November 1994 G.823 The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy, 1993 G.824 The Control of Jitter and Wander Within Digital Networks Which are Based on the 1544kbps Hierarchy, 1993 O.151 Error Performance Measuring Equipment Operating at the Primary Rate and Above, October 1992 ETSI ETS 300 686 Business TeleCommunications; 34Mbps and 140Mbps digital leased lines (D34U, D34S, D140U, and D140S); Network interface presentation, 1996 ETS 300 687 Business TeleCommunications; 34Mbps digital leased lines (D34U and D34S); Connection characteristics, 1996 ETS EN 300 689 Access and Terminals (AT); 34Mbps digital leased lines (D34U and D34S); Terminal equipment interface, July 2001 TBR 24 Business TeleCommunications; 34Mbps digital unstructured and structured lease lines; attachment requirements for terminal equipment interface, 1997 Telcordia GR-253-CORE SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995 GR-499-CORE Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2, December 1998

Page 7

DS3150 6 of 28 Figure 1-2. External Connections Table 1-B. Transformer Recommendations MANUFACTURER PART NO. TEMP RANGE PIN- PACKAGE/ SCHEMATIC OCL PRIMARY H MIN LL H MAX BANDWIDTH 75, MHz Pulse Engineering PE-65968 0°C to +70°C 6-SMT LS-1/C 19 0.06 0.250 to 500 Pulse Engineering PE-65969 0°C to +70°C 6-thru-hole LC-1/C 19 0.06 0.250 to 500 Halo Electronics TG07- 0206NS 0°C to +70°C 6-SMT SMD/B 19 0.06 0.250 to 500 Halo Electronics TD07- 0206NE 0°C to +70°C 6-DIP DIP/B 19 0.06 0.250 to 500 Note: Table subject to change. Industrial temperature range and dual transformers also available. Contact the manufacturers for details. 1:2ct 1:2ct 0.05µF TRANSMIT RECEIVE TX+ TX- RX+ RX- 0.01µF 3.3V POWER PLANE GROUND PLANE VDD VDD VDD VSS VSS VSS DS3150 0.1µF 1µF 330 (1%) 0.05µF 330 (1%) 0.01µF 0.1µF 1µF 0.01µF 0.1µF 1µF VDD

Page 8

DS3150 7 of 28 1.1 Receiver Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the incoming coaxial cable (75) through a 1:2 step-up transformer. Figure 1-2 shows the arrangement of the transformer and other recommended interface components. The device expects the incoming signal to be in B3ZS- or HDB3-coded AMI format. Optional Preamp. The receiver can be used in monitoring applications, which typically have series resistors that result in a resistive loss of approximately 20dB. When the RMON input pin is high, the receiver compensates for this resistive loss by applying flat gain to the incoming signal before sending the signal to the equalizer block. Adaptive Equalizer. The adaptive equalizer applies both frequency-dependent gain and flat gain to offset signal losses from the coaxial cable and provides a signal of nominal amplitude and pulse shape to the clock and data recovery block. The equalizer circuitry automatically adapts to coaxial cable losses from 0 to 15dB, which translates into 0 to 380 meters (DS3), 0 to 440 meters (E3), or 0 to 360 meters (STS-1) of coaxial cable (AT&T 734A or equivalent). The equalizer can perform direct (0 meter) monitoring of the transmitter output signal. Clock and Data Recovery. The clock and data recovery (CDR) block takes the amplified, equalized signal from the equalizer and produces separate clock, positive data and negative data signals. The CDR requires a master clock (44.736MHz for DS3, 34.368MHz for E3, 51.840MHz for STS-1). If the signal on MCLK is toggling, the device selects the MCLK signal as the master clock. If MCLK is wired high or left floating, the device uses the signal on the TCLK pin as the master clock. If MCLK is wired low, the device takes its master clock from an internal oscillator. The selected master clock is also used by the jitter attenuator. Loss-of-Signal Detector. The receiver contains both analog and digital LOS detectors. The analog LOS detector resides in the equalizer block. If the incoming signal level is less than a signal level approximately 24dB below nominal, analog loss-of-signal (ALOS) is declared. The ALOS signal cannot be directly examined, but when ALOS occurs the equalizer squelches the recovered data, forcing all zeros out of the clock and data recovery circuitry and subsequently causing digital loss-of-signal (DLOS), which is indicated on the LOS pin. ALOS clears when the incoming signal level is greater than or equal to a signal level approximately 18dB below nominal. The digital loss-of-signal detector declares DLOS when it detects 175 75 consecutive zeros in the recovered data stream. When DLOS occurs, the receiver asserts the LOS pin. DLOS is cleared when there are no excessive zero occurrences over a span of 175 75 clock periods. An excessive zero occurrence is defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive zeros in the E3 mode. The LOS pin is deasserted when the DLOS condition is cleared. The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which asserts LOS when it counts 175 75 consecutive zeros coming out of the clock and data recovery block and clears LOS when it counts 175 75 consecutive pulse intervals without excessive zero occurrences. The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the DLOS detector as follows:

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DS3150 8 of 28 For E3 LOS Assertion: 1) The ALOS circuitry detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal and mutes the data coming out of the clock and data recovery block. (24dB below nominal is in the “tolerance range” of G.775, where LOS may or may not be declared.) 2) The DLOS detector counts 175 75 consecutive zeros coming out of the clock and data recovery block and asserts LOS. (175 75 meets the 10  N  255 pulse interval duration requirement of G.775.) For E3 LOS Clear: 1) The ALOS circuitry detects that the incoming signal is greater than or equal to a signal level approximately 18dB below nominal and enables data to come out of the clock and data recovery block. (18dB below nominal is in the “tolerance range” of G.775 where LOS may or may not be declared.) 2) The DLOS detector counts 175 75 consecutive pulse intervals without excessive zero occurrences and deasserts LOS. (175 75 meets the 10  N  255 pulse interval duration requirement of G.775.) The requirements of ANSI T1.231 for STS-1 LOS defects are supported by the DLOS detector. At STS-1 rate, the time required for the DLOS detector to count 175 75 consecutive zeros falls in the range of 2.3T100s required by ANSI T1.231 for declaring an LOS defect. Although the time required for the DLOS detector to count 175 75 consecutive pulse intervals with no excessive zeros is less than the 125µs to 250s period required by ANSI T1.231 for clearing an LOS defect, a period of this length where LOS is inactive can easily be timed in software. During LOS, the RCLK output signal is derived from the device’s master clock. The ALOS detector has a longer time constant than the DLOS detector. Thus, when the incoming signal is lost, the DLOS detector activates first, asserting the LOS pin, followed by the ALOS detector. When a signal is restored, the DLOS detector does not get a valid signal that it can qualify for no excessive zero occurrences until the ALOS detector has seen the incoming signal rise above a signal level approximately 18dB below nominal. Framer Interface Format and the B3ZS/HDB3 Decoder. The recovered data can be output in either NRZ or bipolar format. To select the bipolar format, wire the ZCSE input pin high. In this format, the B3ZS/HDB3 decoder is disabled, and the recovered data is buffered and output on the RPOS and RNEG output pins. Received positive-polarity pulses are indicated by RPOS = 1, while negative-polarity pulses are indicated by RNEG = 1. In bipolar interface format the receiver simply passes on the data received and does not check it for bipolar violations or excessive zero occurrences. To select the NRZ format, wire ZCSE low. In this format, the B3ZS/HDB3 decoder is enabled, and the recovered data is decoded and output as a composite NRZ value on the RNRZ pin. Code violations are flagged on the RLCV pin. In the discussion that follows, a valid pulse that conforms to the AMI rule is denoted as B. A pulse that violates the AMI rule is known as bipolar violation (BPV) and is denoted as V. In DS3 and STS-1 modes, B3ZS decoding is performed. RLCV is asserted during any RCLK cycle where the data on RNRZ causes ones of the following code violations: A BPV immediately preceded by a valid pulse (B, V) A BPV with the same polarity as the last BPV

Page 10

DS3150 9 of 28 A third consecutive zero (0, 0, 0) In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RNRZ causes one of the following code violations: A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V) A BPV with the same polarity as the last BPV A fourth consecutive zero (0, 0, 0, 0) When RLCV is asserted to flag a BPV, the RNRZ pin outputs a 1. The state bit that tracks the polarity of the last BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not. To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be inverted using the ICE input pin. See the ICE pin description in Table 2-A for details. Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in Table 1-A. See the graphs in Figure 1-3. Receiver Jitter Transfer. The jitter transfer performance of the receiver, with and without the jitter attenuator enabled, is shown in Figure 1-8. Figure 1-3. Receiver Jitter Tolerance E3 JITTER TOLERANCE 0.01 0.1 1 10 100 0.1 1 10 100 1000 FREQUENCY (kHz) U I P -P G.823 and ETSI 300 689 JA in Rx JA disabled DS3 JITTER TOLERANCE 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 FREQUENCY (kHz) U I P -P GR-499 Cat II G.824 GR-499 Cat I JA in Rx JA disabled STS-1 JITTER TOLERANCE 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 FREQUENCY (kHz) U I P -P GR-253-CORE JA in Rx JA disabled Note 1: All jitter tolerance curves are worst case over temperature, voltage, cable length (0 to 900 feet), and RMON pin setting. Note 2: The low-frequency plateau seen in most of the jitter tolerance curves is not the actual performance of the DS3150 but rather the limit of the measuring equipment (64 UIP-P). Actual jitter tolerance in these low-frequency ranges is greater than or equal to 64 UIP-P. Note 3: Receiver jitter tolerance is not tested during production test.

DS3150QC1+ Reviews

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5 / 5 (106)
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Tessa*****herty

February 23, 2020

Can't speak to the long term reliability as of yet, but they seem to be of decent quality and I don't expect any issues.

Marle*****liver

December 17, 2019

Better than ever - more stock, better prices, quicker shipments, many choices of payment.

Mart*****aymond

December 3, 2019

Well packed, good item, capacitors both within 2.5% tolerance!

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December 1, 2019

Reasonable prices, fast shipping, and the best customer service I've ever experienced! Absolutely will share it to my friends.

Nat*****a Lam

November 28, 2019

I am always amazed at the cost of automotive or marine costs when a rectifier is needed while these will do the exact same thing if you are a bit technically minded to wire them up.

Renat*****inosa

November 25, 2019

Very user friendly to find part and specs. Easy to deal with the transaction for different payment types. Thanks!

Zayle*****legos

November 5, 2019

To be honest, you're beating your competitor on delivery - sometimes I request 2nd day and you still get it here overnight. Thanks!

Juel*****hley

October 21, 2019

I am satisfied with Heisener company

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September 18, 2019

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Skyla*****raborty

August 27, 2019

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