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IS61WV102416BLL-10TLI

hot IS61WV102416BLL-10TLI

IS61WV102416BLL-10TLI

For Reference Only

Part Number IS61WV102416BLL-10TLI
Manufacturer ISSI, Integrated Silicon Solution Inc
Description IC SRAM 16MBIT 10NS 48TSOP
Datasheet IS61WV102416BLL-10TLI Datasheet
Package 48-TFSOP (0.724", 18.40mm Width)
In Stock 46134 piece(s)
Unit Price $ 25.34 *
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Lead Time Can Ship Immediately
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IS61WV102416BLL-10TLI

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IS61WV102416BLL-10TLI Specifications

ManufacturerISSI, Integrated Silicon Solution Inc
CategoryIntegrated Circuits (ICs) - Memory
Datasheet IS61WV102416BLL-10TLI Datasheet
Package48-TFSOP (0.724", 18.40mm Width)
Series-
Memory TypeVolatile
Memory FormatSRAM
TechnologySRAM - Asynchronous
Memory Size16Mb (1M x 16)
Write Cycle Time - Word, Page10ns
Access Time10ns
Memory InterfaceParallel
Voltage - Supply2.4 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case48-TFSOP (0.724", 18.40mm Width)
Supplier Device Package48-TSOP I

IS61WV102416BLL-10TLI Datasheet

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. G 06/02/2014 Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL 1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JUNE 2014 FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE op- tions • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply Vdd 1.65V to 2.2V (IS61WV102416ALL) speed = 20ns for Vdd 1.65V to 2.2V Vdd 2.4V to 3.6V (IS61/64WV102416BLL) speed = 10ns for Vdd 2.4V to 3.6V speed = 8ns for Vdd 3.3V + 5% • Packages available: – 48-ball miniBGA (9mm x 11mm) – 48-pin TSOP (Type I) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS61WV102416ALL/BLL and IS64WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-perfor- mance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be re- duced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm). A0-A19 CE OE WE 1024K x 16 MEMORY ARRAYDECODER COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte UB LB

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2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL PIN DESCRIPTIONS A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground 48-pin mini BGA (9mmx11mm) 1 2 3 4 5 6 A B C D E F G H LB OE A0 A1 A2 NC I/O8 UB A3 A4 CE I/O0 I/O9 I/O10 A5 A6 I/O1 I/O2 GND I/O11 A17 A7 I/O3 VDD VDD I/O12 NC A16 I/O4 GND I/O14 I/O13 A14 A15 I/O5 I/O6 I/O15 A19 A12 A13 WE I/O7 A18 A8 A9 A10 A11 NC

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL PIN DESCRIPTIONS A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground 48-pin TSOP-I (12mm x 20mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A4 A3 A2 A1 A0 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 A5 A6 A7 A8 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14

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4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V Vdd Vdd Relates to GND –0.3 to 4.0 V tstg Storage Temperature –65 to +150 °C Pt Power Dissipation 1.0 W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter Conditions Max. Unit Cin Input Capacitance Vin = 0V 6 pF Ci/O Input/Output Capacitance VOut = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected X H X X X High-Z High-Z isb1, isb2 Output Disabled H L H X X High-Z High-Z iCC X L X H H High-Z High-Z Read H L L L H dOut High-Z iCC H L L H L High-Z dOut H L L L L dOut dOut Write L L X L H din High-Z iCC L L X H L High-Z din L L X L L din din

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL OPERATING RANGE (VDD) (IS61WV102416BLL)(1) Range Ambient Temperature VDD (8 nS) VDD (10 nS) Commercial 0°C to +70°C 3.3V + 5% 2.4V-3.6V Industrial –40°C to +85°C 3.3V + 5% 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (VDD) (IS64WV102416BLL) Range Ambient Temperature VDD (10 nS) Automotive –40°C to +125°C 2.4V-3.6V OPERATING RANGE (VDD) (IS61WV102416ALL) Range Ambient Temperature VDD (20 nS) Commercial 0°C to +70°C 1.65V-2.2V Industrial –40°C to +85°C 1.65V-2.2V Automotive –40°C to +125°C 1.65V-2.2V

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6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage Vdd = Min., iOH = –1.0 mA 1.8 — V VOL Output LOW Voltage Vdd = Min., iOL = 1.0 mA — 0.4 V ViH Input HIGH Voltage 2.0 Vdd + 0.3 V ViL Input LOW Voltage(1) –0.3 0.8 V iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA Note: 1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. ViH (max.) = Vdd + 0.3V dC; ViH (max.) = Vdd + 2.0V aC (pulse width 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage Vdd = Min., iOH = –4.0 mA 2.4 — V VOL Output LOW Voltage Vdd = Min., iOL = 8.0 mA — 0.4 V ViH Input HIGH Voltage 2 Vdd + 0.3 V ViL Input LOW Voltage(1) –0.3 0.8 V iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA Note: 1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. ViH (max.) = Vdd + 0.3V dC; ViH (max.) = Vdd + 2.0V aC (pulse width 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage iOH = -0.1 mA 1.65-2.2V 1.4 — V VOL Output LOW Voltage iOL = 0.1 mA 1.65-2.2V — 0.2 V ViH Input HIGH Voltage 1.65-2.2V 1.4 Vdd + 0.2 V ViL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA Notes: 1. ViL (min.) = –0.3V dC; ViL (min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested. ViH (max.) = Vdd + 0.3V dC; ViH (max.) = Vdd + 2.0V AC (pulse width -2.0ns). Not 100% tested.

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC TEST LOADS Figure 1. 319 Ω 5 pF Including jig and scope 353 Ω OUTPUT 3.3V Figure 2. ZO = 50Ω 1.5V 50Ω OUTPUT 30 pF Including jig and scope AC TEST CONDITIONS (HIGH SPEED) Parameter Unit Unit Unit (2.4V-3.6V) (3.3V + 5%) (1.65V-2.2V) Input Pulse Level 0.4V to Vdd-0.3V 0.4V to Vdd-0.3V 0.4V to Vdd-0.2V Input Rise and Fall Times 1.5ns 1.5ns 1.5ns Input and Output Timing Vdd/2 Vdd/2 + 0.05 Vdd/2 and Reference Level (VRef) Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2

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8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 -10 -20 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit iCC Vdd Dynamic Operating Vdd = Max., Com. — 110 — 90 — 50 mA Supply Current iOut = 0 mA, f = fmaX Ind. — 115 — 95 — 60 Vin = 0.4V or Vdd –0.3V Auto. — — — 140 — 100 typ.(2) 60 iCC1 Operating Vdd = Max., Com. — 85 — 85 — 45 mA Supply Current iOut = 0 mA, f = 0 Ind. — 90 — 90 — 55 Vin = 0.4V or Vdd –0.3V Auto. — — — 110 — 90 isb1 TTL Standby Current Vdd = Max., Com. — 30 — 30 — 30 mA (TTL Inputs) Vin = ViH or ViL Ind. — 35 — 35 — 35 CE ≥ ViH, f = 0 Auto. — — — 70 — 70 isb2 CMOS Standby Vdd = Max., Com. — 20 — 20 — 20 mA Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 25 — 25 — 25 Vin ≥ Vdd – 0.2V, or Auto. — — — 60 — 60 Vin ≤ 0.2V, f = 0 typ.(2) 4 Note: 1. At f = fmaX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 -10 Symbol Parameter Min. Max. Min. Max. Unit trC Read Cycle Time 8 — 10 — ns taa Address Access Time — 8 — 10 ns tOHa Output Hold Time 2.5 — 2.5 — ns taCe CE Access Time — 8 — 10 ns tdOe OE Access Time — 5.5 — 6.5 ns tHzOe(2) OE to High-Z Output — 3 — 4 ns tLzOe(2) OE to Low-Z Output 0 — 0 — ns tHzCe(2 CE to High-Z Output 0 3 0 4 ns tLzCe(2) CE to Low-Z Output 3 — 3 — ns tba LB, UB Access Time — 5.5 — 6.5 ns tHzb(2) LB, UB to High-Z Output 0 3 0 3 ns tLzb(2) LB, UB to Low-Z Output 0 — 0 — ns tPu Power Up Time 0 — 0 — ns tPd Power Down Time — 8 — 10 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.

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10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -20 ns Symbol Parameter Min. Max. Unit trC Read Cycle Time 20 — ns taa Address Access Time — 20 ns tOHa Output Hold Time 2.5 — ns taCe CE Access Time — 20 ns tdOe OE Access Time — 8 ns tHzOe(2) OE to High-Z Output 0 8 ns tLzOe(2) OE to Low-Z Output 0 — ns tHzCe(2 CE to High-Z Output 0 8 ns tLzCe(2) CE to Low-Z Output 3 — ns tba LB, UB Access Time — 8 ns tHzb LB, UB to High-Z Output 0 8 ns tLzb LB, UB to Low-Z Output 0 — ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL t RC t OHAt AA t DOE t LZOE t ACE t LZCE t HZOE HIGH-Z DATA VALID CE_RD2.eps ADDRESS OE CE DOUT t HZCE READ CYCLE NO. 2(1,3) (CE and OE Controlled) Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = ViL. 3. Address is valid prior to or coincident with CE LOW transitions. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = ViL) DATA VALID READ1.eps PREVIOUS DATA VALID t AA t OHA t OHA t RC DOUT ADDRESS

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12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 -10 Symbol Parameter Min. Max. Min. Max. Unit twC Write Cycle Time 8 — 10 — ns tsCe CE to Write End 6.5 — 8 — ns taw Address Setup Time 6.5 — 8 — ns to Write End tHa Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tPwb LB, UB Valid to End of Write 6.5 — 8 — ns tPwe1 WE Pulse Width 6.5 — 8 — ns tPwe2 WE Pulse Width (OE = LOW) 8.0 — 10 — ns tsd Data Setup to Write End 5 — 6 — ns tHd Data Hold from Write End 0 — 0 — ns tHzwe(2) WE LOW to High-Z Output — 3.5 — 5 ns tLzwe(2) WE HIGH to Low-Z Output 2 — 2 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initi- ate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -20 ns Symbol Parameter Min. Max. Unit twC Write Cycle Time 20 — ns tsCe CE to Write End 12 — ns taw Address Setup Time 12 — ns to Write End tHa Address Hold from Write End 0 — ns tsa Address Setup Time 0 — ns tPwb LB, UB Valid to End of Write 12 — ns tPwe1 WE Pulse Width (OE = HIGH) 12 — ns tPwe2 WE Pulse Width (OE = LOW) 17 — ns tsd Data Setup to Write End 9 — ns tHd Data Hold from Write End 0 — ns tHzwe(3) WE LOW to High-Z Output — 9 ns tLzwe(3) WE HIGH to Low-Z Output 3 — ns Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.

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14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) DATA UNDEFINED t WC VALID ADDRESS t SCE t PWE1 t PWE2 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CE WE DOUT DIN DATAIN VALID t LZWE t SD CE_WR1.eps

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) DATA UNDEFINED LOW t WC VALID ADDRESS t PWE1 t AW t HA HIGH-Z t PBW t HD t SA t HZWE ADDRESS CE UB, LB WE DOUT DIN OE DATAIN VALID t LZWE t SD UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) DATA UNDEFINED t WC VALID ADDRESS LOW LOW t PWE2 t AW t HA HIGH-Z t PBW t HD t SA t HZWE ADDRESS CE UB, LB WE DOUT DIN OE DATAIN VALID t LZWE t SD UB_CEWR3.eps

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16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) DATA UNDEFINED t WC ADDRESS 1 ADDRESS 2 t WC HIGH-Z t PBW WORD 1 LOW WORD 2 UB_CEWR4.eps t HD t SA t HZWE ADDRESS CE UB, LB WE DOUT DIN OE DATAIN VALID t LZWE t SD t PBW DATAIN VALID t SD t HD t SA t HA t HA Notes: 1. The internal Write time is defined by the overlap of CE = LOw, UB and/or LB = LOw, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t Ha, t sd, and t Hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 17 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL DATA RETENTION WAVEFORM (CE Controlled) VDD CE ≥ VDD - 0.2V tSDR tRDR VDR CE GND 1.65V 1.4V Data Retention Mode DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 1.2 3.6 V idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V Ind. — 20 mA Auto. — 50 tsdr Data Retention Setup Time See Data Retention Waveform 0 — ns trdr Recovery Time See Data Retention Waveform trC — ns

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18 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) Order Part No. Package 10 (81) IS61WV102416BLL-10MI 48 mini BGA (9mm x 11mm) IS61WV102416BLL-10MLI 48 mini BGA (9mm x 11mm), Lead-free IS61WV102416BLL-10TLI TSOP (Type I), Lead-free Note: 1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V - 3.6V Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) Order Part No. Package 20 IS61WV102416ALL-20MI 48 mini BGA (9mm x 11mm) IS61WV102416ALL-20MLI 48 mini BGA (9mm x 11mm), Lead-free IS61WV102416ALL-20TLI TSOP (Type I), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) Order Part No. Package 10 IS64WV102416BLL-10MA3 48 mini BGA (9mm x 11mm) IS64WV102416BLL-10MLA3 48 mini BGA (9mm x 11mm), Lead-free IS64WV102416BLL-10CTLA3 TSOP (Type I), Copper Leadframe, Lead-free

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 19 Rev. G 06/02/2014 IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL 2. R ef er en ce d oc um en t : J E D E C M O -2 07 1. C O N TR O LL IN G D IM E N S IO N : M M . N O TE : 08 /2 1/ 20 08

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Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

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