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ISL6123IRZA

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ISL6123IRZA

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Part Number ISL6123IRZA
Manufacturer Renesas Electronics America
Description IC POWER SUPPLY SEQUENCER 24QFN
Datasheet ISL6123IRZA Datasheet
Package 24-VFQFN Exposed Pad
In Stock 977 piece(s)
Unit Price $ 6.0200 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 24 - Sep 29 (Choose Expedited Shipping)
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Part Number # ISL6123IRZA (PMIC - Power Supply Controllers, Monitors) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ISL6123IRZA Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - PMIC - Power Supply Controllers, Monitors
Datasheet ISL6123IRZADatasheet
Package24-VFQFN Exposed Pad
Series-
ApplicationsPower Supply Sequencer
Voltage - Input-
Voltage - Supply1.5 V ~ 5.5 V
Current - Supply200µA
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case24-VFQFN Exposed Pad
Supplier Device Package24-QFN-EP (4x4)

ISL6123IRZA Datasheet

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FN9005 Rev 1.00 September 26, 2012 ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 DATASHEETThe Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128 and ISL6130 are integrated 4-channel controlled-on/controlled-off power-supply sequencers with supply monitoring, fault protection and a “sequence completed” signal (RESET). For larger systems, more than four supplies can be sequenced by simply connecting a wire between the SYSRESET pins of cascaded ICs. The ISL6125 uses four active open-drain outputs to control the on/off sequencing of four supplies. The other sequencers use a patented, micropower 7x charge pump to drive four external low-cost NFET switch gates above the supply rail by 5.3V. These ICs can be biased from 5V down to 1.5V by any supply. The 4-channel ISL6123 (ENABLE input), ISL6124 (ENABLE input) and ISL6125 offer the designer 4-rail control when all four rails must be in minimal compliance before turn-on and during operation. The ISL6123 and ISL6130 have a low-power standby mode when disabled, which is suitable for battery-powered applications. The ISL6125 operates like the ISL6124, but instead of charge-pump-driven gate drive outputs, it has open-drain logic outputs for direct interface to other circuitry. In contrast, for the ISL6126 and ISL6130, each of the four channels operates independently. Each GATE turns on once its individually associated input voltage requirements are met. The ISL6127 is a pre-programmed A-B-C-D turn-on and D-C-B-A turn-off sequenced IC. Once all inputs are in compliance and ENABLE is asserted, sequencing begins. Each subsequent GATE turns on after the previous one turns on. The ISL6128 has two groups of two channels, each with its independent I/O. It is ideal for voltage sequencing into redundant capability loads. All four inputs must be satisfied before turn-on, but a single group fault is ignored by the other group. External resistors provide flexible voltage threshold programming of monitored rail voltages. Delay and sequencing are provided by external capacitors for ramp-up and ramp-down. Additional I/O is provided for indicating and driving the RESET state in various configurations. For volume applications, other programmable options and features are available. Contact Intersil sales support with your needs. Features • Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four Power Supplies (0.7V to 5V) • Operates From 1.5V to 5V Supply Voltage • Supplies VDD +5.3V of Charge Pumped Gate Drive • Adjustable Voltage Slew Rate for Each Rail • Multiple Sequencers Can be Daisy-Chained to Sequence an Infinite Number of Independent Supplies • Glitch Immunity • Undervoltage Lockout for Each Supply • 1µA Sleep State (ISL6123, ISL6130) • Active High (ISL6123, ISL6130) ENABLE or Low (ISL6124, ISL6125, ISL6126, ISL6127, ISL6128) ENABLE Input • Active Open Drain Version Available (ISL6125) • Voltage-determined Sequence (ISL6126, ISL6130) • Pre-programmed Sequence Available (ISL6127) • Dual Channel Groupings (ISL6128) • QFN Package • Pb-free (RoHS-compliant) Applications • Graphics Cards • FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing • Network Routers • Telecommunications Systems FIGURE 1. TYPICAL ISL6123 APPLICATION V1OUT V2OUT V3OUT V4OUT UVLO_B UVLO_A UVLO_D UVLO_C D LY _ O N _A D LY _ O F F _ A D LY _ O F F _ B D LY _ O F F _ C D LY _ O F F _ D D LY _ O N _B D LY _ O N _C D LY _ O N _D G A T E D G A T E C G A T E B G A T E A V1 V2 V3 V4 ENABLE SYSRST GROUND RESET VDDFN9005 Rev 1.00 Page 1 of 23 September 26, 2012

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL6123IRZA 61 23IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL6124IRZA 61 24IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL6125IRZA 61 25IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL6126IRZA 61 26IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL6127IRZA 61 27IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL6128IRZA 61 28IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL6130IRZA 61 30IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4 ISL6123EVAL1Z ISL6123 Evaluation Platform ISL6125EVAL1Z ISL6125 Evaluation Platform NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130. For more information on MSL please see Tech Brief TB363. FIGURE 2. ISL6125 APPLICATION FIGURE 3. ISL6123 BLOCK DIAGRAM (1/4) V1OUT V2OUT V3OUT V4OUT UVLO_B UVLO_A UVLO_D UVLO_C D LY _O N _A D LY _ O F F _ A D LY _ O F F _ B D LY _ O F F _ C D LY _O F F _ D D LY _O N _B D LY _O N _C D LY _O N _D O U T D O U T C O U T B O U T A S1 S2 S4 ENABLE SYSRST GROUND RESET VDD S3 en en en en P1 P2 P3 ISL6125 EN SYSRST UVLOX 0.633V RESET DLY_ONX 1.26V DLY_OFFX 1.26V GATEX LOGIC 1µA BIAS LOCK OUT VDD RISING DELAY VDD+5V Q-PUMP 1µA 1µA -1µA 30µs FILTER 150ms RISING DELAY 10msFN9005 Rev 1.00 Page 2 of 23 September 26, 2012

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130Pin Configurations ISL6123, ISL6124, ISL6125 (24 LD QFN) TOP VIEW ISL6126, ISL6130 (24 LD QFN) TOP VIEW ISL6127 (24 LD QFN) TOP VIEW ISL6128 (24 LD QFN) TOP VIEW 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 EPAD ENABLE_1/ ENABLE_1 GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C G A T E _ D D LY _O N _ B N C G N D U V L O _ B DLY_OFF_B UVLO_D DLY_ON_D DLY_ON_C UVLO_C DLY_OFF_A N C U V L O _ A D LY _ O N _ A S Y S R S T V D D R E S E T (GND) N C *OUTPUT_A *OUTPUT_B *OUTPUT_C *O U T P U T _ D *OUTPUT_A, OUTPUT_B, OUTPUT_C, OUTPUT_D ARE UNIQUE TO ISL6125 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 EPAD ENABLE_1/ ENABLE_1 GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C G A T E _ D N C N C G N D U V L O _ B DLY_OFF_B UVLO_D NC NC UVLO_C DLY_OFF_A N C U V L O _ A N C N C V D D R E S E T (GND) N C 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 EPAD ENABLE_1/ ENABLE_1 GATE_A NC NC GATE_B GATE_C G A T E _ D N C N C G N D U V L O _ B NC UVLO_D NC NC UVLO_C NC N C U V L O _ A N C S Y S R S T V D D R E S E T (GND) N C 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 EPAD ENABLE_1 GATE_A DLY_OFF_C DLY_OFF_D GATE_B GATE_C G A T E _D D LY _ O N _B R E S E T _ 2 G N D U V L O _B DLY_OFF_B UVLO_D DLY_ON_D DLY_ON_C UVLO_C DLY_OFF_A N C U V L O _ A D LY _ O N _ A N C V D D R E S E T (GND) E N A B L E _ 2 FN9005 Rev 1.00 Page 3 of 23 September 26, 2012

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130Pin Descriptions PIN NAME PIN NUMBER DESCRIPTION ISL6123, ISL6124, ISL6125 ISL6126, ISL6130 ISL6127 ISL6128 VDD 23 23 23 23 Chip Bias. Bias IC from nominal 1.5V to 5V. GND 10 10 10 10 Bias Return. IC ground. ENABLE_1/ ENABLE_1 1 1 1 1 Input to start on/off sequencing. Input to initiate start of programmed sequencing of supplies on or off. Enable functionality disabled for 10ms after UVLO is satisfied. ISL6123 and ISL6130 have ENABLE, and ISL6124, ISL6125, ISL6126 and ISL6127 have ENABLE. Only ISL6128 has two ENABLE inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and ENABLE_2 is for (C, D). ENABLE_2/ ENABLE_2 NC NC NC 11 RESET 24 24 24 24 RESET Output. RESET provides low signal 150ms after all GATEs are fully enhanced. Delay is for stabilization of output voltages. RESET asserts low upon UVLO not being satisfied or ENABLE/ENABLE being deasserted. RESET outputs are open-drain, N-channel FET and are guaranteed to be in correct state for VDD down to 1V and are filtered to ignore fast transients on VDD and UVLO_X. RESET_2 only exists on ISL6128 for (C, D) group I/O. RESET_2 NC NC NC 9 UVLO_A 20 20 20 20 Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout referenced to an internal 0.633V reference. Filtered to ignore short (<30µs) transients below programmed UVLO level. UVLO_B 12 12 12 12 UVLO_C 17 17 17 17 UVLO_D 14 14 14 14 DLY_ON_A 21 21 Gate On Delay Timer Output. Allows programming of delay and sequence for VOUT turn-on using a capacitor to ground. Each capacitor charged with 1µA 10ms after turn-on initiated by ENABLE/ENABLE. Internal current source provides delay to associated FET GATE turn-on. DLY_ON_B 8 8 DLY_ON_C 16 16 DLY_ON_D 15 15 DLY_OFF_A 18 18 18 Gate Off Delay Timer Output. Allows programming of delay and sequence for VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each capacitor charged with 1µA internal current source to an internal reference voltage, causing corresponding gate to be pulled down, thus turning off FET. DLY_OFF_B 13 13 13 DLY_OFF_C 3 3 3 DLY_OFF_D 4 4 4 GATE_A 2 2 2 2 FET Gate Drive Output. Drives external FETs with 1µA current source to soft- start ramp into load.GATE_B 5 5 5 5 GATE_C 6 6 6 6 GATE_D 7 7 7 7 OUTPUT_A 2 (ISL6125) On ISL6125 only, these are ACTIVE open drain outputs that can be pulled up to a maximum of VDD voltage.OUTPUT_B 5 (ISL6125) OUTPUT_C 6 (ISL6125) OUTPUT_D 7 (ISL6125) SYSRST 22 22 System Reset I/O. As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This input can also be used to initiate programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input signal on this pin being driven high to first GATE. As an output, when there is a UV condition, this pin pulls low. If common to other SYSRST pins in a multiple IC configuration, it causes immediate and unconditional latch-off of all other GATEs on all other ISL612X sequencers. GND EPAD EPAD EPAD EPAD Ground. Die Substrate. Can be left floating. NC 9, 19 8, 9, 11, 15, 16, 19, 21, 22 3, 4, 8, 9, 11, 13, 15,16,18, 19, 21 19, 22 No ConnectFN9005 Rev 1.00 Page 4 of 23 September 26, 2012

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130ISL612X and ISL6130 Variant Feature Matrix PART NAME EN/EN CMOS/ TTL GATE DRIVE OR OPEN DRAIN OUTPUTS REQUIRED CONDITIONS FOR INITIAL START-UP NUMBER OF UVLO INPUTS MONITORED BY EACH RESET NUMBER OF CHANNELS THAT TURN OFF WHEN ONE UVLO FAULTS PRESET OR ADJUSTABLE SEQUENCE NUMBER OF UVLO AND PAIRS OF I/O FEATURES ISL6123 EN TTL Gate Drive 4 UVLO 1 EN 4 UVLO 4 Gates Time Adjustable On and Off 4 Monitors with 1 I/O Auto Restart, Low Bias Current Sleep ISL6124 EN CMOS Gate Drive 4 UVLO 1 EN 4 UVLO 4 Gates Time Adjustable On and Off 4 Monitors with 1 I/O Auto Restart ISL6125 EN CMO Open Drain 4 UVLO 1 EN 4 UVLO 4 Open Drain Time Adjustable On and Off 4 Monitors with 1 I/O Auto Restart, Open Drain Sequenced Outputs ISL6126 EN CMOS Gate Drive 1 UVLO 1 EN 4 UVLO 1 Gate Voltage Determined ON Time Adjustable Off 4 Monitors with 1 I/O Gates Independent On as UVLO Valid ISL6127 EN CMOS Gate Drive 4 UVLO 1 EN 4 UVLO 4 Gates Preset 4 Monitors with 1 I/O Auto Restart ISL6128 EN CMOS Gate Drive 4 UVLO 2 EN 2 UVLO 2 Gates Preset 2 Monitors with 2 I/O Dual Redundant Operation ISL6130 EN TTL Gate Drive 1 UVLO 1 EN 4 UVLO 1 Gate Voltage Determined ON Time Adjustable Off 4 Monitors with 1 I/O Gates Independent On as UVLO Valid Low Bias Current SleepFN9005 Rev 1.00 Page 5 of 23 September 26, 2012

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130Absolute Maximum Ratings (Note 6) Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V ISL6125 LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V UVLO, ENABLE, ENABLE, SYSRST . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V RESET, DLY_ON, DLYOFF . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V Operating Conditions VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.5V to +5.5V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 24 Ld 4x4 QFN Package (Notes 4, 5) . . . . . 46 8 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 6. All voltages are relative to GND, unless otherwise specified. Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT UVLO Falling Undervoltage Lockout Threshold VUVLOvth TJ = +25°C 619 633 647 mV Undervoltage Lockout Threshold Tempco TCUVLOvth 40 µV/°C Undervoltage Lockout Hysteresis VUVLOhys 10 mV Undervoltage Lockout Threshold Range RUVLOvth Max VUVLOvth- Min VUVLOvth 7 mV Undervoltage Lockout Delay TUVLOdel ENABLE satisfied 10 ms Transient Filter Duration tFIL VDD, UVLO, ENABLE glitch filter 30 µs DELAY ON/OFF Delay Charging Current DLY_ichg VDLY = 0V 0.92 1 1.08 µA Delay Charging Current Range DLY_ichg_r DLY_ichg(max) - DLY_ichg(min) 0.08 µA Delay Charging Current Temperature Coefficient TC_DLY_ichg 0.2 nA/°C Delay Threshold Voltage DLY_Vth 1.238 1.266 1.294 V Delay Threshold Voltage Temperature Coefficient TC_DLY_Vth 0.2 mV/°C ENABLE/ENABLE, RESET AND SYSRST I/O ENABLE Threshold VENh 1.2 V ENABLE Threshold VENh 0.5 VDD V ENABLE/ENABLE Hysteresis VENh -VENl Measured at VDD = 1.5V 0.2 V ENABLE/ENABLE Lockout Delay tdelEN_LO UVLO satisfied 10 ms ENABLE/ENABLE Input Capacitance Cin_en 5 pF RESET Pull-up Voltage Vpu_rst VDD V RESET Pull-Down Current IRSTpd1 VDD = 1.5V, RST = 0.1V 5 mA IRSTpd3 VDD = 3.3V, RST = 0.1V 13 mA IRSTpd5 VDD = 5V, RST = 0.1V 17 mAFN9005 Rev 1.00 Page 6 of 23 September 26, 2012

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130Descriptions and Operation The ISL612X sequencer family consists of several 4-channel voltage sequencing controllers in various functional and personality configurations. All are designed for use in multiple-voltage systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD + 5.3V (VQP) in a user-programmed sequence. With the 4-channel ISL6123, ENABLE must be asserted high, and all four voltages to be sequenced must be above their respective user-programmed undervoltage lockout (UVLO) levels before programmed output turn-on sequencing can begin. Sequencing order and delay are determined by the choice of external capacitor values on the DLY_ON and RESET Delay after GATE High TRSTdel GATE = VDD+5V 160 ms RESET Output Low VRSTl Measured at VDD = 5V with 5k pull-up resistors 0.1 V RESET Output Capacitance COUT_RST 10 pF SYSRST Pull-Up Voltage Vpu_srst VDD V SYSRST Pull-Down Current Ipu_1.5 VDD = 1.5V 5 µA Ipu_5 VDD = 5V 100 µA SYSRST Low Output Voltage Vol_srst VDD = 1.5V, IOUT = 100µA 150 mV SYSRST Output Capacitance Cout_srst 10 pF SYSRST Low to GATE Turn-Off tdelSYS_G GATE = 80% of VDD + 5V 40 ns GATE GATE Turn-On Current IGATEon GATE = 0V 0.8 1.1 1.4 µA GATE Turn-Off Current IGATEoff_l GATE = VDD, Disabled -1.4 -1.05 -0.8 µA GATE Current Range IGATE_range Within IC IGATE max-min 0.35 µA GATE Turn-On/Off Current Temperature Coefficient TC_IGATE 0.2 nA/°C GATE Pull-Down High Current IGATEoff_h GATE = VDD, UVLO = 0V 88 mA GATE High Voltage VGATEh VDD < 2V, TJ = +25°C VDD + 4.9V V VGATEh VDD > 2V VDD + 5V VDD + 5.3V V GATE Low Voltage VGATEl Gate Low Voltage, VDD = 1V 0 0.1 V ISL6125 OPEN DRAIN Open Drain On Resistance RDSON_5V VDD = 5V, EN = VDD 25  RDSON_3.3V VDD = 3.3V, EN = VDD 32  RDSON_2.5V VDD = 2.5V, EN = VDD 40  BIAS IC Supply Current IVDD_5V VDD = 5V 0.20 0.5 mA IVDD_3.3V VDD = 3.3V 0.14 mA IVDD_1.5V VDD = 1.5V 0.10 mA ISL6123, ISL6130 Stand By IC Supply Current IVDD_sb VDD = 5V, ENABLE = 0V 1 µA VDD Power-on Reset VDD_POR 1 V NOTE: 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITFN9005 Rev 1.00 Page 7 of 23 September 26, 2012

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ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130DLY_OFF pins. Once all four UVLO inputs and ENABLE are satisfied for 10ms (tdelEN_LO), the four DLY_ON capacitors are simultaneously charged with 1µA current sources to the DLY_Vth level of 1.27V. As each DLY_ON pin reaches the DLY_Vth level, its associated GATE turns on, with a 1µA source current to the charge pump voltage (VQP) of VDD + 5.3V. Thus, all four GATEs sequentially turn on in the user defined order. Once at DLY_Vth, the DLY_ON pins discharge so they are ready when next needed. After the entire turn-on sequence has been completed and all GATEs have reached the charge pumped voltage (VQP), a 160ms delay (TRSTdel) is started to ensure stability, after which the RESET output is released to go high. After turn-on, if any input falls below its UVLO point for longer than the glitch filter period (~30µs), it is considered a fault. RESET and SYSRST are pulled low, and all GATEs are simultaneously also pulled low. In this mode, the GATEs are pulled low with 88mA. Normal shutdown mode is entered when no UVLO is violated and ENABLE is deasserted. When ENABLE is deasserted, RESET is immediately asserted and pulled low. Next, all four shutdown ramp capacitors on the DLY_OFF pins are charged with a 1µA source. When any ramp-capacitor reaches DLY_Vth, a latch is set, and a current is sunk on the respective GATE pin to turn off its external MOSFET. When the GATE voltage is approximately 0.6V, the GATE is pulled down the rest of the way at a higher current level. Each individual external FET is thus turned off, which removes the voltages from the load in the user programmed sequence. The ISL6123 and ISL6124 have the same functionality, except for the ENABLE active polarity; the ISL6124 has an ENABLE input. Additionally, the ISL6123 and ISL6130 also have an ultra low-power sleep state when ENABLE is low. The ISL6125 has the same personality as the ISL6124, but instead of charged-pump-driven GATE outputs, it has open-drain outputs that can be pulled up to a maximum of VDD. The ISL6126 and ISL6130 are different in that their on sequence is not time determined but voltage determined. Each of the four channels operate independently. Once the IC is biased and any one of the UVLO inputs is greater than the 0.63V internal reference, and the ENABLE input is also satisfied, the associated GATE for the satisfied UVLO input turns on. In turn, the other UVLO inputs must be satisfied for the associated GATEs to turn on. After a period of 160ms (TRSTdel) once all GATEs are fully on (GATE voltage = VQP), RESET is released to go high. The UVLO inputs can be driven by either a previously turned-on output rail offering a voltage-determined sequence or by logic signal inputs. Any subsequent UVLO level that is less than its programmed level pulls the associated GATE and RESET output low (if previously released) but does not latch-off the other GATEs. Predetermined turn-off is accomplished by deasserting ENABLE. This causes RESET to latch low and all four GATE outputs to follow the programmed turn-off sequence, similarly to the ISL6124. The ISL6127 is a 4-channel sequencer pre-programmed for A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and ENABLE inputs are satisfied for ~10ms, the sequencing starts. The next GATE in the sequence starts to ramp up once the previous GATE has reached ~VQP-1V. After a period of 160ms (TRSTdel) after the last GATE is at VQP, the RESET output is deasserted. If any UVLO is unsatisfied, RESET is pulled low, SYSRST is pulled low, and all GATEs are simultaneously turned off. When ENABLE is signaled high, the D GATE starts to pull low. Once below 0.6V, the next GATE starts to pull low, and so on, until all GATEs are at 0V. Unloaded, this turn-off sequence completes in <1ms. This variant offers a lower cost and size implementation because the external delay capacitors are not used. Because the delay capacitors are not used, this IC cannot delay the start of subsequent GATEs. Thus, necessary stabilization or system housekeeping need to be considered. The ISL6128 is a 4-channel device that groups the four channels into two groups of two channels each. Each group of A, B and C, D, has its own ENABLE and RESET I/O pins. All four UVLO and both ENABLEs must be satisfied for sequencing to start. The A, B group turns on first, 10ms after the second ENABLE is pulled low, with A then B turning on, followed by C then D. Once the preceding GATE = VQP, the next DLY_ON pin starts to charge its capacitor; thus, all four GATEs turn on. Approximately 160ms after D GATE = VQP, the RESET output is released to go high. Once any UVLO is unsatisfied, only the related group’s RESET and two GATEs are pulled low. The related EN input must be cycled for the faulted group to be turned on again. Normal shutdown is invoked by signaling both ENABLE inputs high, which causes the two related GATEs to shut down in reverse order from turn-on. DLY_X capacitors adjust the delay between GATES during turn-on and turn-off, but not the order. During bias up, the RESET output is guaranteed to be in the correct state, with VDD lower than 1V. Upon power-up, the SYSRST pin follows VDD with a weak internal pull-up. It is both an input and an output connection and can provide two functions. As an input, if it is pulled low, all GATEs are unconditionally shut off, and RESET pulls low (Figure 8). This input can also be used as a no-wait enabling input. If all inputs (ENABLE and UVLO) are satisfied, it does not wait through the ~10ms enable delay to initiate DLY_ON capacitor charging when released to go high. As an output, it is useful when implementing multiple sequencers in a design needing simultaneous shutdown, as with a kill switch across all sequencers. Once any UVLO is unsatisfied longer than tFIL, the related SYSRST pulls low. It also pulls low all other SYSRST inputs that are on a common connection. By doing so, it unconditionally shuts down all outputs across multiple sequencers. Except for the ISL6128 after a fault, restart of the turn-on sequence is automatic, once all requirements are met. This allows for no interaction between the sequencer and a controller IC, if desired. The ENABLE and RESET I/O do allow for a higher FN9005 Rev 1.00 Page 8 of 23 September 26, 2012

Page 10

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130level of feedback and control, if desired. The ISL6128 requires that the related ENABLE be cycled for restart of its associated group GATEs. If no capacitors are connected between DLY_ON or DLY_OFF pins and ground, then all such related GATEs start to turn on immediately after the 10ms (TUVLOdel) ENABLE stabilization timeout has expired. The GATEs start to turn off immediately when ENABLE is asserted. If some of the rails are sequenced together to reduce cost and eliminate the effect of capacitor variance on the timing, a common capacitor can be connected to two or more DLY_ON or DLY_OFF pins. In this case, multiply the capacitor value by the number of common DLY_X pins to obtain the desired timing. Table 1 shows the nominal time delay on the DLY_X pins for various capacitor values, from the start of charging to the 1.27V reference. This table does not include the 10ms of ENABLE lockout delay during a start-up sequence, but it does represent the time from the end of the ENABLE lockout delay to the start of GATE transition. There is no ENABLE lockout delay for a sequence-off, so this table illustrates the delay to GATE transition from a disable signal. Figure 4 shows the turn-on and Figure 5 shows the nominal turn-off timing diagram of the ISL6123 and ISL6124. The ISL6125 is similar to the ISL6124 except that, instead of charge pumped GATE outputs, there are sequenced open-drain outputs that can be pulled up to a maximum of VDD. Delay and flexible sequencing possibilities include multiple series, parallel, or adjustable capacitors that can be used to easily fine-tune timing over that offered by standard value capacitors. TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE TIME(s) Open 0.00006 100pF 0.00013 1000pF 0.0013 0.01µF 0.013 0.1µF 0.13 1µF 1.3 10µF 13 NOTE: Nom. TDEL_SEQ = Capacitor (µF)*1.3M. FIGURE 4. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM UVLO_B UVLO_C UVLO_D ENABLE (ISL6123) RESET DLYON_A DLYON_B DLYON_C DLYON_D GATE_A GATE_B GATE_C GATE_D UVLO_A VEN DLY_Vth DLY_Vth DLY_Vth DLY_Vth VQPUMP VQPUMP VQPUMP ENABLE (ISL6124) VUVLOVth VUVLOVth VUVLOVth VUVLOVth tRSTdel tUVLOdel VQPUMP-1V VQPUMP

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Kars*****ayre

August 21, 2020

Competitively priced set of diodes, tested as described. Quality is about what you would expect for no- or off-brand.

Sami*****ggins

August 21, 2020

It's so nice to have all these babies. I was using so many for projects, I decided to buy these. They'll definitely last me a while!

Riv*****Oak

August 1, 2020

FAST POSTING TOP CONDITION RECORD HAVE A GREAT CHRISTMAS

Kas*****hakta

July 13, 2020

I've had no issues. Good product, would buy again.

Egyp*****rmon

July 13, 2020

Everything perfect. Great seller.

Niko*****well

July 10, 2020

Super easy to replace and labelled terminals made it a quick replacement.

Cassi*****arson

July 10, 2020

Items arrived well pakaged, reasonable postage and as described. Top seller

Spen*****Morse

July 8, 2020

Happy with purchase, would do business again

Isai*****hadha

July 8, 2020

Great product & fast shipping. Works as they should.

Broo*****avala

July 3, 2020

Excellent company. Product as described. Usually fast and well packed.Very nice.

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