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ISL88705IP846Z

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ISL88705IP846Z

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Part Number ISL88705IP846Z
Manufacturer Renesas Electronics America
Description IC SUPERVISOR MPU 4.64V 8-DIP
Datasheet ISL88705IP846Z Datasheet
Package 8-DIP (0.300", 7.62mm)
In Stock 7,236 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 28 - Nov 2 (Choose Expedited Shipping)
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Part Number # ISL88705IP846Z (PMIC - Supervisors) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ISL88705IP846Z Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - PMIC - Supervisors
Datasheet ISL88705IP846ZDatasheet
Package8-DIP (0.300", 7.62mm)
Series-
TypeSimple Reset/Power-On Reset
Number of Voltages Monitored1
OutputOpen Drain or Open Collector
ResetActive Low
Reset Timeout140 ms Minimum
Voltage - Threshold4.64V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeThrough Hole
Package / Case8-DIP (0.300", 7.62mm)
Supplier Device Package8-PDIP

ISL88705IP846Z Datasheet

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FN8092 Rev 6.00 November 30, 2015 ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813 DATASHEETDesigned with high reset threshold accuracy and low power consumption, the ISL88705, ISL88706, ISL88707, ISL88708, ISL88716 and ISL88813 devices are microprocessor supervisors that are designed to monitor power-supply and battery functions in microprocessor systems. They can help to lower system cost, reduce board space requirements and increase the reliability of systems. These devices provide essential functions such as supply voltage supervision by asserting a reset output during power-up and power-down as well as during brownout conditions. An auxiliary voltage monitor is provided for detecting power failures warning the system of low battery conditions or presence detection. In addition, an independent watchdog timer helps to monitor microprocessor activity every 1.6s (typical). An active-low manual reset is offered and reset signals remain asserted until VDD returns to proper operating levels. Users can increase the nominal 200ms power-on reset time-out delay by adding an external capacitor to the CPOR pin on the ISL88707 and ISL88708. Features • Fixed-Voltage Options Allow Precise Monitoring of +3.0V, +3.3V, and +5.0V Power Supplies • Additional Voltage Monitor for Power-Fail Detection or Low-Battery Warning - Monitors Voltages Down to 1.25V - Adjustable Power-Fail Input Threshold • Watchdog Timer Capability With 1.6s Time-out • Both RST and RST Outputs Available • 140ms Minimum Reset Pulse Width with Option to Customize Using an External Capacitor • Manual Reset Input on all Devices • Reset Signal Valid Down to VDD = 1V • Accurate ±1.8% Voltage Threshold • Immune to Power-Supply Transients • Ultra Low 10µA Maximum Supply Current at 3V • Pb-Free (RoHS Compliant) Applications • Portable/Battery Powered Equipment • Notebook/Desktop Computer Systems • Designs Using DSPs, Microcontrollers or Microprocessors • Controllers • Intelligent Instruments • Communications Systems • Industrial Equipment Pinouts ISL88705, ISL88706 (8 LD SOIC) (PDIP - NO LONGER AVAILABLE) TOP VIEW ISL88716, ISL88813 (8 LD SOIC) (PDIP - NO LONGER AVAILABLE) TOP VIEW ISL88707, ISL88708 (8 LD SOIC) (PDIP - NO LONGER AVAILABLE) TOP VIEW 1 2 3 4 8 7 6 5 VDD GND PFI WDO RST WDI PFO MR 1 2 3 4 8 7 6 5 VDD GND PFI WDO RST WDI PFO MR 1 2 3 4 8 7 6 5 VDD GND PFI RST RST CPOR PFO MRFN8092 Rev 6.00 Page 1 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813Ordering Information PART NUMBER (Note) PART MARKING VTH TEMP RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL88705IP846Z (No longer available, recommended replacement: ISL88705IB846Z) 88705 I46Z 4.64V -40 to +85 8 Ld PDIP** MDP0031 ISL88813IP846Z (No longer available, recommended replacement: ISL88813IB846Z) 88813 I46Z 4.64V -40 to +85 8 Ld PDIP** MDP0031 ISL88707IP846Z (No longer available, recommended replacement: ISL88707IB846Z) 88707 I46Z 4.64V -40 to +85 8 Ld PDIP** MDP0031 ISL88706IP844Z (No longer available, recommended replacement: ISL88706IB844Z) 88706 I44Z 4.38V -40 to +85 8 Ld PDIP** MDP0031 ISL88708IP844Z (No longer available, recommended replacement: ISL88708IB844Z) 88708 I44Z 4.38V -40 to +85 8 Ld PDIP** MDP0031 ISL88706IP831Z (No longer available, recommended replacement: ISL88706IB831Z) 88706 I31Z 3.09V -40 to +85 8 Ld PDIP** MDP0031 ISL88708IP831Z (No longer available, recommended replacement: ISL88708IB831Z) 88708 I31Z 3.09V -40 to +85 8 Ld PDIP** MDP0031 ISL88706IP829Z (No longer available, recommended replacement: ISL88706IB829Z) 88706 I29Z 2.92V -40 to +85 8 Ld PDIP** MDP0031 ISL88708IP829Z (No longer available, recommended replacement: ISL88708IB829Z) 88708 I29Z 2.92V -40 to +85 8 Ld PDIP** MDP0031 ISL88706IP826Z (No longer available, recommended replacement: ISL88706IB826Z) 88706 I26Z 2.63V -40 to +85 8 Ld PDIP** MDP0031 ISL88716IP826Z (No longer available, recommended replacement: ISL88716IB826Z) 88716 I26Z 2.63V -40 to +85 8 Ld PDIP** MDP0031 ISL88708IP826Z (No longer available, recommended replacement: ISL88708IB826Z) 88708 I26Z 2.63V -40 to +85 8 Ld PDIP** MDP0031 ISL88705IB846Z* 88705 I46Z 4.64V -40 to +85 8 Ld SOIC M8.15 ISL88813IB846Z* 88813 I46Z 4.64V -40 to +85 8 Ld SOIC M8.15 ISL88707IB846Z* 88707 I46Z 4.64V -40 to +85 8 Ld SOIC M8.15 ISL88706IB844Z* 88706 I44Z 4.38V -40 to +85 8 Ld SOIC M8.15 ISL88708IB844Z* 88708 I44Z 4.38V -40 to +85 8 Ld SOIC M8.15 ISL88706IB831Z* 88706 I31Z 3.09V -40 to +85 8 Ld SOIC M8.15 ISL88708IB831Z* 88708 I31Z 3.09V -40 to +85 8 Ld SOIC M8.15 ISL88706IB829Z* 88706 I29Z 2.92V -40 to +85 8 Ld SOIC M8.15 ISL88708IB829Z* 88708 I29Z 2.92V -40 to +85 8 Ld SOIC M8.15 ISL88706IB826Z* 88706 I26Z 2.63V -40 to +85 8 Ld SOIC M8.15 ISL88716IB826Z* 88716 I26Z 2.63V -40 to +85 8 Ld SOIC M8.15 ISL88708IB826Z* 88708 I26Z 2.63V -40 to +85 8 Ld SOIC M8.15 ISL88705EVAL1 Evaluation Board *Add “-TK” suffix for Tape and Reel Packaging. Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.FN8092 Rev 6.00 Page 2 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813Functional Block Diagrams ± VREF VDD POR GND WDT VREF PFI WDI PB WDO PF PFO MR RST ISL88705, ISL88706 VREF VDD POR GND WDT VREF PFI WDI PB WDO PF PFO MR RST ISL88716, ISL88813 VREF VDD POR GNDVREF PFI PB PF PFO MR ISL88707, ISL88708 RST RST CPOROSC ± ± ± ± ± FN8092 Rev 6.00 Page 3 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813Pin Descriptions ISL88705, ISL88706 ISL88716, ISL88813 ISL88707, ISL88708 NAME DESCRIPTION 1 1 1 MR Manual Reset Input. A reset signal is generated when this input is pulled low. The MR input is an active low debounced input to which a user can connect a push-button to add manual reset capability or drive with a signal. The MR pin has an internal 20kpull-up. 2 2 2 VDD Power Supply Terminal. The voltage at this pin is compared against an internal factory-programmed voltage trip point, VTH1. A reset is first asserted when the device is initially powered up to ensure that the power supply has stabilized. Thereafter, reset is again asserted whenever VDD falls below VTH1. The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief power-supply transients. The voltage threshold VTH1 is specified in the part number suffix. 3 3 3 GND Ground Connection 4 4 4 PFI Power-Fail Input This is an auxiliary monitored voltage input with a 1.25V threshold that causes PFO state to follow the PFI input state. 5 5 5 PFO Power-Fail Output. This output goes high if the voltage on PFI is greater than 1.25V, otherwise PFO stays low. 6 CPOR Adjustable POR Time-out Delay Input. Connecting an external capacitor from CPOR to ground allows the user to increase the Power-On Reset time-out (tPOR) from the nominal 200ms. 6 6 WDI Watchdog Input. The Watchdog Input takes an input from a microprocessor and ensures that it periodically toggles the WDI pin, otherwise the internal nominal 1.6s watchdog timer runs out, then reset is asserted and WDO is pulled low. The internal Watchdog Timer is cleared whenever the WDI sees a rising or falling edge or the device is manually reset. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog feature. 7 7 RST Active-Low Reset Output. The RST output is an active low output with an internal PMOS pull-up that is pulled low to GND when reset is asserted. Reset is asserted whenever: 1. The device is first powered up 2. VDD falls below its minimum voltage sense level or 3. MR is asserted. The reset output continues to be asserted for typically 200ms after VDD rises above the reset threshold or MR input goes from low to high. A watchdog time-out will not trigger a reset unless WDO is connected to MR. 7 8 RST Active-High Reset Output. The RST pin functions identically to its complementary RST output but is an active high push-pull output. RST is set high to VDD when reset is asserted. See the RST in “Pin Descriptions” on page 4 for more details on conditions that cause a reset. 8 8 WDO Watchdog Output. This output is pulled low when the nominal 1.6s internal Watchdog Timer expires and periodically resets until the watchdog is cleared. WDO also goes low during low VDD conditions. Whenever VDD is below the reset threshold, WDO stays low. However, unlike RESET, WDO does not have a minimum pulse width. As soon as VDD rises above the reset threshold, WDO goes high with no delay.FN8092 Rev 6.00 Page 4 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813Absolute Maximum Ratings Thermal Information Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on any Pin with Respect to GND . . . . . . . . . . . -1.0V to +7V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Recommended Operating Conditions Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C Thermal Resistance (Typical, Note 1) JA (°C/W) PDIP Package* (4-layer test board) . . . . . . . . . . . . . 83 SOIC Package (4-layer test board) . . . . . . . . . . . . . 110 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Supply Voltage Range 2.0 5.5 V IDD VDD = 5V, WDT Inactive 10 19 µA VDD = 3V, WDT Inactive 8 10 µA ILI Input Leakage Current (PFI) 100 nA ILO Output Leakage Current 100 nA VOLTAGE THRESHOLDS VTH1 Fixed VDD Voltage Trip Point 4.556 4.640 4.724 V 4.301 4.380 4.459 V 3.034 3.090 3.146 V 2.867 2.920 2.973 V 2.583 2.630 2.677 V VTH1HYST Hysteresis at VTH1 Input Temperature = +25°C VTH1 = 4.64V 46 mV VTH1 = 4.38V 44 mV VTH1 = 3.09V 37 mV VTH1 = 2.92V 29 mV VTH1 = 2.63V 31 mV RST AND RST VOL Reset Output Voltage Low VDD  3.3V, Sinking 2.5mA 0.05 0.40 V VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V VOH RST Output Voltage High VDD  3.3V, Sourcing 2.5mA VDD - 0.6 VDD - 0.4 V VDD < 3.3V, Sourcing 1.5mA VDD - 0.6 VDD - 0.4 V RST Output Voltage High VDD  3.3V, Sourcing 0.8mA VDD - 0.6 VDD - 0.4 V VDD < 3.3V, Sourcing 0.5mA VDD - 0.6 VDD - 0.4 V tRPD VTH to Reset Asserted Delay 45 µs tPOR POR Time-Out Delay CPOR is open 140 200 260 ms CLOAD Load Capacitance on Reset Pins 5 pFFN8092 Rev 6.00 Page 5 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813Principles of Operation The ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813 devices provide those functions needed for monitoring critical voltages such as power-supply and battery functions in microprocessor systems. Features of these supervisors include Power-On Reset control, Supply Voltage Supervision, Power-Fail Detection and Manual Reset Assertion. The integration of all these features along with high reset threshold accuracy and low power consumption make these devices ideal for portable or battery-powered equipment. Power-On Reset (POR) Applying power to the device activates a POR circuit which asserts reset (i.e. RST goes high while RST goes low). These signals provide several benefits: • It prevents the system microprocessor from starting to operate with insufficient voltage. • It prevents the processor from operating prior to stabilization of the oscillator. • It ensures that the monitored device is held out of operation until internal registers are properly loaded. • It allows time for an FPGA to download its configuration prior to initialization of the circuit. The reset signals remain active until VDD rises above the minimum voltage sense level for time period tPOR. This ensures that the supply voltage has stabilized to sufficient operating levels. MANUAL RESET VMRL MR Input Voltage Low 0.8 V VMRH MR Input Voltage High VDD - 0.6 V tMR MR Minimum Pulse Width 550 ns RPU Internal MR Pull-Up Resistor 20 k WATCHDOG TIMER (Note 2) tWDT Watchdog Time-out Period 1.0 1.6 2.0 s tWDPS WDI Minimum Pulse Width 100 ns VIL Watchdog Input Voltage Low 0.3 x VDD V VIH Watchdog Input Voltage High 0.7 x VDD V VWDOL WDO Output Voltage Low VDD  3.3V, Sinking 2.5mA 0.05 0.40 V VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V VWDOH WDO Output Voltage High VDD  3.3V, Sourcing 2.5mA VDD - 0.6 VDD - 0.4 V VDD < 3.3V, Sourcing 1.5mA VDD - 0.6 VDD - 0.4 V IWDT Watchdog Input Current 1 µA POWER-FAIL DETECTION VTHPFI PFI Input Threshold Voltage MR = Open 1.20 1.25 1.30 V PFIVTHHYST Hysteresis Voltage 20 mV VPFOL PFO Output Voltage Low VDD  3.3V, Sinking 2.5mA 0.05 0.40 V VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V VPFOH PFO Output Voltage High VDD  3.3V, Sourcing 2.5mA VDD - 0.6 VDD - 0.4 V VDD < 3.3V, Sourcing 1.5mA VDD - 0.6 VDD - 0.4 V NOTE: 2. Applies to ISL88705, ISL88706, ISL88716, and ISL88813. Electrical Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSFN8092 Rev 6.00 Page 6 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813Low Voltage Monitoring These devices monitor both the voltage level of VDD and an auxiliary voltage on PFI. When IC is initially biased reset is asserted until the VDD voltage is greater than the specific IC fixed-voltage trip point for the tPOR duration of 200ms. At any subsequent time that VDD does not exceed its voltage threshold, reset is once again asserted, i.e. RST is high and RST is low (see Figure 1). .Power Failure Monitor These devices also have a Power-Failure Monitor that helps to monitor an additional critical voltage on the Power-Fail Input (PFI) pin. For example, the PFI pin could be used to provide an early power-fail warning, detect a low-battery condition, presence detection or simply monitor a power supply other than +5V. The 1.25V threshold detector can be adjusted using an external resistor divider network to provide custom voltage monitoring of voltages greater than 1.25V, according to Equation 1 (see Figure 2). PFO goes low whenever PFI is less than the 1.25V (or user-set) threshold voltage. . If using a voltage divider on the PFI input to critique an external voltage and intending to use the MR input to initiate resets then avoid having the PFI voltage less than PFI Vth +2.2V as unintended PFO transition may occur when MR is transitioning high. Adjusting tPOR On the ISL88707 and ISL88708, users can adjust the Power-On Reset time-out delay (tPOR) to many times the nominal tPOR of 200ms. To do this, connect a capacitor between CPOR and ground (see Figure 3). For example, connecting a 50pF capacitor to CPOR will increase tPOR from 200ms to ~1.4s. Care should be taken in PCB layout and capacitor placement in order to reduce stray capacitance as much as possible, which contributes to tPOR error. FIGURE 1. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED) VDD MR RST tPOR VTH1 1V tPOR tPOR >tMR tRPD RST PFI VTH 1.25 R1 R2+ R2 --------------------       = (EQ. 1) FIGURE 2. CUSTOM VTH WITH RESISTOR DIVIDER ON PFI VIN R1 R2 PFI ISL8870xFN8092 Rev 6.00 Page 7 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813. Manual Reset The manual-reset input (MR) allows the user to trigger a reset by using a push-button switch. The MR input is an active low debounced input. By connecting a push-button directly from MR to ground, the designer adds manual system reset capability (see Figure 4). Reset is asserted if the MR pin is pulled low to less than 100mV for the minimum MR pulse width or longer while the push-button is closed. After MR is released, the reset outputs remain asserted for tPOR (200ms) and then released. Watchdog Timer The Watchdog Timer circuit checks microprocessor activity by monitoring the WDI input pin. The microprocessor must periodically toggle the WDI pin within tWDT (typically ~1.6s), otherwise the WDO pin pulls low (see Figure 5). The WDO then signals reset periodically (typically ~1.9s) for ~220ms until the WDI is again toggled. Internally, the 1.6s timer is cleared by either a reset or by toggling the WDI input, which can detect pulses longer than 50ns. Whenever there is a low-voltage VDD condition, WDO goes low. Unlike the reset outputs, however, WDO does not have a minimum reset pulse width (tPOR). WDO goes high as soon as VDD rises above its voltage trip point (see Figure 5). With WDI open or connected to a tristated high impedance input, the Watchdog Timer is disabled and only pulls low when VDD < VTH1. ISL88707, ISL88708 FIGURE 3. ADJUSTING tPOR WITH A CAPACITOR CPOR (pF) CPOR 0 2 4 6 8 10 12 14 0 10 20 30 40 50 60 70 80 90 100 NORMALIZED tPOR vs CPOR (pF) OPEN = 200ms MR PB 20k FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON ISL8870xFN8092 Rev 6.00 Page 8 of 16 November 30, 2015

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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813FIGURE 5. WATCHDOG TIMING DIAGRAM VDD WDI WDO VTH1 1V tWDT >tWDPS < tWDT< tWDT < tWDT tPOR tRPD RST tPOR tWDT tPOR Typical Performance Curves FIGURE 6. IDD vs TEMPERATURE FIGURE 7. VTH1 vs TEMPERATURE FOR 5V SUPPLY FIGURE 8. VTH1 vs TEMPERATURE < 5V SUPPLY FIGURE 9. VTHPFI vs TEMPERATURE 6.00 6.50 7.00 7.50 8.00 8.50 9.00 9.50 10.0 10.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 90 TEMPERATURE (°C) I D D ( µ A ) 11.0 VDD = 3.3V VDD = 5V 4.20 4.25 4.30 4.36 4.40 4.45 4.50 4.55 4.60 4.65 -40 -30 -20 -10 0 10 20 30 40 50 60 70 90 TEMPERATURE (°C) V T H 1 (V ) 4.70 VTH = 4.64V VTH = 4.38V -40 -30 -20 -10 0 10 20 30 40 50 60 70 90 TEMPERATURE (°C) V T H 1 (V ) 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 VTH = 2.92V VTH = 3.09V VTH = 2.63V TEMPERATURE (°C) 1.2530 1.2525 1.2520 1.2515 1.2510 1.2505 1.2500 V T H P F I ( V ) -40 -30 -20 -10 0 10 20 30 40 50 60 70 90FN8092 Rev 6.00 Page 9 of 16 November 30, 2015

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