Page 2
FN6612
Rev 0.00
December 21, 2007
ISL9107, ISL9108
1.5A 1.6MHz Low Quiescent Current High Efficiency Synchronous Buck Regulator
DATASHEETISL9107 and ISL9108 are 1.6MHz synchronous step-down
regulators with integrated power switches capable of
delivering 1.5A output current, which is ideal for powering
low-voltage microprocessors in compact devices such as
PDAs and cellular phones. These devices are optimized for
generating low output voltages down to 0.8V. The supply
voltage range is from 2.7V to 5.5V allowing for the use of a
single Li+ cell, three NiMH cells or a regulated 5V input.
1.6MHz pulse-width modulation (PWM) switching frequency
allows using small external components. They have flexible
operation mode selection of forced PWM mode and Skip
(Low IQ) mode with typical 17A quiescent current for
highest light load efficiency to maximize battery life.
The ISL9107 and ISL9108 integrate a pair of low
ON-resistance P-Channel and N-Channel MOSFETs to
maximize efficiency and minimize external component
count.
The ISL9107 offers a typical 215ms Power-Good (PG) timer
when powered up. The timer output can be reset by RSI.
When shutdown, ISL9107 and ISL9108 discharge the output
capacitor. Other features include internal digital soft-start,
enable for power sequence, overcurrent protection, and
thermal shutdown.
The ISL9107 and ISL9108 are offered in 8 Ld 2mmx3mm
DFN package with 0.9mm typical height. The complete
converter can occupy less than 1cm2 area.
Features
• Integrated Synchronous Buck Regulator with up to 95%
Efficiency
• 2.7V to 5.5V Supply Voltage
• 1.5A Guaranteed Output Current
• 17A Quiescent Supply Current in Skip (Low IQ) Mode
• Selectable Forced PWM Mode and Skip Mode
• Less Than 1µA Logic Controlled Shutdown Current
• 100% Maximum Duty Cycle for Lowest Dropout
• Discharge Output Capacitor when Shutdown
• Internal Digital Soft-Start
• Enable, Peak Current Limiting, Short Circuit Protection
• Over-Temperature Protection
• Power-Good Function (for ISL9107 only)
• 8 Ld 2mmx3mm DFN
• Pb-Free (RoHS Compliant)
Applications
• Single Li-Ion Battery-Powered Equipment
• DSP Core Power
• PDAs and Palmtops
Pinouts
ISL9107
(8 LD 2X3 DFN)
TOP VIEW
ISL9108
(8 LD 2X3 DFN)
TOP VIEW
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL9107IRZ-T 107 -40 to +85 8 Ld 2x3 DFN L8.2x3
ISL9108IRZ-T 108 -40 to +85 8 Ld 2x3 DFN L8.2x3
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
2
3
4
1
7
6
5
8VIN
EN
PG
MODE
SW
GND
FB
RSI
SW
GND
FB
NC
VIN
EN
NC
MODE
2
3
4
1
7
6
5
8
FN6612 Rev 0.00 Page 1 of 13
December 21, 2007
Page 3
ISL9107, ISL9108Absolute Maximum Ratings (Reference to GND) Thermal Information
VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
EN, MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PG, RSI (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.5A
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Notes 2, 3) JA (°C/W) JC (°C/W)
2x3 DFN Package . . . . . . . . . . . . . . 78 11
Junction Temperature Range. . . . . . . . . . . . . . . . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. For ISL9107 only.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 2.2µH,
C1 = 10µF, C2 = 10µF, IOUT = 0A (see the Typical Application Circuit on page 7).
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
SUPPLY
Undervoltage Lockout Threshold VUVLO Rising - 2.5 2.7 V
Falling 2.2 2.4 - V
Quiescent Supply Current IVIN MODE = VIN, no load at the output - 17 30 µA
MODE = GND, no load at the output - 5 8 mA
Shut Down Supply Current ISD VIN = 5.5V, EN = LOW - 0.05 2 A
OUTPUT REGULATION
FB Regulation Voltage VFB TA = 0°C to +85°C 0.784 0.8 0.816 V
TA = -40°C to +85°C 0.78 0.8 0.82 V
FB Bias Current IFB VFB = 0.75V - 0.1 - µA
Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) - 0.2 - %/V
COMPENSATION
Error Amplifier Trans-conductance Design info only - 20 - µA/V
SW
P-Channel MOSFET ON-Resistance VIN = 3.6V, IO = 200mA - 0.12 0.22
VIN = 2.7V, IO = 200mA - 0.16 0.27
N-Channel MOSFET ON-Resistance VIN = 3.6V, IO = 200mA - 0.11 0.22
VIN = 2.7V, IO = 200mA - 0.15 0.27
N-Channel Bleeding MOSFET ON-Resistance - 90 -
P-Channel MOSFET Peak Current Limit IPK VIN = 5.5V 1.8 2.1 2.6 A
Maximum Duty Cycle - 100 - %
PWM Switching Frequency fS TA = -40°C to +85°C 1.35 1.6 1.75 MHz
SW Minimum On-Time MODE = LOW (forced PWM mode) - - 100 ns
Soft Start-Up Time - 1.1 - msFN6612 Rev 0.00 Page 2 of 13
December 21, 2007
Page 4
ISL9107, ISL9108PG (NOTE 1)
Output Low Voltage Sinking 1mA, VFB = 0.7V - - 0.3 V
Delay Time 150 215 275 ms
PG Pin Leakage Current PG = VIN = 3.6V - 0.01 0.1 µA
Minimum Supply Voltage for Valid PG Signal 1.2 - - V
Internal PGOOD Low Rising Threshold Percentage of Nominal Regulation Voltage 89.5 92 94.5 %
Internal PGOOD Low Falling Threshold Percentage of Nominal Regulation Voltage 85 88 91 %
Internal PGOOD High Rising Threshold Percentage of Nominal Regulation Voltage 108.2 110.7 113.2 %
Internal PGOOD High Falling Threshold Percentage of Nominal Regulation Voltage 104 107 110 %
Internal PGOOD Delay Time - 50 - µs
RSI (NOTE 1), EN, MODE
Logic Input Low - - 0.4 V
Logic Input High 1.4 - - V
Logic Input Leakage Current Pulled up to 5.5V - 0.1 1 µA
Thermal Shutdown - 150 - °C
Thermal Shutdown Hysteresis - 25 - °C
Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C, VIN = VEN = 3.6V, L = 2.2µH,
C1 = 10µF, C2 = 10µF, IOUT = 0A (see the Typical Application Circuit on page 7). (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Pin Descriptions
PIN #
ISL9107
PIN NAME
ISL9108
PIN NAME DESCRIPTION
1 VIN Input supply voltage pin. Connect a 10µF ceramic capacitor to power ground.
2 EN Enable pin. Enable the output when driven to high. Shut down the chip and discharge output capacitor when
driven to low. Do not leave this pin floating.
4 MODE Mode selection pin. Connect to logic high or VIN to enable skip mode; connect to logic low or ground for force
PWM mode.
6 FB Buck regulator output feedback pin. Connect to the output voltage through voltage divider resistors for
adjustable output voltage.
7 GND System ground.
8 SW Switching node pin. Connect to one terminal of the inductor.
E-PAD - Exposed pad. It should be connected to ground for proper electrical performance. The exposed pad must also
be connected to as much as possible for optimal thermal performance.
3 PG NC For ISL9107, it is 215ms timer output. It outputs 215ms delayed power-good signal when output voltage is
within power-good window. It can be reset by a high RSI signal, then 215ms starts when RSI goes from high
to low.
For ISL9108, do not connect. Leave this pin floating.
5 RSI NC For ISL9107, this input resets the 215ms timer. Please refer to “Theory of Operation” on page 9 for more
details.
For ISL9108, do not connect. Leave this pin floating.FN6612 Rev 0.00 Page 3 of 13
December 21, 2007
Page 5
ISL9107, ISL9108Typical Operating Performance
FIGURE 1. EFFICIENY vs LOAD CURRENT (VOUT = 3.3V) FIGURE 2. EFFICIENCY vs LOAD CURRENT (VOUT = 2.5V)
FIGURE 3. EFFICIENCY vs LOAD CURRENT (VOUT = 1.6V) FIGURE 4. IQ vs VIN (MODE = VIN, VOUT = 1.6V, IOUT = 0)
FIGURE 5. IQ vs VIN (MODE = GND, VOUT = 1.6V, IOUT = 0)
50
55
60
65
70
75
80
85
90
95
100
0 500 1000 1500
LOAD CURRENT (mA)
E
F
F
IC
IE
N
C
Y
(
%
) VIN = 3.6V VIN = 4.2V
0 500 1000 1500
50
55
60
65
70
75
80
85
90
95
100
LOAD CURRENT (mA)
E
F
F
IC
IE
N
C
Y
(
%
)
VIN = 4.2V
VIN = 3.6V
50
55
60
65
70
75
80
85
90
95
100
0 500 1000 1500
LOAD CURRENT (mA)
E
F
F
IC
IE
N
C
Y
(
%
)
EFFICIENCY @ 2.7V
EFFICIENCY @ 3.6V
EFFICIENCY @ 4.2V
0
5
10
15
20
25
30
2.7 3.4 4.1 4.8 5.5
INPUT VOLTAGE (V)
Q
U
IE
S
C
E
N
T
C
U
R
R
E
N
T
(
µ
A
)
0
1
2
3
4
5
6
7
8
2.7 3.4 4.1 4.8 5.5
INPUT VOLTAGE (V)
Q
U
IE
S
C
E
N
T
C
U
R
R
E
N
T
(
m
A
)
FN6612 Rev 0.00 Page 4 of 13
December 21, 2007
Page 6
ISL9107, ISL9108FIGURE 6. SOFT-START (VIN = 4.2V, VOUT = 1.6V,
IOUT = 1.5A)
FIGURE 7. SOFT-START (VIN = 4.2V, VOUT = 1.6V,
IOUT = 1mA)
FIGURE 8. STEADY-STATE IN SKIP MODE (VIN = 5.0V,
VOUT = 1.6V, IOUT = 35mA)
FIGURE 9. STEADY-STATE IN PWM MODE (VIN = 5.0V,
VOUT = 1.6V, IOUT = 1.5A)
FIGURE 10. LOAD TRANSIENT TEST (MODE = VIN = 5.0V;
VO = 1.6V; IO = 0.01A~1A)
FIGURE 11. LOAD TRANSIENT TEST (MODE = GND,
VIN = 5.0V; VO = 1.6V; IO = 0.01A~1A)
Typical Operating Performance (Continued)
5V/DIV
1V/DIV
5V/DIV
1A/DIV
200µs/DIV
VSW
VOUT
IL
EN
200µs/DIV
5V/DIV
1V/DIV
5V/DIV
500mA/DIV
VSW
VOUT
IL
EN
2µs/DIV
200mA/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
50mV/DIV
IL
1µs/DIV
1A/DIV
20mV/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
IL
100µs/DIV
1A/DIV
100mV/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
IL
100µs/DIV
1A/DIV
100mV/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
IL
VSWFN6612 Rev 0.00 Page 5 of 13
December 21, 2007
Page 7
ISL9107, ISL9108FIGURE 12. LOAD TRANSIENT TEST (MODE = VIN = 4.2V;
VO = 1.6V; IO = 0.01A~1A)
FIGURE 13. LOAD TRANSIENT TEST (MODE = GND,
VIN = 4.2V; VO = 1.6V; IO = 0.01A~1A)
FIGURE 14. LOAD TRANSIENT TEST (MODE = VIN = 3.6V;
VO = 1.6V; IO = 0.01A~1A)
FIGURE 15. LOAD TRANSIENT TEST (MODE = GND,
VIN = 3.6V; VO = 1.6V; IO = 0.01A~1A)
Typical Operating Performance (Continued)
100µs/DIV
1A/DIV
100mV/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
IL
100µs/DIV
1A/DIV
100mV/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
IL
100µs/DIV
1A/DIV
100mV/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
IL
100µs/DIV
1A/DIV
100mV/DIV
5V/DIV
VOUT (AC COUPLED)
VSW
ILFN6612 Rev 0.00 Page 6 of 13
December 21, 2007
Page 8
ISL9107, ISL9108Typical Applications
FIGURE 16. TYPICAL APPLICATION DIAGRAM FOR ISL9107 AND ISL9108
PARTS DESCRIPTION MANUFACTURERS PART NUMBER SPECIFICATIONS SIZE
L Inductor Sumida CDRH4D15/SNP-2R2NC 2.2µH/2.0A/48m 4.4mmx4.4mmx1.7mm
C1 Input capacitor Murata GRM21BR60J106KE19L 10µF/6.3V 2.0mmx1.25mmx1.25mm
C2 Output capacitor Murata GRM21BR60J106KE19L 10µF/6.3V 2.0mmx1.25mmx1.25mm
C3 Capacitor Murata GRM188R71H221KA01C 220pF/50V 1.6mmx0.8mmx0.8mm
R1(ISL9107) Resistor Various 100k SMD, 1.6mmx0.8mmx0.45mm
R2, R3 Resistor Various 100k SMD, 1.6mmx0.8mmx0.45mm
ISL9107
SW
GND
FB
RSI
VIN
EN
PG
MODE
INPUT
OUTPUT
1.6V/0A~1.5A
R1
100k
R2
100k
R3
100k
2.7V TO 5.5V
E-PAD
C2
10µF
L
2.2µH
C3
220pF
C1
10µF
ISL9108
SW
GND
FB
NC
VIN
EN
MODE
NC
INPUT
OUTPUT
1.6V/0A~1.5A
R2
100k
R3
100k
2.7V TO 5.5V
E-PAD
C2
10µF
L
2.2µH
C3
220pF
C1
10µFFN6612 Rev 0.00 Page 7 of 13
December 21, 2007
Page 9
ISL9107, ISL9108Block Diagram
FIGURE 17. FUNCTIONAL BLOCK DIAGRAM
*Note: Only applies to ISL9107.
SW
+
CSA
+
+
OCP
VREF1
SKIP
+
+
SOFT-
START
0.8V
EAMP
COMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
FB
+
PG*
MODE
SHUTDOWN
VIN
GND
+
BANDGAP
SCP
+
EN
SHUTDOWN
RSI*
VREF2
VREF3
VREF4
VREF5
ZERO-CROSS
SENSING
SLOPE
COMP
PGOOD
DELAY
OSCILLATOR
+
*NoteFN6612 Rev 0.00 Page 8 of 13
December 21, 2007
Page 10
ISL9107, ISL9108Theory of Operation
The ISL9107 and ISL9108 are step-down switching regulators
optimized for battery-powered handheld applications. The
regulators operate at typical 1.6MHz fixed switching frequency
under heavy load condition to allow small external inductor and
capacitors to be used for minimal printed-circuit board (PCB)
area. At light load, the regulators can be selected to enter skip
mode to reduce the switching frequency, unless forced to the
fixed frequency, to minimize the switching loss and to
maximize the battery life. The quiescent current under skip
mode with no loading is typically only 17µA. The supply current
is typically only 0.1µA when the regulator is disabled.
PWM Control Scheme
These devices use the peak-current-mode pulse-width
modulation (PWM) control scheme for fast transient response
and pulse-by-pulse current limiting. Figure 17 shows the circuit
functional block diagram. The current loop consists of the
oscillator, the PWM comparator COMP, current sensing circuit
and the slope compensation for the current loop stability. The
current sensing circuit consists of the resistance of the P-
Channel MOSFET when it is turned on and the Current Sense
Amplifier (CSA). The control reference for the current loops
comes from the Error Amplifier (EAMP) of the voltage loop.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA output
and the compensation slope reaches the control reference of
the current loop, the PWM comparator COMP sends a signal
to the PWM logic to turn off the P-Channel MOSFET and to
turn on the N-Channel MOSFET. The N-MOSFET remains on till
the end of the PWM cycle. Figure 18 shows the typical operating
waveforms during the normal PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the CSA
output.
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a 0.8V
reference voltage to the voltage control loop. The feedback
signal comes from the FB pin. The soft-start block only affects
the operation during the start-up and will be discussed
separately in “Soft Start-Up” on page 10. The EAMP is a
transconductance amplifier, which converts the voltage error
signal to a current output. The voltage loop is internally
compensated by a RC network. The maximum EAMP voltage
output is precisely clamped to the bandgap voltage.
Skip Mode
With the MODE pin connected to logic high, the device enters
a pulse-skipping mode at light load to minimize the switching
loss by reducing the switching frequency. Figure 19 illustrates
the skip mode operation. A zero-cross sensing circuit (as
shown in Figure 17) monitors the N-Channel MOSFET current
for zero crossing. When it is detected to cross zero for 8
consecutive cycles, the regulator enters the skip mode. During
the 8 consecutive cycles, the inductor current could be
negative. The counter is reset to zero when the sensed N-
Channel MOSFET current does not cross zero during any
cycle within the 8 consecutive cycles. Once the device enters
the skip mode, the pulse modulation starts being controlled by
the SKIP comparator shown in Figure 17. Each pulse cycle is
still synchronized by the PWM clock. The P-Channel MOSFET
is turned on at the rising edge of clock and turned off when its
current reaches 20% of the peak current limit. As the average
inductor current in each cycle is higher than the average
current of the load, the output voltage rises cycle over cycle.
When the output voltage reaches 1.5% above it’s nominal
voltage, the P-Channel MOSFET is turned off immediately and
the inductor current is fully discharged to zero and stays at
zero. The output voltage reduces gradually due to the load
current discharging the output capacitor. When the output
voltage drops to the nominal voltage, the P-Channel MOSFET
will be turned on again, repeating the previous operations.
The regulator resumes normal PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value.
Enable
The enable (EN) pin allows the user to enable or disable the
converter for purposes such as power-up sequencing. With the
EN pin pulled to high, the converter is enabled, the internal
reference circuit wakes up first and then the soft start-up
begins. When the EN pin is pulled to logic low, the converter is
disabled, the P-Channel MOSFET is turned off immediately
and the output capacitor is discharged through internal
discharge path.
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the device is disabled.
FIGURE 18. PWM OPERATION WAVEFORMS
vEAMP
d
iL
vOUT
vCSA FN6612 Rev 0.00 Page 9 of 13
December 21, 2007
