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L6563H

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L6563H

For Reference Only

Part Number L6563H
Manufacturer STMicroelectronics
Description IC PFC CTRLR TRANSITION 16SOIC
Datasheet L6563H Datasheet
Package 16-SOIC (0.154", 3.90mm Width)
In Stock 9,590 piece(s)
Unit Price $ 1.4600 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jan 21 - Jan 26 (Choose Expedited Shipping)
Request for Quotation

Part Number # L6563H (PMIC - PFC (Power Factor Correction)) is manufactured by STMicroelectronics and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For L6563H specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add L6563H with quantity into BOM. Heisener.com does NOT require any registration to request a quote of L6563H.

L6563H Specifications

ManufacturerSTMicroelectronics
CategoryIntegrated Circuits (ICs) - PMIC - PFC (Power Factor Correction)
Datasheet L6563HDatasheet
Package16-SOIC (0.154", 3.90mm Width)
Series-
ModeDiscontinuous (Transition)
Frequency - Switching-
Current - Startup90µA
Voltage - Supply10.3 V ~ 22.5 V
Operating Temperature-40°C ~ 150°C
Mounting TypeSurface Mount
Package / Case16-SOIC (0.154", 3.90mm Width)
Supplier Device Package16-SO

L6563H Datasheet

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This is information on a product in full production. June 2017 DocID16047 Rev 4 1/50 L6563H High voltage start-up transition-mode PFC Datasheet - production data Features  On-board 700 V start-up source  Tracking boost function  Fast “bidirectional” input voltage feedforward (1/V2 correction)  Interface for cascaded converter's PWM controller  Remote ON/OFF control  Accurate adjustable output overvoltage protection  Protection against feedback loop disconnection (latched shutdown)  Inductor saturation protection  Low (100 µA) start-up current  6 mA max. operating bias current  1% (at TJ = 25 °C) internal reference voltage  -600/+800 mA totem pole gate driver with active pull-down during UVLO Applications  PFC pre-regulators for: – Hi-end AC-DC adapter/charger – IEC61000-3-2 or JEITA-MITI compliant SMPS, in excess of 400 W  SMPS for LED luminaires Figure 1. Block diagram SO-16 SO16 www.st.com

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Contents L6563H 2/50 DocID16047 Rev 4 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 Tracking boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.7 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . 33 6.8 High voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1 SO16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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DocID16047 Rev 4 3/50 L6563H List of tables 50 List of tables Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Summary of L6563H idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6. SO16 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 7. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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List of figures L6563H 4/50 DocID16047 Rev 4 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. IC consumption vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. IC consumption vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. VCC Zener voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Start-up and UVLO vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Feedback reference vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. E/A output clamp levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. UVLO saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11. OVP levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12. Inductor saturation threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13. Vcs clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. ZCD sink/source capability vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 15. ZCD clamp level vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 16. TBO clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 17. VVFF - VTBO dropout vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 18. IINV - ITBO current mismatch vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 19. IINV - ITBO mismatch vs. ITBO current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 20. R discharge vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21. Line drop detection threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 22. VMULTpk - VVFF dropout vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 23. PFC_OK threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 24. PFC_OK FFD threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25. PWM_LATCH high saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 26. RUN threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 27. PWM_STOP low saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 28. Multiplier characteristics at VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 29. Multiplier characteristics at VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 30. Multiplier gain vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 31. Gate drive clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 32. Gate drive output saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 33. Delay to output vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 34. Start-up timer period vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 35. HV start voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 36. VCC restart voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 37. HV breakdown voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 38. Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 24 Figure 39. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic . . . 26 Figure 40. RFF · CFF as a function of 3 rd harmonic distortion introduced in the input current . . . . . . . 27 Figure 41. THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 42. THD optimization: standard TM PFC controller (left side) and L6563H (right side) . . . . . . 29 Figure 43. Tracking boost block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 44. Tracking output voltage vs. input voltage characteristic with TBO . . . . . . . . . . . . . . . . . . . 32 Figure 45. Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 32 Figure 46. Interface circuits that let dc-dc converter's controller IC drive L6563H in burst mode . . . . 33 Figure 47. Interface circuits that let the L6563H switch on or off a PWM controller. . . . . . . . . . . . . . . 34 Figure 48. Interface circuits for power up sequencing when dc-dc has the SS function . . . . . . . . . . . 34

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DocID16047 Rev 4 5/50 L6563H List of figures 50 Figure 49. Interface circuits for actual power-up sequencing (master PFC) . . . . . . . . . . . . . . . . . . . . 34 Figure 50. Brownout protection (master PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 51. High voltage start-up generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 52. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 36 Figure 53. High voltage start-up behavior during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 54. High voltage start-up managing the dc-dc output short-circuit . . . . . . . . . . . . . . . . . . . . . . 38 Figure 55. Demonstration board EVL6563H-100W, wide-range mains: electrical schematic . . . . . . . 39 Figure 56. L6563H 100 W TM PFC evaluation board: compliance to EN61000-3-2 standard . . . . . . 40 Figure 57. L6563H 100 W TM PFC evaluation board: compliance to JEITA-MITI standard . . . . . . . . 40 Figure 58. L6563H 100 W TM PFC evaluation board: input current waveform at 230-50 Hz - 100 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 59. L6563H 100W TM PFC evaluation board: input current waveform at 100 V-50 Hz - 100 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 60. 90 W adapter with L6563H, L6599A, SRK2000A demonstration board: electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 61. 150 W - 12 V adapter with L6563H, L6599A, SRK2000A: electrical schematic . . . . . . . . . 42 Figure 62. EVL6563H -250 W TM PFC demonstration board: electrical schematic . . . . . . . . . . . . . . 43 Figure 63. EVL6599A-90WADP 90 W adapter demonstration board: electrical schematic. . . . . . . . . 44 Figure 64. SO16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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Description L6563H 6/50 DocID16047 Rev 4 1 Description The L6563H is a current-mode PFC controller operating in transition mode (TM) which embeds the same features existing in the L6563S with the addition of a high voltage start-up source. These functions make the IC especially suitable for applications that have to be compliant with energy saving regulations and where the PFC pre-regulator works as the master stage. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% at Tj = 25 °C) internal voltage reference. Loop's stability is optimized by the voltage feedforward function (1/V2 correction), which in this IC uses a proprietary technique that considerably improves line transient response as well in case of mains both drops and surges (“bidirectional”). Additionally, the IC provides the option for tracking boost operation, i.e. the output voltage is changed tracking the mains voltage. The device includes disable functions suitable for remote ON/OFF control too. In addition to an over voltage protection able to keep the output voltage under control during transient conditions, the IC is provided also with a protection against feedback loop failures or erroneous settings. Other on-board protection functions allow that brownout conditions and boost inductor saturation can be safely handled. An interface with the PWM controller of the DC-DC converter supplied by the PFC pre- regulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation, etc.) and to handle the PFC stage in case of light load for the DC-DC converter, to make it easier to comply with energy saving regulations (Blue Angel, EnergyStar, Energy2000, etc.). The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOSFET or IGBT drive. This, combined with the other features and the possibility to operate with ST's proprietary fixed-off-time control, makes the device an excellent solution for SMPS up to 400 W that need to be compliant with EN61000-3-2 and JEITA-MITI standards.

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DocID16047 Rev 4 7/50 L6563H Maximum ratings 50 2 Maximum ratings 2.1 Absolute maximum ratings 2.2 Thermal data Table 1. Absolute maximum ratings Symbol Pin Parameter Value Unit VHVS 9 Voltage range (referred to ground) -0.3 to 700 V IHVS 9 Output current Self-limited IHVS Vcc 16 IC supply voltage (Icc = 20 mA) Self-limited V - 1, 3, 7 Max. pin voltage (Ipin =1 mA) Self-limited V - 2, 4 to 6, 8, 11, 12 Analog inputs and outputs -0.3 to 8 V IPWM_STOP 11 Max. sink current 3 mA IZCD 13 Zero current detector max. current -10 (source) 10 (sink) mA Table 2. Thermal data Symbol Parameter Value Unit RthJA Max. thermal resistance, junction to ambient 120 °C/W Ptot Power dissipation at TA = 50 °C 0.75 W TJ Junction temperature operating range -40 to 150 °C Tstg Storage temperature -55 to 150 °C

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Pin connection L6563H 8/50 DocID16047 Rev 4 3 Pin connection Figure 2. Pin connection Table 3. Pin description No. Name Function 1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre- regulator is fed into the pin through a resistor divider. The pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by TBO (pin 6) is activated. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. 2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 V the gate driver output is inhibited (burst-mode operation). 3 MULT Mains input to the multiplier. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used also to derive the information on the RMS mains voltage. 4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. 5 VFF Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be connected from the pin to GND. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. The voltage at this pin, a dc level equal to the peak voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage. Never connect the pin directly to GND but with a resistor ranging from 100 k (minimum) to 2 M  (maximum). 6 TBO Tracking boost function. This pin provides a buffered VFF voltage. A resistor connected between this pin and GND defines a current that is sunk from pin INV (1). In this way, the output voltage is changed proportionally to the mains voltage (tracking boost). If this function is not used leave this pin open.

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DocID16047 Rev 4 9/50 L6563H Pin connection 50 7 PFC_OK PFC pre-regulator output voltage monitoring/disable function. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66V, a feedback failure is assumed. In this case the device is latched off and the PWM_LATCH (8) pin is asserted high. Normal operation can be resumed only by cycling Vcc bringing its value lower than 6V before to move up to Turn on threshold. If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input. 8 PWM_LATCH Output pin for fault signaling. During normal operation this pin features high impedance. If a feedback failure is detected (PFC_OK > 2.5 V and INV < 1.66 V) the pin is asserted high. Normally, this pin is used to stop the operation of the dc-dc converter supplied by the PFC pre- regulator by invoking a latched disable of its PWM controller. If not used, the pin is left floating. 9 HVS High voltage start-up. The pin, able to withstand 700 V, is to be tied directly to the rectified mains voltage. A 1 mA internal current source charges the capacitor connected between pin Vcc (16) and pin GND (14) until the voltage on the pin Vcc reaches the start-up threshold, then it is shut down. Normally, the generator is re-enabled when the Vcc voltage falls below 6 V to ensure a low power throughput during short-circuit. Otherwise, when a latched protection is tripped the generator is re-enabled as Vcc reaches the UVLO threshold to keep the latch supplied. 10 N.C. Not internally connected. Provision for clearance on the PCB to meet safety requirements. 11 PWM_STOP Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.8 V on pin RUN (12) the voltage on the pin is pulled to ground. Normally, this pin is used to temporarily stop the operation of the dc-dc converter supplied by the PFC pre-regulator by disabling its PWM controller. A typical usage of this function is brownout protection in systems where the PFC pre-regulator is the master stage. If not used, the pin is left floating. 12 RUN Remote ON/OFF control. A voltage below 0.8 V shuts down (not latched) the IC and brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC restarts as the voltage at the pin goes above 0.88V. Connect this pin to pin VFF (5) either directly or through a resistor divider to use this function as brownout (AC mains undervoltage) protection. 13 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative- going edge triggers MOSFET’s turn-on. 14 GND Ground. Current return for both the signal part of the IC and the gate driver. 15 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages. 16 Vcc Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. Table 3. Pin description (continued) No. Name Function

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Hall*****amesh

December 24, 2020

There are cheaper ones out there but this one really take the guessing game out.

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December 23, 2020

Happy with purchase, would do business again

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L6563H

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

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