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Part Number LCMXO2280E-4TN100C
Manufacturer Lattice Semiconductor Corporation
Description IC FPGA 73 I/O 100TQFP
Datasheet LCMXO2280E-4TN100C Datasheet
Package 100-LQFP
In Stock 3,760 piece(s)
Unit Price $ 20.8061 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 8 - Jun 13 (Choose Expedited Shipping)
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LCMXO2280E-4TN100C Specifications

ManufacturerLattice Semiconductor Corporation
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet LCMXO2280E-4TN100CDatasheet
Number of LABs/CLBs285
Number of Logic Elements/Cells2280
Total RAM Bits28262
Number of I/O73
Number of Gates-
Voltage - Supply1.14 V ~ 1.26 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 85°C (TJ)
Package / Case100-LQFP
Supplier Device Package100-TQFP (14x14)

LCMXO2280E-4TN100C Datasheet

Page 1

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MachXO Family Data Sheet DS1002 Version 03.0, June 2013

Page 3

June 2013 Data Sheet DS1002 © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 1-1 DS1002 Introduction_01.5 Features  Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to  intercept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volatile memory programmable through JTAG port • Supports background programming of  non-volatile memory  Sleep Mode • Allows up to 100x static current reduction  TransFR™ Reconfiguration (TFR) • In-field logic update while system operates  High I/O to Logic Density • 256 to 2280 LUT4s • 73 to 271 I/Os with extensive package options • Density migration supported • Lead free/RoHS compliant packaging  Embedded and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Up to 7.7 Kbits distributed RAM • Dedicated FIFO control logic  Flexible I/O Buffer • Programmable sysIO™ buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2  LVTTL  PCI  LVDS, Bus-LVDS, LVPECL, RSDS  sysCLOCK™ PLLs • Up to two analog PLLs per device • Clock multiply, divide, and phase shifting  System Level Support • IEEE Standard 1149.1 Boundary Scan • Onboard oscillator • Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply • IEEE 1532 compliant in-system programming Introduction The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfac- ing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. Table 1-1. MachXO Family Selection Guide Device LCMXO256 LCMXO640 LCMXO1200 LCMXO2280 LUTs 256 640 1200 2280 Dist. RAM (Kbits) 2.0 6.1 6.4 7.7 EBR SRAM (Kbits) 0 0 9.2 27.6 Number of EBR SRAM Blocks (9 Kbits) 0 0 1 3 VCC Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V Number of PLLs 0 0 1 2 Max. I/O 78 159 211 271 Packages 100-pin TQFP (14x14 mm) 78 74 73 73 144-pin TQFP (20x20 mm) 113 113 113 100-ball csBGA (8x8 mm) 78 74 132-ball csBGA (8x8 mm) 101 101 101 256-ball caBGA (14x14 mm) 159 211 211 256-ball ftBGA (17x17 mm) 159 211 211 324-ball ftBGA (19x19 mm) 271 MachXO Family Data Sheet Introduction

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Introduction MachXO Family Data Sheet 1-2 The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex- ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high- security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification.

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June 2013 Data Sheet DS1002 © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2-1 DS1002 Architecture_01.5 Architecture Overview The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Figures 2-1, 2-2, and 2-3 show the block diagrams of the various family members. The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter- face standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func- tions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in a two-dimensional array. Only one type of block is used per row. In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on dif- ferent Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast mem- ory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT use. The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration set- ting, allowing device entering to a known state for predictable system function. The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices. These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing easy integration into the overall system. MachXO Family Data Sheet Architecture

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2-2 Architecture MachXO Family Data Sheet Figure 2-1. Top View of the MachXO1200 Device1 1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks. Figure 2-2. Top View of the MachXO640 Device JTAG Port Programmable Functional Units without RAM (PFFs) Programmable Functional Units with RAM (PFUs) PIOs Arranged into sysIO Banks sysMEM Embedded Block RAM (EBR) sysCLOCK PLL JTAG Port PIOs Arranged into sysIO Banks Programmable Function Units with RAM (PFUs) Programmable Function Units without RAM (PFFs)

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2-3 Architecture MachXO Family Data Sheet Figure 2-3. Top View of the MachXO256 Device PFU Blocks The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-4. PFU Diagram Slice Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice. The registers in the Slice can be configured for positive/negative and edge/level clocks. JTAG Port Programmable Function Units with RAM (PFUs) Programmable Function Units without RAM (PFFs) PIOs Arranged into sysIO Banks Slice 0 LUT4 & CARRY LUT4 & CARRY FF/ Latch FCIN FCO D FF/ Latch D Slice 1 LUT4 & CARRY LUT4 & CARRY Slice 2 LUT4 & CARRY LUT4 & CARRY From Routing To Routing Slice 3 LUT4 & CARRY LUT4 & CARRY FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D

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2-4 Architecture MachXO Family Data Sheet There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the sig- nals associated with each Slice. Figure 2-5. Slice Diagram Table 2-1. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0/M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCIN Fast Carry In1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register Outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the Slice Output Inter-PFU signal FCO Fast Carry Out1 1. See Figure 2-4 for connection details. 2. Requires two PFUs. LUT4 & CARRY LUT4 & CARRY Slice A0 B0 C0 D0 FF/ Latch OFX0 F0 Q0 A1 B1 C1 D1 CI CI CO CO F SUM CE CLK LSR FF/ Latch OFX1 F1 Q1 Fast Connection to I/O Cell* F SUM D D M1 From Adjacent Slice/PFU To Adjacent Slice/PFU Fast Connection to I/O Cell* LUT Expansion Mux M0 OFX0 From Routing To Routing Control Signals selected and inverted per Slice in routing Notes: Some inter-Slice signals are not shown. * Only PFUs at the edges have fast connections to the I/O cell.

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2-5 Architecture MachXO Family Data Sheet Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables (LUT4). A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by program- ming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol- lowing functions can be implemented by each Slice: • Addition 2-bit • Subtraction 2-bit • Add/Subtract 2-bit using dynamic control • Up counter 2-bit • Down counter 2-bit • Ripple mode multiplier building block • Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice functions as the read-write port, while the other companion Slice supports the read-only port. For more information on RAM mode in MachXO devices, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM Logic Ripple RAM ROM PFU Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit SP 16x2 ROM 16x1 x 2 PFF Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit N/A ROM 16x1 x 2 SPR16x2 DPR16x2 Number of Slices 1 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM

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2-6 Architecture MachXO Family Data Sheet Figure 2-6. Distributed Memory Primitives ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation Routing There are many resources provided in the MachXO devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec- tions in the horizontal and vertical directions. Logic Ripple RAM ROM LUT 4x8 or MUX 2x1 x 8 2-bit Add x 4 SPR16x2 x 4 DPR16x2 x 2 ROM16x1 x 8 LUT 5x4 or MUX 4x1 x 4 2-bit Sub x 4 SPR16x4 x 2 DPR16x4 x 1 ROM16x2 x 4 LUT 6x 2 or MUX 8x1 x 2 2-bit Counter x 4 SPR16x8 x 1 ROM16x4 x 2 LUT 7x1 or MUX 16x1 x 1 2-bit Comp x 4 ROM16x8 x 1 DO1 DO0 DI0 DI1 AD0 AD1 AD2 AD3 WRE CK DO0 AD0 AD1 AD2 AD3 DPR16x2SPR16x2 ROM16x1 RDO1 RDO0DI0 DI1 WCK WRE WDO1 WDO0 WAD0 WAD1 WAD2 WAD3 RAD0 RAD1 RAD2 RAD3

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