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MAX1858EEG+

hot MAX1858EEG+

MAX1858EEG+

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Part Number MAX1858EEG+
Manufacturer Maxim Integrated
Description IC REG CTRLR BUCK 24QSOP
Datasheet MAX1858EEG+ Datasheet
Package 24-SSOP (0.154", 3.90mm Width)
In Stock 2104 piece(s)
Unit Price $ 8.48 *
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MAX1858EEG+ Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - DC DC Switching Controllers
Datasheet MAX1858EEG+ Datasheet
Package24-SSOP (0.154", 3.90mm Width)
Series-
Output TypeTransistor Driver
FunctionStep-Down
Output ConfigurationPositive
TopologyBuck
Number of Outputs2
Output Phases2
Voltage - Supply (Vcc/Vdd)4.75 V ~ 23 V
Frequency - Switching100kHz ~ 600kHz
Synchronous RectifierYes
Clock SyncYes
Control FeaturesCurrent Limit, Enable, Frequency Control, Reset
Operating Temperature-40°C ~ 85°C (TA)
Package / Case24-SSOP (0.154", 3.90mm Width)
Supplier Device Package24-QSOP

MAX1858EEG+ Datasheet

Page 1

Page 2

General Description The MAX1858 dual, synchronized, step-down controller generates two outputs from input supplies ranging from 4.75V to 23V. Each output is adjustable from sub-1V to 18V and supports loads of 10A or higher. Input voltage ripple and total RMS input ripple current are reduced by synchronized 180° out-of-phase operation. The switching frequency is adjustable from 100kHz to 600kHz with an external resistor. Alternatively, the con- troller can be synchronized to an external clock gener- ated to another MAX1858 or a system clock. One MAX1858 can be set to generate an in-phase, or 90° out-of-phase, clock signal for synchronization with addi- tional controllers. This allows two controllers to operate either as an interleaved two- or four-phase system with each output shifted by 90°. The device also features “first-on/last-off” power sequencing for compatibility with DSPs, ASICs, and FPGAs, as well as soft-start and soft-stop to ensure reliable and repeatable power sequencing. The MAX1858 eliminates the need for current-sense resistors by utilizing the low-side MOSFET’s on-resistance as a current-sense element. This protects the DC-DC components from damage during output-overload condi- tions or when output short-circuit faults without requiring a current-sense resistor. Adjustable foldback current limit reduces power dissipation during short-circuit condition. A power-on reset output signals the system when both outputs reach regulation. The MAX1858 is available in a 24-pin QSOP package. An evaluation kit is available to speed designs. Applications Network Power Supplies Telecom Power Supplies DSP, ASIC, and FPGA Power Supplies Set-Top Boxes Broadband Routers Servers Features  Two Independent Output Voltages  180° Out-of-Phase Operation  90° Out-of-Phase Operation (Using Two MAX1858s)  Foldback Current Limit  4.75V to 23V Input Supply Range  0 to 18V Output-Voltage Range (Up to 10A)  >90% Efficiency  Fixed-Frequency Pulse-Width Modulation (PWM) Operation  Adjustable 100kHz to 600kHz Switching Frequency  External SYNC Input  Clock Output for Master/Slave Synchronization  Power-On/-Off Sequencing with Soft-Start and Soft-Stop  RST Output with 140ms Minimum Delay  Lossless Current Limit (No Sense Resistor) M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR ________________________________________________________________ Maxim Integrated Products 1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 EN LX2 DH2 BST2OSC ILIM2 FB2 COMP2 TOP VIEW DL2 VL PGND DL1CKO GND REF V+ 16 15 14 13 9 10 11 12 BST1 DH1 LX1 COMP1 FB1 ILIM1 SYNC QSOP MAX1858 RST Pin Configuration Ordering Information 19-2432; Rev 0; 7/02 EVALU ATION KIT M ANUAL AVAIL ABLE For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE MAX1858EEG -40°C to +85°C 24 QSOP Typical Operating Circuit appears at end of data sheet.

Page 3

M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V+ to GND..............................................................-0.3V to +25V PGND to GND .......................................................-0.3V to +0.3V VL to GND ..................-0.3V to the lower of +6V and (V+ + 0.3V) BST1, BST2 to GND ...............................................-0.3V to +30V LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) DL1, DL2 to PGND........................................-0.3V to (VL + 0.3V) CKO, REF, OSC, ILIM1, ILIM2, COMP1, COMP2 to GND ..........................-0.3V to (VL + 0.3V) FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V VL to GND Short Circuit..............................................Continuous REF to GND Short Circuit ...........................................Continuous Continuous Power Dissipation (TA = +70°C) 24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C ELECTRICAL CHARACTERISTICS (V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 60kΩ, compensation components for COMP_ are from Figure 1, TA = -40°C to +85°C (Note 1), unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS GENERAL (Note 2) 4.75 23 V+ Operating Range VL = V+ (Note 2) 4.75 5.5 V V+ Operating Supply Current VL unloaded, no MOSFETs connected 3.5 6 mA V+ Standby Supply Current EN = LX_ = FB_ = 0V ROSC = 60kΩ 0.3 0.6 mA Thermal Shutdown Rising temperature, typical hysteresis = 10°C 160 °C ILIM_ = VL 75 100 125 RILIM_ = 100kΩ 32 50 62 Current-Limit Threshold PGND - LX_ RILIM_ = 600kΩ 225 300 375 mV VL REGULATOR Output Voltage 5.5V < V+ < 23V, 1mA < ILOAD < 50mA 4.75 5 5.25 V VL Undervoltage Lockout Trip Level 4.4 4.55 4.7 V REFERENCE Output Voltage IREF = 0µA 1.98 2.00 2.02 V Reference Load Regulation 0µA < IREF < 50µA 0 4 10 mV SOFT-START Digital Ramp Period Internal 6-bit DAC for one converter to ramp from 0V to full scale (Note 3) 1024 DC-DC Clocks Soft-Start Steps 64 Steps FREQUENCY 0°C to +85°C 84 100 115 Low End of Range ROSC = 60kΩ -40°C to +85°C 80 100 120 kHz High End of Range ROSC = 10kΩ 540 600 660 kHz DH_ Minimum Off-Time ROSC = 10kΩ 250 303 ns

Page 4

M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 60kΩ, compensation components for COMP_ are from Figure 1, TA = -40°C to +85°C (Note 1), unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS SYNC Range Internal oscillator nominal frequency must be set to half of SYNC frequency 200 1200 kHz High 100 SYNC Input Pulse Width (Note 3) Low 100 ns SYNC Rise/Fall Time (Note 3) 100 ns ERROR AMPLIFIER FB_ Input Bias Current 250 nA 0°C to +85°C 0.985 1.00 1.015 FB_ Input Voltage Set Point -40°C to +85°C 0.98 1.00 1.02 V 0°C to +85°C 1.25 1.8 2.70 FB_ to COMP_ Transconductance -40°C to +85°C 1.2 1.8 2.9 mS DRIVERS D L_, D H_ Break-Before-Make Time CLOAD = 5nF 30 ns Low 1.5 2.5 DH_ On-Resistance High 3 5 Ω Low 0.6 1.5 DL_ On-Resistance High 3 5 Ω LOGIC INPUTS (EN, SYNC) Input Low Level Typical 15% hysteresis, VL = 4.75V 0.8 V Input High Level VL = 5.5V 2.4 V Input High/Low Bias Current VEN = 0 or 5.5V -1 0.1 +1 µA LOGIC OUTPUTS (CKO) Output Low Level VL = 5V, sinking 5mA 0.4 V Output High Level VL = 5V, sourcing 5mA 4.0 V COMP_ Pulldown Resistance During Shutdown and Current Limit 17 Ω RST OUTPUT Output-Voltage Trip Level Both FBs must be over this to allow the reset timer to start; there is no hysteresis 0.87 0.9 0.93 V VL = 5V, sinking 3.2mA 0.4 Output Low Level VL = 1V, sinking 0.4mA 0.3 V Output Leakage V+ = VL = 5V, V RST = 5.5V, VFB = 1V 1 µA Reset Timeout Period VFB_=1V 140 315 560 ms FB_ to Reset Delay FB_ overdrive from 1V to 0.85V 4 µs Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: Operating supply range is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation. Note 3: Guaranteed by design and not production tested.

Page 5

M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR 4 _______________________________________________________________________________________ Typical Operating Characteristics (Circuit of Figure 1, VIN = 12V, TA = +25°C, unless otherwise noted.) EFFICIENCY vs. LOAD M A X 1 8 5 8 t o c0 1 LOAD (A) EF FI C IE N C Y ( % ) 101 10 20 30 40 50 60 70 80 90 100 0 0.1 100 OUT2 OUT1 OUTPUT-VOLTAGE ACCURACY vs. LOAD M A X 1 8 5 8 t o c0 2 LOAD (A) O U TP U T V O LT A G E A C C U R A C Y ( % ) 105 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 15 OUT2 OUT1 VL VOLTAGE ACCURACY vs. LOAD CURRENT M A X 1 8 5 8 t o c0 3 LOAD CURRENT (mA) V L V O LT A G E A C C U R A C Y 10050 -1.5 -1.0 -0.5 0 0.5 -2.0 0 150 SWITCHING FREQUENCY vs. ROSC M A X 1 8 5 8 t o c0 4 ROSC (kΩ) S W IT C H IN G F R EQ U EN C Y ( kH z) 5040302010 100 200 300 400 500 600 0 0 60 LOAD TRANSIENT RESPONSE (OUTPUT 1) MAX1858 toc05 10µs/div 0A IOUT1 10A VOUT2 50mV/div AC-COUPLED VOUT1 50mV/div AC-COUPLED LOAD TRANSIENT RESPONSE (OUTPUT 2) MAX1858 toc06 10µs/div 0A IOUT2 10A VOUT1 50mV/div AC-COUPLED VOUT2 50mV/div AC-COUPLED

Page 6

SOFT-START AND SOFT-STOP WAVEFORM MAX1858 toc07 1ms/div 0V 1V/div VOUT2 VOUT1 1V/div 5V 0V VEN 0V RESET TIMEOUT MAX1858 toc08 100ms/div VOUT1 0V 0V 0V VOUT2 5V/div 0V EN VRST OUT-OF-PHASE WAVEFORM MAX1858 toc09 1µs/div VOUT1 20mV/div VOUT2 20mV/div 12V VLX1 VLX2 0V 0V 12V M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR _______________________________________________________________________________________ 5 EXTERNALLY SYNCHRONIZED SWITCHING WAVEFORM MAX1858 toc10 400ns/div VOUT1 10mV/div AC-COUPLED 5V 5V 0V 0V VSYNC VCK0 VLX1 10V 0V CKO OUTPUT WAVEFORM MAX1858 toc11 VOUT1 10mV/div AC-COUPLED 5V 0V VCK0 VLX1 10V 0V SYNC = GND 400ns/div SHORT-CIRCUIT CURRENT FOLDBACK AND RECOVERY MAX1858 toc13 IOUT1 = 10A (5A/div) VOUT1 = 1.8V (1V/div) VOUT2 = 2.5V (1V/div) IOUT2 = 10A (5A/div) SHORT VOUT2 CKO OUTPUT WAVEFORM MAX1858 toc12 400ns/div VOUT1 10mV/div 5V 0V VCK0 VLX1 10V 0V SYNC = VL Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, TA = +25°C, unless otherwise noted.)

Page 7

M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR 6 _______________________________________________________________________________________ Pin Description PIN NAME FUNCTION 1 COMP2 Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series resistor (RCOMP2) and capacitor (CCOMP2A) to GND in parallel with a second compensation capacitor (CCOMP2B) as shown in Figure 1. 2 FB2 Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive-divider between REG2’s output and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB2 to a resistive voltage-divider from REF to REG2’s output. See the Setting the Output Voltage section. 3 ILIM2 Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to 100mV if ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the REG2’s current-limit threshold (VITH2) from 50mV (RILIM2 = 100kΩ) to 300mV (RILIM2 = 600kΩ). See the Setting the Valley Current Limit section. 4 OSC Oscillator Frequency Set Input. The controller generates the clock signal by dividing down the oscillator, so the switching frequency equals half the synchronization frequency (fSW = fOSC/2). Connect a resistor from OSC to GND (ROSC) to set the switching frequency from 100kHz (ROSC = 60kΩ) to 600kHz (ROSC = 10kΩ). The controller still requires ROSC when an external clock is connected to SYNC. When using SYNC, set ROSC for one half of the SYNC input. 5 V+ Input Supply Voltage. 4.75V to 23V. 6 REF 2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor. 7 GND Analog Ground 8 CKO Clock Output. Clock Output for external 2- or 4-phase synchronization (see the Clock Synchronization (SYNC, CKO) section). 9 SYNC Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect SYNC to a 200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase operation as a master controller. Connect SYNC to VL for 4-phase operation as a master controller (see the Clock Synchronization (SYNC, CKO) section). 10 ILIM1 Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to 100mV if ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1’s current-limit threshold (VITH1) from 50mV (RILIM1 = 100kΩ) to 300mV (RILIM1 = 600kΩ). See the Setting the Valley Current Limit section. 11 FB1 Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive-divider between REG1’s output and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB1 to a resistive voltage-divider from REF and REG1’s output. See the Setting the Output Voltage section. 12 COMP1 Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series resistor (RCOMP1) and capacitor (CCOMP1A) to GND in parallel with a second compensation capacitor (CCOMP1B) as shown in Figure 1. 13 RST Open-Drain Reset Output. RST is low when either output voltage is more than 10% below its regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high impedance as long as both outputs maintain regulation. Connect a resistor between RST and the logic supply for logic-level voltages.

Page 8

Detailed Description DC-DC PWM Controller The MAX1858 step-down converters use a PWM volt- age-mode control scheme (Figure 2) for each out-of- phase controller. The controller generates the clock signal by dividing down the internal oscillator or SYNC input when driven by an external clock, so each con- troller’s switching frequency equals half the oscillator frequency (fSW = fOSC/2). An internal transconductance error amplifier produces an integrated error voltage at the COMP pin, providing high DC accuracy. The volt- age at COMP sets the duty cycle using a PWM com- parator and a ramp generator. At each rising edge of the clock, REG1’s high-side N-channel MOSFET turns on and remains on until either the appropriate duty cycle or until the maximum duty cycle is reached. REG2 operates out-of-phase, so the second high-side MOSFET turns on at each falling edge of the clock. During each high-side MOSFET’s on-time, the associat- ed inductor current ramps up. During the second-half of the switching cycle, the high- side MOSFET turns off and the low-side N-channel MOSFET turns on. Now the inductor releases the stored energy as its current ramps down, providing current to the output. Under overload conditions, when the induc- tor current exceeds the selected valley current-limit (see the Current-Limit Circuit (ILIM_) section), the high- side MOSFET does not turn on at the appropriate clock edge and the low-side MOSFET remains on to let the inductor current ramp down. Synchronized Out-of-Phase Operation The two independent regulators in the MAX1858 oper- ate 180° out-of-phase to reduce input filtering require- ments, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component cost and saves board space, making the MAX1858 ideal for cost-sensitive applications. Dual-switching regulators typically operate both con- trollers in-phase, and turn on both high-side MOSFETs at the same time. The input capacitor must then sup- port the instantaneous current requirements of both controllers simultaneously, resulting in increased ripple voltage and current when compared to a single switch- ing regulator. The higher RMS ripple current lowers effi- ciency due to power loss associated with the input capacitor’s effective series resistance (ESR). This typi- cally requires more low-ESR input capacitors in parallel to minimize input voltage ripple and ESR-related loss- es, or to meet the necessary ripple-current rating. M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR _______________________________________________________________________________________ 7 Pin Description (continued) PIN NAME FUNCTION 14 DH1 High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1. 15 LX1 External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver. 16 BST1 Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic capacitor and diode according to Figure 1. 17 DL1 Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to VL. 18 PGND Power Ground 19 VL Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers and external boost circuitry for the high-side gate drivers. 20 DL2 Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to VL. 21 BST2 Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic capacitor and diode according to Figure 1. 22 LX2 External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver. 23 DH2 High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2. 24 EN Active-High Enable Input. A logic low shuts down both controllers. Connect to VL for always-on operation.

Page 9

M A X 1 8 5 8 With dual synchronized out-of-phase operation, the MAX1858’s high-side MOSFETs turn on 180° out-of- phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple-current rating, allowing fewer or less expensive capacitors, and reduces shield- ing requirements for EMI. The Out-of-Phase Waveforms in the Typical Operating Characteristics demonstrate synchronized 180° out-of-phase operation. Internal 5V Linear Regulator (VL) All MAX1858 functions are internally powered from an on-chip, low-dropout 5V regulator. The maximum regu- lator input voltage (V+) is 23V. Bypass the regulator’s output (VL) with a 4.7µF ceramic capacitor to PGND. The VL dropout voltage is typically 500mV, so when V+ is greater than 5.5V, VL is typically 5V. The MAX1858 also employs an undervoltage lockout circuit that dis- ables both regulators when VL falls below 4.5V. VL should also be bypassed to GND with 0.1µF. Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR 8 _______________________________________________________________________________________ V+ BST1 DH1 LX1 DL1 VL BST2 DH2 LX2 DL2 FB1 COMP1 *IRF7811W **OPTIONAL FB2 COMP2 PGND REF GND OSC SYNC CKO ILIM1 ILIM2EN OFF ON RESET OUTPUT CLOCK OUTPUT VL RST MAX1858 CV+ 0.22µF CIN1 2 × 10µF COUT1 4 × 220µF NH1* NL1* L1 1µH VIN 6V - 23V CBST1 0.1µF R1A 8.06kΩ R1B 10kΩ CCOMP1B 100pF CREF 0.22µF CCOMP2B 100pF R2B 10kΩ 118kΩ 140kΩ R2A 15kΩ 4.7Ω4.7Ω RV+ 4.7Ω NL2* ** ** NH2* L2 1.2µH COUT2 4 × 220µF CIN2 2 × 10µF OUTPUT2 VOUT = 2.5V CBST2 0.1µF CVL 4.7µF 0.1µF CCOMP2A 6.8nF RCOMP2 8.2kΩ 96.5kΩ D3 CMSSH-3 OUTPUT1 VOUT = 1.8V RCOMP1 5.9kΩ CCOMP1A 10nF 84.5kΩ D2 CMSSH-3 Figure 1. Standard Application Circuit

Page 10

The internal VL linear regulator can source over 50mA to supply the IC, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. When driving large FETs, little or no regulator cur- rent may be available for external loads. For example, when switched at 600kHz, a single large FET with 18nC total gate charge requires 18nC x 600kHz = 11mA. To drive larger MOSFETs, or deliver larger loads, connect VL to an external power supply from 4.75V to 5.5V. M A X 1 8 5 8 Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR _______________________________________________________________________________________ 9 CONVERTER 1 R S Q ILIM1 DL1 PGND LX1 DH1 BST1 FB1 COMP1 SOFT-START DAC SEQUENCING OSCILLATOR OSC SYNC CK0 V+5V LINEAR REGULATOR VLGND REF DL2 LX2 DH2 BST2 ILIM2FB2 COMP2 CONVERTER 2 RESET EN UVLO AND SHUTDOWN VREF 2V MAX1858 RST VREF VL Q VL - 0.5V 5µA Figure 2. Functional Diagram

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