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MAX191BCNG+

hot MAX191BCNG+

MAX191BCNG+

For Reference Only

Part Number MAX191BCNG+
Manufacturer Maxim Integrated
Description IC ADC 12BIT 100KSPS W/REF 24DIP
Datasheet MAX191BCNG+ Datasheet
Package 24-DIP (0.300", 7.62mm)
In Stock 434 piece(s)
Unit Price $ 18.86 *
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MAX191BCNG+

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MAX191BCNG+ Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet MAX191BCNG+ Datasheet
Package24-DIP (0.300", 7.62mm)
Series-
Number of Bits12
Sampling Rate (Per Second)100k
Number of Inputs1
Input TypePseudo-Differential
Data InterfaceSPI, Parallel
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeInternal
Voltage - Supply, Analog��5V, 5V
Voltage - Supply, Digital5V
Operating Temperature0°C ~ 70°C
Package / Case24-DIP (0.300", 7.62mm)
Supplier Device Package24-PDIP

MAX191BCNG+ Datasheet

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General Description The MAX191 is a monolithic, CMOS, 12-bit analog-to- digital converter (ADC) featuring differential inputs, track/hold (T/H), internal voltage reference, internal or external clock, and parallel or serial µP interface. The MAX191 has a 7.5µs conversion time, a 2µs acquisition time, and a guaranteed 100ksps sample rate. The MAX191 operates from a single +5V supply or from dual ±5V supplies, allowing ground-referenced bipolar input signals. The device features a logic power-down input, which reduces the 3mA VDD supply current to 50µA max, including the internal-reference current. Decoupling capacitors are the only external compo- nents needed for the power supply and reference. This ADC operates with either an external reference, or an internal reference that features an adjustment input for trimming system gain errors. The MAX191 provides three interface modes: two 8-bit parallel modes, and a serial interface mode that is com- patible with SPITM, QSPITM, and MICROWIRETM serial- interface standards. ________________________Applications Battery-Powered Data Logging PC Pen Digitizers High-Accuracy Process Control Electromechanical Systems Data-Acquisition Boards for PCs Automatic Testing Systems Telecommunications Digital Signal Processing (DSP) ____________________________Features ♦ 12-Bit Resolution, 1/2LSB Linearity ♦ +5V or ±5V Operation ♦ Built-In Track/Hold ♦ Internal Reference with Adjustment Capability ♦ Low Power: 3mA Operating Mode 20µA Power-Down Mode ♦ 100ksps Tested Sampling Rate ♦ Serial and 8-Bit Parallel µP Interface ♦ 24-Pin Narrow DIP and Wide SO Packages M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ________________________________________________________________ Maxim Integrated Products 1 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 VDD CLK/SCLK PAR HBENAIN- AIN+ VSS PD TOP VIEW CS RD D7/DOUT D6/SCLKOUTBIP AGND REFADJ VREF 16 15 14 13 9 10 11 12 D5/SSTRB D4 D3/D11 D2/D10DGND D1/D9 D0/D8 BUSY DIP/SO MAX191 Pin Configuration 2.46V REF IN REF OUT 12-BIT SAR ADC OSC CONTROL LOGIC 3-STATE OUTPUT 8-BIT BUS AND SERIAL I/O 18 17 16 15 14 13 11 10 20 19 9 21 D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8 CS RD BUSY HBEN REFADJ VREF AIN + AIN - 5 6 3 4 24 23 VDD CLK/SCLK 7 12 PD 1 22 8 AGND DGND 2 PAR BIP MAX191 12 VSS Functional Diagram 19-4506; Rev 4; 2/97 PART TEMP. RANGE PIN-PACKAGE MAX191ACNG 0°C to +70°C 24 Narrow Plastic DIP 24 Wide SO ±1/2 ±1 ±1/2 ERROR (LSB) 24 Narrow Plastic DIP MAX191BCNG MAX191ACWG 0°C to +70°C 0°C to +70°C MAX191BCWG 0°C to +70°C 24 Wide SO ±1 MAX191BC/D Dice* ±10°C to +70°C MAX191AENG -40°C to +85°C 24 Narrow Plastic DIP ±1/2 MAX191BENG -40°C to +85°C 24 Narrow Plastic DIP ±1 MAX191AEWG -40°C to +85°C 24 Wide SO ±1/2 MAX191AMRG 24 Narrow CERDIP** ±1/2 MAX191BMRG 24 Narrow CERDIP** ±1 -55°C to +125°C -55°C to +125°C MAX191BEWG -40°C to +85°C 24 Wide SO ±1 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. EVALU ATION KIT M ANUAL FOLLO WS DA TA SH EET * Dice are specified at TA = +25°C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883. Ordering Information

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M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD to DGND............................................................-0.3V to +7V VSS to AGND ............................................................-7V to +0.3V VDD to VSS ..............................................................................12V AGND, VREF, REFADJ to DGND................-0.3V to (VDD + 0.3V) AIN+, AIN-, PD to VSS.................................-0.3V to (VDD + 0.3V) CS, RD, CLK, BIP, HBEN, PAR, to DGND....-0.3V to (VDD + 0.3V) BUSY, D0–D7 to DGND..............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW Wide SO (derate 11.76mW/°C above +70°C) ......................941mW Narrow CERDIP (derate 12.50mW/°C above +70°C) ........1000mW Operating Temperature Ranges MAX191_C_ _ ................................................................0°C to +70°C MAX191_E_ _ .............................................................-40°C to +85°C MAX191_M_ _ ..........................................................-55°C to +125°C Storage Temperature Range.....................................-65°C to +160°C Lead Temperature (soldering, 10sec).....................................+300°C PARAMETER CONDITIONS MIN TYP MAX UNITS Offset Error MAX191B ±2 LSB MAX191A ±1 Differential Nonlinearity No missing codes over temperature ±1 LSB Integral Nonlinearity MAX191B ±1 LSB MAX191A ±2 Gain Error (Note 3) MAX191B ±3 LSB Resolution 12 Bits MAX191A ±1/2 Gain-Error Tempco (Note 4) Excludes internal-reference drift ±0.2 ppm/°C 1kHz input signal, TA = +25°C 70 dB 1kHz input signal, TA = +25°C -80 dB Spurious-Free Dynamic Range 1kHz input signal, TA = +25°C 80 dB Synchronous CLK (12 to 13 CLKs) Conversion Time (Note 5) Internal CLK, CL = 120pF 6 12 18 µs Track/Hold Acquisition Time 2 µs Aperture Delay 25 ns Aperture Jitter 50 ps 0.1 1.6 MHz Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion (up to the 5th Harmonic) External Clock Frequency Range (Note 6) SYMBOL DNL INL SINAD SFDR THD tCONV fCLK 7.50 8.125 DC ACCURACY (Note 2) DYNAMIC ACCURACY (sample rate = 100kHz, VIN = 4Vp-p) CONVERSION RATE

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mA M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PD External Leakage for Float State (Note 12) VFLT V2.8Reference compensation mode—externalPD Floating-State Voltage nA±100Maximum current allowed for “floating state” IIN µA±20PD = 0V to VDD (Note 11)PD Input Current ±200PD = high/float IIN µA ±0.1PD = low Input Current CLK CIN pF10Input Capacitance (Note 6) VIL V0.5PD Input Low Voltage VIH V4.5PD Input High Voltage IIN µA±10VIN = 0V to VDDInput Current VIH V2.4CS, RD, CLK, HBEN, PAR, BIPInput High Voltage VIL V0.8CS, RD, CLK, HBEN, PAR, BIPInput Low Voltage kΩ5 10External-reference modeInput Resistance mA1External-reference = 5VInput Current REFADJ Input Adjustment Range (Note 10) V2.5 5.0External-reference modeInput Voltage Range µA60REFADJ = 5VREFADJ Input Current V2.4REFADJ Output Voltage V4.5REFADJ Disable Threshold mV-60 30 µV±300VDD = ±5%, VSS = ±5%Power-Supply Rejection µF4.7Reference compensation mode—externalCapacitive Load Required mA18Output Short-Circuit Current mV4TA = +25°C, IOUT = 0mA to 2mALoad Regulation SYMBOL UNITSMIN TYP MAXCONDITIONSPARAMETER Input Voltage Range (Note 7) VVSS VDD Input Capacitance (Note 6) pF45 80 Input Leakage Current µA±10VIN = VSS to VDD 50MAX191_C VREF Output Voltage V4.076 4.096 4.116TA = +25°C Small-Signal Bandwidth MHz2 60MAX191_E Output Current Capability (Note 9) mA2TA = +25°C VREF Output Tempco (Note 8) ppm/°C 80MAX191_M ANALOG INPUT INTERNAL REFERENCE REFERENCE INPUT LOGIC INPUTS

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M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 4 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER RD Pulse Width CONDITIONS 150 UNITS MAX191C/E MIN TYP MAX 150 ns 140 0 140 MAX191M MIN TYP MAX 150 160 0 160 CL = 100pF 120 ns 80 100 ns120t8 110 120100 nst7 100 12080 nst6 0 0CS to RD Hold Time 0 nst5 SYMBOL RD to BUSY Delay CS to RD Setup Time 0 ns CL = 50pF 120 ns t4 t3 t2 t1 TIMING CHARACTERISTICS (Figures 6–10) (VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14) Aperture Delay Jitter < 50ps 25 nst12 2 22 200 200200 nst10 HBEN to RD Hold Time 0 0 ns0t9 Data Access Time (Note 15) Data Setup Time After BUSY (Note 15) Bus-Relinquish Time (Note 16) HBEN to RD Setup Time Delay Between Read Operations (Note 6) 200 230 ns260t13CLK to BUSY Delay (Note 6) 100 130 ns150t14 SCLKOUT to SSTRB Rise Delay SCLKOUT to SSTRB Fall Delay 100 130 ns150t15 TA = +25°C MIN TYP MAX µst11Delay Between Conversions VSS V-5.25 0Negative Supply Voltage IDD VDD VOL VOH COUT IL µA20 50 V0.4IOUT = 1.6mA mA3 5 V4.75 5.25Positive Supply Voltage Output Low Voltage SYMBOL PD = low PD = high/float PD = low LSB±1/2FS change, VSS = -5V ±5%Negative Supply Rejection (Note 13) LSB±1/2FS change, VDD = 5V ±5%Positive Supply Rejection (Note 13) ISS µA V pF 4.0IOUT = -200µAOutput High Voltage 1 20 CS = RD = VDD, AIN = 5V, D0/D8–D7/ DOUT = 0V or VDD, HBEN = PAR = BIP = 0V or VDD Positive Supply Current 15 PD = high/float Three-State Output Capacitance (Note 6) 20 100 µA Negative Supply Current UNITS ±10D0/D8-D7/DOUT MIN TYP MAXCONDITIONS Three-State Leakage Current PARAMETER LOGIC OUTPUTS POWER REQUIREMENTS

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M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down _______________________________________________________________________________________ 5 PARAMETER SCLK to SCLKOUT Delay CONDITIONS 160 UNITS ns CS to DOUT Three-State 100 ns SYMBOL CS or RD Setup Time CS or RD Hold Time ns 150 ns t20 t19 t17 t16 TIMING CHARACTERISTICS (Figures 6–10) (continued) (VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14) 10 MAX191C/E MIN TYP MAX 180 110 10 150 MAX191M MIN TYP MAX 200 120 10 150 310 350SCLK to SSTRB Delay 260 nst23 260 280SCLK to DOUT Delay 240 nst22 130SCLKOUT to DOUT Delay 100 nst21 150 Note 1: Performance at power-supply tolerance limits guaranteed by power-supply rejection test. Note 2: VDD = 5V, VSS = 0V, FS = VREF. Note 3: FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB. Note 4: Gain-Error Tempco = ∆ GE is the gain-error change from TA = +25°C to TMIN or TMAX. Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Note 6: Guaranteed by design, not production tested. Note 7: AIN+, AIN- must not exceed supplies for specified accuracy. Note 8: VREF TC = ∆ T, where ∆ VREF is reference-voltage change from TA = +25°C to TMIN or TMAX. Note 9: Output current should not change during conversion. This current is in addition to the current required by the internal DAC. Note 10: REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V. This will typically result in a 1.7 times larger change in the REF output (Figure 19a). Note 11: This current is included in the PD supply current specification. Note 12: Floating the PD pin guarantees external compensation mode. Note 13: VREF = 4.096V, external reference. Note 14: All input control signals are specified with tr = tf = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Note 15: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 16: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. TA = +25°C MIN TYP MAX

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M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 6 _______________________________________________________________________________________ __________________________________________Typical Operating Characteristics 10 0.01 0.1 10 CLOCK FREQUENCY vs. TIMING CAPACITOR 0.1 1 TIMING CAPACITOR (nF) C LO C K F R EQ U EN C Y ( M H z) 1 SEE FIGURE 5 TA = +25˚C G R 1 9 1 -A 0 -60 150 5 25 TEMPERATURE (°C) S U P P LY C U R R EN T (µ A ) 120 15 10 0 60 20 -30 30 90 VDD = +5V VSS = -5V PD = 0V ISS IDD POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE G R 1 9 1 -B 0 -60 150 5 25 TEMPERATURE (°C) I S S ( µA ) 120 15 10 0 60 20 -30 30 90 NEGATIVE SUPPLY CURRENT vs. TEMPERATURE G R 1 9 1 -C 3.5 0.5 -60 -30 30 60 1.0 2.0 TEMPERATURE (°C) I D D ( m A ) 0 1.5 90 120 150 2.5 3.0 0 POSITIVE SUPPLY CURRENT vs. TEMPERATURE G R 1 9 1 -D 0 -140 0 2 6 1kHz FFT PLOT -100 -40 G R 1 9 1 -E FREQUENCY (kHz) S IG N A L A M P LI TU D E (d B ) 4 -80 1 3 5 -120 -60 -20 fIN = 1kHz fS = 100kHz SNR = 72dB TA = +25˚C -94.3dB -96.1dB-98.0dB -93.8dB 0 -140 0 10 30 40 10kHz FFT PLOT -100 -60 G R 1 9 1 -F FREQUENCY (kHz) S IG N A L A M P LI TU D E (d B ) 15 -80 -120 -40 -20 fIN = 10kHz fS = 100kHz SNR = 71.2dB TA = +25˚C 5 20 25 35 -86.0dB -90.8dB

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M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down _______________________________________________________________________________________ 7 Pin Description Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal oscillator. High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs onto the data bus. In serial mode, HBEN = low enables SCLKOUT to operate during the conversion only, HBEN = high enables SCLKOUT to operate continuously, provided CS is low. Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLKOUT, SSTRB, and DOUT into a high-impedance state. Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLKOUT and SSTRB when CS is low. RD = high forces SCLKOUT and SSTRB into a high-impedance state. D6/SCLKOUT 7 Analog GroundAGND 24 Positive Supply, +5V ±5%VDD 23 CLK/SCLK 22 Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.PAR 21 HBEN 20 CS 19 RD 18 Three-State Data Output/Data Output in serial modeD7/DOUT 13 Three-State Data OutputsD2/D10 14 Three-State Data Outputs: MSB = D11D3/D11 15 Three-State Data OutputD4 16 Three-State Data Output/Serial Strobe Output in serial modeD5/SSTRB 17 Three-State Data Output/Serial Clock Output in serial mode 10 Three-State Data Outputs: LSB = D0D0/D8 11 Three-State Data OutputsD1/D9 12 Digital GroundDGND Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic high selects normal operation, internal-reference compensation mode. An open-circuit condition selects normal operation, external-reference compensation mode. PIN 9 8 6 BUSY Output is low during a conversion.BUSY BIP = low selects unipolar mode BIP = high selects bipolar mode (see Gain and Offset Adjustment section) BIP 5 4 3 Reference Adjust. Connect to VDD to use an extended reference at VREF.REFADJ Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to VDD. VREF Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section).AIN- 2 1 Sampled Analog InputAIN+ Negative Supply, 0V to -5.25VVSS PD FUNCTIONNAME

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_______________Detailed Description The MAX191 uses successive approximation and input track/hold (T/H) circuitry to convert an analog input sig- nal to a 12-bit digital output. Flexible control logic pro- vides easy interface to microprocessors (µPs), so most applications require only the addition of passive com- ponents. No external hold capacitor is required for the T/H. Figure 3 shows the MAX191 in its simplest opera- tional configuration. Pseudo-Differential Input The sampling architecture of the ADC’s analog com- parator is illustrated in the Equivalent Input Circuit (Figure 4). A capacitor switching between the AIN+ and AIN- inputs acquires the signal at the ADC’s ana- log input. At the end of the conversion, the capacitor reconnects to AIN+ and charges to the input signal. An external input buffer is usually not needed for low- bandwidth input signals (<100Hz) because the ADC disconnects from the input during the conversion. In unbuffered applications, an input filter capacitor reduces conversion noise, but also may limit input bandwidth. When converting a single-ended input signal, AIN- should be connected to AGND. If a differential signal is connected, consider that the configuration is pseudo differential—only the signal side to the input channel is held by the T/H. The return side (AIN-) must remain sta- ble within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1µF capacitor from AIN- to AGND. Analog Input—Track/Hold The T/H enters its tracking mode when the ADC is des- elected (CS pin is held high and BUSY pin is high). Hold mode starts approximately 25ns after a conver- sion is initiated. The variation in this delay from one conversion to the next (aperture jitter) is about 50ps. Figures 6–10 detail the T/H and interface timing for the M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 8 _______________________________________________________________________________________ DN 3k CL DGND +5V 3k DN CL DGND a. High-Z to VOH and VOL to VOH b. High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Access Time DN 3k 10pF DGND +5V 3k DN 10pF DGND a. VOH to High-Z b. VOL to High-Z Figure 2. Load Circuits for Bus-Relinquish Time 1 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PD AIN+ AIN- VREF REFADJ AGND BIP BUSY DO/DB D1/D9 DGND VSS 2 VDD CLK/SCLK PAR HBEN CS RD D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 OPEN OUTPUT STATUS 4.7µF 0.1µF 0.1µF 0V TO -5V +5V SERIAL/PARALLEL INTERFACE MODE µP CONTROL INPUTS MAX191 C1 NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK. µP DATA BUS Figure 3. Operational Diagram

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various interface modes. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is cal- culated by: tACQ = 10(RS + RIN)CHOLD (but never less than 2µs), where RIN = 2kΩ , RS = source impedance of the input signal, and CHOLD = 32pF (see Figure 4). Input Bandwidth The ADC’s input tracking circuitry has a 1MHz typical large-signal bandwidth characteristic, and a 30V/µs slew rate. It is possible to digitize high-speed transients and measure periodic signals with bandwidths exceed- ing the ADC’s sample rate of 100ksps by using under- sampling techniques. Note that if undersampling is used to measure high-frequency signals, special care must be taken to avoid aliasing errors. Without ade- quate input bandpass filtering, out-of-band signals and noise may be aliased into the measurement band. Input Protection Internal protection diodes, which clamp the analog input to VDD and VSS , allow AIN+ to swing from (VSS - 0.3V) to (VDD + 0.3V) with no risk of damage to the ADC. However, for accurate conversions near full scale, AIN+ should not exceed the power supplies by more than 50mV because ADC accuracy is affected when the pro- tection diodes are even slightly forward biased. Digital Interface Starting a Conversion In parallel mode, the ADC is controlled by the CS, RD, and HBEN inputs, as shown in Figure 6. The T/H enters hold mode and a conversion starts at the falling edge of CS and RD while HBEN (not shown) is low. BUSY goes low as soon as the conversion starts. On the falling edge of the 13th input clock pulse after the conversion starts, BUSY goes high and the conversion result is latched into three-state output buffers. In seri- al mode, the falling edge of CS initiates a conversion, and the T/H enters hold mode. Data is shifted out seri- ally as the conversion proceeds (Figure 10). See the Parallel Digital-Interface Mode and Serial-Interface Mode sections for details. Internal/External Clock Figure 5 shows the MAX191 clock circuitry. The ADC includes internal circuitry to generate a clock with an external capacitor. As indicated in the Typical Operating Characteristics, a 120pF capacitor con- nected between the CLK and DGND pins generates a 1MHz nominal clock frequency (Figure 5). Alternatively, an external clock (between 100kHz and 1.6MHz) can be applied to CLK. When using an exter- nal clock source, acceptable clock duty cycles are M A X 1 9 1 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down _______________________________________________________________________________________ 9 12-BIT DAC TRACK CHOLD COMPARATOR HOLD 32pF HOLD CSWITCH 10pF CPACKAGE 5pF AIN + AIN - RIN Figure 4. Equivalent Input Circuit CEXT DGND CLK +1.6V CLOCK MAX191 NOTE: CEXT = 120pF GENERATES 1MHz NOMINAL CLOCK Figure 5. Internal Clock Circuit

MAX191BCNG+ Reviews

Average User Rating
5 / 5 (146)
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Enri*****Wood

October 27, 2019

Fast shipping, work as designed. Made some circuitry with these components and they work well.

Spence*****ngston

September 30, 2019

Super easy to replace and labelled terminals made it a quick replacement.

Ram***** Dani

August 30, 2019

FAST POSTING TOP CONDITION RECORD HAVE A GREAT CHRISTMAS

Celi*****evens

August 29, 2019

Heisener has been to my No.1 supplier for years. Very quick and easy when knowing what you are looking for.

Luci*****Waller

August 13, 2019

They work great exactly what I needed.

Brad*****vant

August 1, 2019

Your prices are low and your website is customer-use friendly.

Migue*****daram

July 21, 2019

I was glad to find this product being sold at a great price. They were the perfect replacement.

Landyn*****acharyya

July 15, 2019

What can I say, great value for the money. I only needed 2 but now I have some spares for future projects. They got the job done, nothing more I can say.

Fatim*****donald

May 31, 2019

They work great and I hope to find more used for the extra ones.

Finl*****auer

March 9, 2019

I tested some and all look good.

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If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

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