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MCZ33285EF

hot MCZ33285EF

MCZ33285EF

For Reference Only

Part Number MCZ33285EF
Manufacturer NXP
Description IC TMOS DRIVER DUAL HISIDE 8SOIC
Datasheet MCZ33285EF Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 1248 piece(s)
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Lead Time Can Ship Immediately
Estimated Delivery Time Jan 27 - Feb 1 (Choose Expedited Shipping)
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MCZ33285EF

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MCZ33285EF Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - PMIC - Gate Drivers
Datasheet MCZ33285EF Datasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
Driven ConfigurationHigh-Side
Channel TypeSynchronous
Number of Drivers2
Gate TypeN-Channel MOSFET
Voltage - Supply7 V ~ 40 V
Logic Voltage - VIL, VIH0.7V, 1.7V
Input TypeNon-Inverting
Operating Temperature-40°C ~ 125°C (TA)
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

MCZ33285EF Datasheet

Page 1

Page 2

Document Number: MC33285 Rev. 5.0, 2/2007 Freescale Semiconductor Advance InformationDual High-Side TMOS Driver A single input controls the 33285 in driving two external high-side N- Channel TMOS power FETs controlling incandescent or inductive loads. Pulse Width Modulated (PWM) input control to 1.0 kHz is possible. The 33285 contains a common internal charge pump used to enhance the Gate voltage of both FETs. An external charge capacitor provides access to the charge pump output. Both external FETs are protected against inductive load transients by separate internal source-to-gate dynamic clamps. The power FETs are protected by the 33285 with short-circuit delay time of 800 µs. The device is designed to withstand reverse polarity battery and load dump transients, encountered in automotive applications. Features • PWM Capability • Power TMOS Number One (OUT1) Short-Circuit Detection and Short-Circuit Protection • Voltage Range 7.0 V ≤ 40 V • Extended Temperature Range from -40°C ≤ 125°C • Load Dump Protected • Overvoltage Detection and Activation of OUT2 During Overvoltage • Single Input Control for Both Output Stages • Capacitor Value of 100 nF Connected to Pin CP • Analog Input Control Measurement Detection • OUT1 LOAD Leakage Measurement Detection • Pb-Free Packaging Designated by Suffix Code EF Figure 1. 33285 Simplified Application Diagram HIGH-SIDE TMOS DRIVER D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-PIN SOICN 33285 ORDERING INFORMATION Device Temperature Range (TA) Package MC33285D/R2 -40°C to 125°C 8 SOICN MCZ33285EF/R2 SRC OUT1 OUT2 DRN GND 33285 IN CP VCC VPWR Motor VCC Input Control* This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved.

Page 3

INTERNAL BLOCK DIAGRAMINTERNAL BLOCK DIAGRAM Figure 2. 33285 Simplified Internal Block and Typical Applications Diagram OUT2 OUT1 SRC IN VCC Rthr DRN VOUT2-VDRN> VTH2 VOUT1-VSRC> VTH1 CP Charge PumpOscillator andR S Load Dump R S Q Detection S R Q OUT2 Activation Time THRIN1 THRIN2 VREF CCP VIGN M Kl.30 + - - + + - + - OC Detection Start tOCDET IOUTN1 SCPC IOUTN2 GND ION2 ION1 Bandgap tLDDET tOUT2ECT Divider tOCDETAnalog Integrated Circuit Device Data 2 Freescale Semiconductor 33285

Page 4

PIN CONNECTIONSPIN CONNECTIONS Figure 3. 33285 Pin Connections Table 1. 33285 Pin Definitions Pin Number Pin Name Formal Name Definition 1 SRC Source OUT2 external FET Source connection 2 OUT1 Output 1 This pin is output number 1 3 DRN Drain OUT1 and OUT2 external FET Drain connection 4 OUT2 Output 2 This pin is output number 2 5 CP Charge Pump External capacitor connection for internal the Charge Pump 6 VCC Voltage Power Supply Battery supply voltage 7 GND Ground This is the ground pin. 8 IN Input Voltage level sensitive input for OUT1 and OUT2 2 3 4 8 7 6 5 11 2 4 3 8 7 5 6 IN GND CP VCC SRC OUT1 DRN OUT2Analog Integrated Circuit Device Data Freescale Semiconductor 3 33285

Page 5

ELECTRICAL CHARACTERISTICS MAXIMUM RATINGSELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS Maximum Voltage at Pins OUT1 and OUT2 VOUT VVCC + 20 V Maximum Voltage at Pin CP VCP 50 V Input Voltage VI at DRN VDRN -2.0 to 40 V Input Voltage VI at SRC VSRC -5.0 to 40 V Input Voltage at Pin VCC VCC -2.0 to 40 V Input Voltage at Pin IN. Condition: -2.0 V < VVCC < 40 V VIN -2.0 to VVCC V Operational Voltage VVCC at Pin VCC VVCC 7.0 to VI V THERMAL RATINGS Storage Temperature TSTG -40 to150 °C Operating Ambient Temperature TA -40 to 125 °C Peak Package Reflow Temperature During Reflow (1), (2) TPPRT Note 2 °C Notes 1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Analog Integrated Circuit Device Data 4 Freescale Semiconductor 33285

Page 6

ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions TA from -40°C ≤ 125°C, VCC from 7 V ≤ 20 V, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit OVERVOLTAGE AND OVER CURRENT Load Dump Activation Time tOUT2ACT 300 460 620 ms Error Voltage Threshold VDRN - VSRC 1.12 — 1.44 V SRC PIN 1 Leakage Current ILCDET 15 30 50 mA Leakage Current Detection Time tLCDET 130 200 270 µA DRN PIN 3 Operating Current (7.0 V < VDRN < 20 V) IDRN — — 1.5 mA Leakage Current (0 V < VDRN < 20 V, VVCC < 4.0 V) ILEAK-DRN -5.0 — 5.0 µA OUT1, PIN 2, AND OUT2 PIN 4 Output ON Voltage. Charge Pump ON VON — — VCC + 15 V Turn OFF Current, VOUT > 0.5 V IOUTOFF 66 110 154 µA VCC PIN 6 Supply Voltage Range VCC 7.0 — 40 V Quiescent Supply Current at VCC = 20 V ICC — — 10 mA IN PIN 8 Input Low Voltage OUT1 VIL — — 0.7 V Input High Voltage OUT1 VIH 1.7 — — V Input Hysteresis OUT1 and OUT2 VHYS 0.4 — — V Input Pull Down Current, 0.7 V < VIN < 6.0 V IIN 7.5 15 16.5 µA Open Input Voltage VIOP — — 0.7 V Input Low Voltage OUT2 VIL2 — — 3.0 V Input High Voltage OUT2 VIH2 3.9 — — VAnalog Integrated Circuit Device Data Freescale Semiconductor 5 33285

Page 7

ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA from -40°C ≤ 125°C, VCC from 7 V ≤ 20 V, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit OVER VOLTAGE AND OVER CURRENT Load Dump Detection Time tLDDET 250 400 550 µs Over Current Detection Time tOCDET 520 800 1080 µs OUT1 PIN 2, AND OUT2 PIN 4 Turn ON Time, OUT1: 8.0 nF, 10 µA; OUT2:16 nF, 10 µA -7.0 V < VCC < 10 V, VOUT > VCC + 7.0 -10 V < VCC < 20 V, VOUT > VCC + 11 tON — — — — 1.5 1.5 msAnalog Integrated Circuit Device Data 6 Freescale Semiconductor 33285

Page 8

FUNCTIONAL DESCRIPTION INTRODUCTIONFUNCTIONAL DESCRIPTION INTRODUCTION The power FETs are turned ON by charging their gate capacities with a current flowing out of pins OUT1 and OUT2. During PWM, the values of table below are guaranteed. They are measured with 8.0 nF on OUT1 and 16 nF on OUT2. Test condition VIN: ramp 0 V ≤ 2.5 V or 2.5 V ≤ 5.0 V. Figure 4. Turn On Behavior The output voltages at OUT1 and OUT2 are limited by controlling the current sources ION1, ION2 to avoid current flowing through the external or the internal zener diode. When voltage power supply plus threshold voltage (VCC + VTH) is reached, the current sources are turned OFF. • Threshold VTH1 for OUT1 output voltage control is 7.0 V < VTH1 < VZ • Threshold VTH2 for OUT2 output voltage control is 7.0 V < VTH2 < 15 V Turn Off Characteristics The power FETs on OUT1 and OUT2 are turned OFF by discharging the gate capacity with the constant discharge current IOUTOFF. • Discharge current IOUTxOFF is IOUTxOFF = 110 µA condition: VOUT x > 0.5 V ( VIN < VTHRxIN ) • Test conditions for switching OFF the power FETs: 1. IN open 2. Stages disabled via pin IN 3. Stage OUT1 disabled by an over current error 20 ms 2.5 V 5.0 V IN VCCP THRIN1 THRIN2 IN VOUT1 0 V 0 V 2.5 V IN 0 2.5 V 0 V 5.0 V VOUT2 IN tON1 0 VVCC + 7.0 VOUT2 VOUT2MAX tON2 tON3 VOUT1MAX VOUT1 VOUT2 tON1 tON2 tON3 VOLTAGE VVCC MINIMUM VOUT1, OUT2 AFTER TON1 = 100 µSEC MINIMUM VOUT1,OUT2 AFTER TON2 = 1.0 µSEC MINIMUM VOUT1,OUT2 AFTER TON3 = 1.5 µSEC 7.0 V < VVCC < 10 V 10 V < VVCC < 20 V 20 V < VVCC < 40 V VVCC - 0.7 V VVCC - 0.7 V VVCC - 0.7 V VVCC + 5.95 V VVCC + 9.35 V VVCC + 7.0 V VVCC + 11 VAnalog Integrated Circuit Device Data Freescale Semiconductor 7 33285

Page 9

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODESFUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTRODUCTION The 33285 contains only one charge pump for two outputs.The outputs, OUT1 and OUT2, are switched ON and OFF by the input (IN) .There are three ways to control the outputs: OUT1 can be switched alone OUT1 and OUT2 can be switched together OUT2 can be switched when OUT1 is already on In the last case, the voltage drop on OUT1 when charging OUT2 is limited. The external capacitor (CCP) connected to the CHARGE PUMP (CP) pin is used to store the charge continuously delivered by the charge pump. The voltage on this pin is limited to a maximum value VCPMAX. Both outputs are sourced with a constant current from CCP to switch them ON. Additionally, the gates of the power FETs are precharged from voltage power supply (VCC) to prevent CCP from being discharged by a voltage on OUT1 or OUT2, is still lower than VVCC. The values of the output voltages are limited to VOUT1MAX and VOUT2MAX. The power FET on OUT1 is protected against an exceeded gate-source voltage by an internal zener diode. Channel One protects the N-Channel power FET on OUT1 undercurrent and short-circuit conditions. The drain-source voltage of the FET on OUT1 is checked if Channel One is switched ON. The internal error voltage threshold determines the maximum drain-source voltage allowing the power FET to stay in the ON state. If the measured drain-source voltage exceeds the internal error voltage threshold, the output of the short-circuit protection comparator (SCPC) is enabled. If the output of the SCPC is active longer than tOCDET, output OUT1 is switched OFF. After switching OFF the power FET on OUT1 by an short- circuit condition, the power FET can only be turned ON again by the input IN. When switching OFF the power FETs their gate capacities are discharged by a constant current, IOUTOFF. If the input IN is disconnected, the 33285 outputs, OUT1 and OUT2, are in the OFF state. If overvoltage occurs on the DRAIN (DRN) pin for a time period longer than tLDDET, OUT2 is switched ON for the time tOUT2ACT. In an overvoltage condition OUT1 is OFF if IN is below VIH. INTERNAL ZENER DIODE An on-chip zener diode is placed between OUT1 and The SOURCE (SRC). Design guarantees VZ > VTH1. Zener clamping voltage between OUT1 and SRC is VTH1 < VZ < 20 V PWM CAPABILITY The CPIC2 is PWM capable on OUT2. The loss of charge ON CCP when switching ON OUT2 is refreshed until the Start on the next PWM cycle to a value sufficient to guarantee the specified turn ON behavior. The PWM capability is measured with a test circuit and load conditions: • PWM cycle is period T = 20 ms ; OUT2 is switched ON from 10 to 90 percent of T • Test condition VIN ramps 2.5 V ≤ 5.0 V according to PWM cycle defined above CROSS TALK BETWEEN OUT1 AND OUT2 If output OUT2 is switched ON while OUT1 is already ON, the voltage drop occurring on OUT1 is limited. Voltage drop on OUT1: • 10 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V • 7.0 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V Each time OUT1 is switched ON, a current ILCDET is sourced out of the SRC pin for the time tLCDET to check if there is an external leakage current on that node in the application. The high-side switch on OUT1 is turned ON only if the test is successful.Analog Integrated Circuit Device Data 8 Freescale Semiconductor 33285

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PACKAGING PACKAGE DIMENSIONSPACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. D SUFFIX EF SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASB42564B ISSUE UAnalog Integrated Circuit Device Data Freescale Semiconductor 9 33285

MCZ33285EF Reviews

Average User Rating
5 / 5 (108)
★ ★ ★ ★ ★
5 ★
97
4 ★
11
3 ★
0
2 ★
0
1 ★
0

Myr*****ewan

December 28, 2019

It works fine and does what it has designed for. No regrets.

James*****llahan

December 27, 2019

I have used 2 of the 10 units so far and they work fine.

Dal***** Kade

December 7, 2019

Heisener has been to my No.1 supplier for years. Very quick and easy when knowing what you are looking for.

Gray*****Dubey

October 5, 2019

Excellent shopping cart process, various of products for selection and order fulfillment a good service quality. I rely on them heavily.

Dal***** Hahn

October 5, 2019

Every little component you can always find in here, and good suggestion for relative times too.

Roge*****cker

September 23, 2019

Works as expected. Fits good in circuit board, not lose or slipping around.

Indi*****eppard

August 12, 2019

I was able to make my list of needed parts and use suggested products. The big plus is the fact they show inventory quantity.

Mac*****ond

March 20, 2019

So far all the items still work. I'm using these for some home made solar panels and they're doing great.

Bre***** Tate

March 20, 2019

Item works as described, fast delivery, nice contact!

Ali*****Rao

February 23, 2019

I took the chance and used it and I worked fine for me.

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