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MPC8260ACVVMIBB

hot MPC8260ACVVMIBB

MPC8260ACVVMIBB

For Reference Only

Part Number MPC8260ACVVMIBB
Manufacturer NXP
Description IC MPU MPC82XX 266MHZ 408TBGA
Datasheet MPC8260ACVVMIBB Datasheet
Package 480-LBGA
In Stock 799 piece(s)
Unit Price $ 194.14 *
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MPC8260ACVVMIBB

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MPC8260ACVVMIBB Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microprocessors
Datasheet MPC8260ACVVMIBB Datasheet
Package480-LBGA
SeriesMPC82xx
Core ProcessorPowerPC G2
Number of Cores/Bus Width1 Core, 32-Bit
Speed266MHz
Co-Processors/DSPCommunications; RISC CPM
RAM ControllersDRAM, SDRAM
Graphics AccelerationNo
Ethernet10/100 Mbps (3)
Voltage - I/O3.3V
Operating Temperature-40°C ~ 105°C (TA)
Package / Case480-LBGA
Supplier Device Package408-TBGA (37.5x37.5)

MPC8260ACVVMIBB Datasheet

Page 1

Page 2

© Freescale Semiconductor, Inc., 2005–2009. All rights reserved. Freescale Semiconductor Technical Data This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for .25μm (HiP4) devices in the PowerQUICC II™ MPC8260 communications processor family. These devices include the MPC8260, the MPC8255, the MPC8264, the MPC8265, and the MPC8266. Throughout this document, these devices are collectively referred to as the MPC826xA. Document Number: MPC8260AEC Rev. 2.0, 06/2009 Contents 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical and Thermal Characteristics . . . . . . . . . . . . 7 3. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 23 4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 46 6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 48 7. Document Revision History . . . . . . . . . . . . . . . . . . . 48 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications

Page 3

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 2 Freescale Semiconductor Features Figure 1 shows the block diagram for the MPC8266, the HiP4 superset device. Shaded portions indicate functionality that is not available on all devices; refer to the notes. Figure 1. MPC8266 Block Diagram 1 Features The major features of the MPC826xA family are as follows: • Dual-issue integer core — A core version of the EC603e microprocessor — System core microprocessor supporting frequencies of 150–300 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm 16 Kbytes G2 Core I-Cache I-MMU 16 Kbytes D-Cache D-MMU Communication Processor Module (CPM) Timers Parallel I/O Baud Rate Generators 32 Kbytes 32-bit RISC Microcontroller and Program ROM Serial DMAs 4 Virtual IDMAs 60x-to-PCI Bridge2,3 Bridge Memory Controller Clock Counter System Functions System Interface Unit (SIU) Local Bus 32 bits, up to 83 MHz PCI Bus2,3 32 bits, up to 66 MHz or MCC1 4 MCC2 FCC1 FCC2 FCC3 4 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C Serial Interface 3 MII 2 UTOPIA PortsPorts6 60x Bus Microcode IMA1,3 Dual-Port RAM Interrupt Controller Time Slot AssignerTC Layer Hardware1,3 8 TDM Ports5 Non-Multiplexed I/O 60x-to-Local Bus Interface Unit Notes: 1 MPC8264 2 MPC8265 3 MPC8266 4 Not on MPC8255 5 4 TDM ports on the MPC8255 6 2 MII ports on the MPC8255

Page 4

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 Freescale Semiconductor 3 Features — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without inlining and 1.90 Dhrystones MIPS/MHz with — Supports bus snooping for data cache coherency — Floating-point unit (FPU) • Separate power supply for internal logic and for I/O • Separate PLLs for G2 core and for the CPM — G2 core and CPM can run at different frequencies for power/performance optimization — Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios — Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios • 64-bit data and 32-bit address 60x bus — Bus supports multiple master designs — Supports single- and four-beat burst transfers — 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller — Supports data parity or ECC and address parity • 32-bit data and 18-bit address local bus — Single-master bus, supports external slaves — Eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller • 60x-to-PCI bridge (MPC8265 and MPC8266 only) — Programmable host bridge and agent — 32-bit data bus, 66 MHz, 3.3 V — Synchronous and asynchronous 60x and PCI clock modes — All internal address space available to external PCI host — DMA for memory block transfers — PCI-to-60x address remapping • System interface unit (SIU) — Clock synthesizer — Reset controller — Real-time clock (RTC) register — Periodic interrupt timer — Hardware bus monitor and software watchdog timer — IEEE Std. 1149.1™ standard JTAG test access port • Twelve-bank memory controller — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable peripherals — Byte write enables and selectable parity generation

Page 5

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 4 Freescale Semiconductor Features — 32-bit address decodes with programmable bank size — Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine — Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) — Dedicated interface logic for SDRAM • CPU core can be disabled and the device can be used in slave mode to an external core • Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols — Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Three fast communications controllers supporting the following protocols (only FCC1 and FCC2 on the MPC8255): – 10/100-Mbit Ethernet/IEEE Std. 802.3® CDMA/CS interface through media independent interface (MII) – ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections – Transparent – HDLC—Up to T3 rates (clear channel) — Two multichannel controllers (MCCs) (only MCC2 on the MPC8255) – Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split into four subgroups of 32 channels each. – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC — Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BISYNC) communications – Transparent — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels

Page 6

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 Freescale Semiconductor 5 Features – Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes — Up to eight TDM interfaces (four on the MPC8255) – Supports two groups of four TDM channels for a total of eight TDMs – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit and receive routing, frame synchronization – Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces — Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels — Four independent 16-bit timers that can be interconnected as two 32-bit timers Additional features of the MPC826xA family are as follows: • CPM — 32-Kbyte dual-port RAM — Additional MCC host commands — Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only) • CPM multiplexing — FCC2 can also be connected to the TC layer. • TC layer (MPC8264 and MPC8266 only) — Each of the 8 TDM channels is routed in hardware to a TC layer block – Protocol-specific overhead bits may be discarded or routed to other controllers by the SI – Performing ATM TC layer functions (according to ITU-T I.432) – Transmit (Tx) updates - Cell HEC generation - Payload scrambling using self synchronizing scrambler (programmable by the user) - Coset generation (programmable by the user) - Cell rate by inserting idle/unassigned cells – Receive (Rx) updates - Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA parameters for the delineation state machine - Payload descrambling using self synchronizing scrambler (programmable by the user)

Page 7

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 6 Freescale Semiconductor Features - Coset removing (programmable by the user) - Filtering idle/unassigned cells (programmable by the user) - Performing HEC error detection and single bit error correction (programmable by user) - Generating loss of cell delineation status/interrupt (LOC/LCD) — Operates with FCC2 (UTOPIA 8) — Provides serial loop back mode — Cell echo mode is provided — Supports both FCC transmit modes – External rate mode—Idle cells are generated by the FCC (microcode) to control data rate. – Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate. The TC layer generates idle/unassigned cells to maintain the line bit rate. — Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000) — Cell counters for performance monitoring – 16-bit counters count - HEC error cells - HEC single bit error and corrected cells - Idle/unassigned cells filtered - Idle/unassigned cells transmitted - Transmitted ATM cells - Received ATM cells – Maskable interrupt is sent to the host when a counter expires — Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt — May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps are supported • PCI bridge (MPC8265 and MPC8266 only) — PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz — On-chip arbitration — Support for PCI to 60x memory and 60x memory to PCI streaming — PCI Host Bridge or Peripheral capabilities — Includes 4 DMA channels for the following transfers: – PCI-to-60x to 60x-to-PCI – 60x-to-PCI to PCI-to-60x – PCI-to-60x to PCI-to-60x – 60x-to-PCI to 60x-to-PCI — Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8265) required by the PCI standard as well as message and doorbell registers — Supports the I2O standard

Page 8

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 Freescale Semiconductor 7 Electrical and Thermal Characteristics — Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) — Support for 66 MHz, 3.3 V specification — 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port — Makes use of the local bus signals, so there is no need for additional pins 2 Electrical and Thermal Characteristics This section provides AC and DC electrical specifications and thermal characteristics for the MPC826xA. 2.1 DC Electrical Characteristics This section describes the DC electrical characteristics for the MPC826xA. Table 1 shows the maximum electrical ratings. Table 1. Absolute Maximum Ratings1 1 Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. Rating Symbol Value Unit Core supply voltage2 2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. VDD –0.3 – 2.5 V PLL supply voltage2 VCCSYN –0.3 – 2.5 V I/O supply voltage3 3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation. VDDH –0.3 – 4.0 V Input voltage4 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset. VIN GND(–0.3) – 3.6 V Junction temperature Tj 120 °C Storage temperature range TSTG (–55) – (+150) °C

Page 9

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 8 Freescale Semiconductor Electrical and Thermal Characteristics Table 2 lists recommended operational voltage conditions. NOTE: Core, PLL, and I/O Supply Voltages VDDH, VCCSYN, and VDD must track each other and both must vary in the same direction—in the positive direction (+5% and +0.1 Vdc) or in the negative direction (–5% and –0.1 Vdc). This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC). Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the MPC8280. Note that in PCI mode the I/O interface is different. Figure 2. Overshoot/Undershoot Voltage Table 2. Recommended Operating Conditions1 1 Caution: These are the recommended and tested operating conditions. Proper device operating outside of these conditions is not guaranteed. Rating Symbol Value Unit Core supply voltage VDD 1.7 – 1.92 2 CPU frequency less than or equal to 200 MHz. 1.7–2.13 3 CPU frequency greater than 200 MHz but less than 233 MHz. 1.9 –2.24 4 CPU frequency greater than or equal to 233 MHz. V PLL supply voltage VCCSYN 1.7 – 1.92 1.7–2.13 1.9–2.24 V I/O supply voltage VDDH 3.135 – 3.465 V Input voltage VIN GND (–0.3) – 3.465 V Junction temperature (maximum) Tj 105 5 5 Note that for extended temperature parts the range is (-40)TA – 105Tj. °C Ambient temperature TA 0–70 5 °C GND GND – 0.3 V GND – 1.0 V Not to exceed 10% GVDD of tSDRAM_CLK GVDD + 5% 4 V VIH VIL

Page 10

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0 Freescale Semiconductor 9 Electrical and Thermal Characteristics Table 3 shows DC electrical characteristics. Table 3. DC Electrical Characteristics1 Characteristic Symbol Min Max Unit Input high voltage, all inputs except CLKIN VIH 2.0 3.465 V Input low voltage VIL GND 0.8 V CLKIN input high voltage VIHC 2.4 3.465 V CLKIN input low voltage VILC GND 0.4 V Input leakage current, VIN = VDDH 2 IIN — 10 µA Hi-Z (off state) leakage current, VIN = VDDH 2 IOZ — 10 µA Signal low input current, VIL = 0.8 V IL — 1 µA Signal high input current, VIH = 2.0 V IH — 1 µA Output high voltage, IOH = –2 mA except XFC, UTOPIA mode, and open drain pins In UTOPIA mode: IOH = –8.0 mA PA[0-31] PB[4-31] PC[0-31] PD[4-31] VOH 2.4 — V In UTOPIA mode: IOL = 8.0 mA PA[0-31] PB[4-31] PC[0-31] PD[4-31] VOL — 0.5 V

MPC8260ACVVMIBB Reviews

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Margare*****acharyya

September 26, 2019

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September 3, 2019

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August 31, 2019

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March 11, 2019

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January 30, 2019

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