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MPC850DECZQ50BU

hot MPC850DECZQ50BU

MPC850DECZQ50BU

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Part Number MPC850DECZQ50BU
Manufacturer NXP
Description IC MPU MPC8XX 50MHZ 256BGA
Datasheet MPC850DECZQ50BU Datasheet
Package 256-BBGA
In Stock 1691 piece(s)
Unit Price $ 47.685 *
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MPC850DECZQ50BU

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MPC850DECZQ50BU Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microprocessors
Datasheet MPC850DECZQ50BU Datasheet
Package256-BBGA
SeriesMPC8xx
Core ProcessorMPC8xx
Number of Cores/Bus Width1 Core, 32-Bit
Speed50MHz
Co-Processors/DSPCommunications; CPM
RAM ControllersDRAM
Graphics AccelerationNo
Ethernet10 Mbps (1)
USBUSB 1.x (1)
Voltage - I/O3.3V
Operating Temperature-40°C ~ 95°C (TA)
Package / Case256-BBGA
Supplier Device Package256-PBGA (23x23)

MPC850DECZQ50BU Datasheet

Page 1

Page 2

© Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Semiconductor Technical Data This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A,B, and C of the MPC850 Family. 1 Overview The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. The MPC850, which includes support for Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications applications. It is provides functions similar to the MPC860, with system enhancements such as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM. In addition to a high-performance embedded MPC8xx core, the MPC850 integrates system functions, such as a versatile memory controller and a communications processor module (CPM) that incorporates a specialized, independent RISC communications processor (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded MPC8xx core. Document Number: MPC850EC Rev. 2, 07/2005 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Electrical and Thermal Characteristics . . . . . . . . . . . . 7 4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8 5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 9 6. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 39 8. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 41 9. Mechanical Data and Ordering Information . . . . . . . 63 10. Document Revision History . . . . . . . . . . . . . . . . . . . 68 MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications

Page 3

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor Overview The CPM of the MPC850 supports up to seven serial channels, as follows: • One or two serial communications controllers (SCCs). The SCCs support Ethernet, ATM (MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent mode of operation. • One USB channel • Two serial management controllers (SMCs) • One I2C port • One serial peripheral interface (SPI). Table 1 shows the functionality supported by the members of the MPC850 family. Additional documentation may be provided for parts listed in Table 1. Table 1. MPC850 Functionality Matrix Part Number of SCCs Supported Ethernet Support ATM Support USB Support Multi-channel HDLC Support Number of PCMCIA Slots Supported MPC850 1 Yes - Yes - 1 MPC850DE 2 Yes - Yes - 1 MPC850SR 2 Yes Yes Yes Yes 1 MPC850DSL 2 Yes Yes Yes No 1

Page 4

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3 Features 2 Features Figure 1 is a block diagram of the MPC850, showing its major components and the relationships among those components: Figure 1. MPC850 Microprocessor Block Diagram The following list summarizes the main features of the MPC850: • Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — Performs branch folding and branch prediction with conditional prefetch, but without conditional execution System Interface Unit Memory Controller Bus Interface Unit System Functions Real-Time Clock PCMCIA InterfaceBus Embedded 2-Kbyte I-Cache MMU 1-Kbyte D-Cache Data MMU Load/Store Instruction Bus Parallel I/O Baud Rate Generators Dual-Port RAM Interrupt Controller Four Timers 20 Virtual 2 Virtual 32-Bit RISC Communications Processor (CP) and Program ROM SCC2 USB SPI Timer Non-Multiplexed Serial Interface MPC8xx Core Instruction IDMA Channels Serial DMA and Channels Unified Bus Communications Processor Module Peripheral Bus SCC3 I2C — UTOPIA Ports (850SR & DSL) SMC1 SMC2 Time Slot Assigner TDMa

Page 5

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 4 Freescale Semiconductor Features — 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture) – Caches are two-way, set-associative – Physically addressed – Cache blocks can be updated with a 4-word line burst – Least-recently used (LRU) replacement algorithm – Lockable one-line granularity — Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and fully-associative instruction and data TLBs — MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups • Advanced on-chip emulation debug mode • Data bus dynamic bus sizing for 8, 16, and 32-bit buses — Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian memory systems — Twenty-six external address lines • Completely static design (0–80 MHz operation) • System integration unit (SIU) — Hardware bus monitor — Spurious interrupt monitor — Software watchdog — Periodic interrupt timer — Low-power stop mode — Clock synthesizer — Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG) • Memory controller (eight banks) — Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM (SDRAM), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), flash EPROM, etc. — Memory controller programmable to support most size and speed memory interfaces — Boot chip-select available at reset (options for 8, 16, or 32-bit memory) — Variable block sizes, 32 Kbytes to 256 Mbytes — Selectable write protection — On-chip bus arbiter supports one external bus master — Special features for burst mode support • General-purpose timers — Four 16-bit timers or two 32-bit timers

Page 6

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 5 Features — Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture • Interrupts — Eight external interrupt request (IRQ) lines — Twelve port pins with interrupt capability — Fifteen internal interrupt sources — Programmable priority among SCCs and USB — Programmable highest-priority request • Single socket PCMCIA-ATA interface — Master (socket) interface, release 2.1 compliant — Single PCMCIA socket — Supports eight memory or I/O windows • Communications processor module (CPM) — 32-bit, Harvard architecture, scalar RISC communications processor (CP) — Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD closes the receive buffer descriptor) — Supports continuous mode transmission and reception on all serial channels — Up to 8 Kbytes of dual-port RAM — Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four USB endpoints — Three parallel I/O registers with open-drain capability • Four independent baud-rate generators (BRGs) — Can be connected to any SCC, SMC, or USB — Allow changes during operation — Autobaud support option • Two SCCs (serial communications controllers) — Ethernet/IEEE 802.3, supporting full 10-Mbps operation — HDLC/SDLC™ (all channels supported at 2 Mbps) — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk® — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC))

Page 7

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 6 Freescale Semiconductor Features • QUICC multichannel controller (QMC) microcode features — Up to 64 independent communication channels on a single SCC — Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots — Supports either transparent or HDLC protocols for each channel — Independent TxBDs/Rx and event/interrupt reporting for each channel • One universal serial bus controller (USB) — Supports host controller and slave modes at 1.5 Mbps and 12 Mbps • Two serial management controllers (SMCs) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division-multiplexed (TDM) channel • One serial peripheral interface (SPI) — Supports master and slave modes — Supports multimaster operation on the same bus • One I2C® (interprocessor-integrated circuit) port — Supports master and slave modes — Supports multimaster environment • Time slot assigner — Allows SCCs and SMCs to run in multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame syncs, clocking — Allows dynamic changes — Can be internally connected to four serial channels (two SCCs and two SMCs) • Low-power support — Full high: all units fully powered at high clock frequency — Full low: all units fully powered at low clock frequency — Doze: core functional units disabled except time base, decrementer, PLL, memory controller, real-time clock, and CPM in low-power standby — Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for fast wake-up — Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt timer — Low-power stop: to provide lower power dissipation

Page 8

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 7 Electrical and Thermal Characteristics — Separate power supply input to operate internal logic at 2.2 V when operating at or below 25 MHz — Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V internal) operation • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints — Each watchpoint can generate a breakpoint internally • 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins. 3 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850. Table 2 provides the maximum ratings. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). Table 3 provides the package thermal characteristics for the MPC850. Table 2. Maximum Ratings (GND = 0V) Rating Symbol Value Unit Supply voltage VDDH -0.3 to 4.0 V VDDL -0.3 to 4.0 V KAPWR -0.3 to 4.0 V VDDSYN -0.3 to 4.0 V Input voltage 1 1 Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not be applied to its inputs). Vin GND-0.3 to VDDH + 2.5 V V Junction temperature 2 2 The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient temperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of the device. Tj 0 to 95 (standard) -40 to 95 (extended) °C Storage temperature range Tstg -55 to +150 °C

Page 9

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 8 Freescale Semiconductor Thermal Characteristics 4 Thermal Characteristics Table 3 shows the thermal characteristics for the MPC850. Table 4 provides power dissipation information. Table 5 provides the DC electrical characteristics for the MPC850. Table 3. Thermal Characteristics Characteristic Symbol Value Unit Thermal resistance for BGA 1 1 For more information on the design of thermal vias on multilayer boards and BGA layout considerations in general, refer to AN-1231/D, Plastic Ball Grid Array Application Note available from your local Freescale sales office. θJA 40 2 2 Assumes natural convection and a single layer board (no thermal vias). °C/W θJA 31 3 3 Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board temperature rise of 20°C above ambient. °C/W θJA 24 4 4 Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board temperature rise of 13°C above ambient. TJ = TA + (PD •θJA) PD = (VDD • IDD) + PI/O where: PI/O is the power dissipation on pins °C/W Thermal Resistance for BGA (junction-to-case) θJC 8 °C/W Table 4. Power Dissipation (PD) Characteristic Frequency (MHz) Typical 1 1 Typical power dissipation is measured at 3.3V Maximum 2 2 Maximum power dissipation is measured at 3.65 V Unit Power Dissipation All Revisions (1:1) Mode 33 TBD 515 mW 40 TBD 590 mW 50 TBD 725 mW Table 5. DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage at 40 MHz or less VDDH, VDDL, KAPWR, VDDSYN 3.0 3.6 V Operating voltage at 40 MHz or higher VDDH, VDDL, KAPWR, VDDSYN 3.135 3.465 V Input high voltage (address bus, data bus, EXTAL, EXTCLK, and all bus control/status signals) VIH 2.0 3.6 V Input high voltage (all general purpose I/O and peripheral pins) VIH 2.0 5.5 V

Page 10

MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 9 Power Considerations 5 Power Considerations The average chip-junction temperature, TJ, in °C can be obtained from the equation: TJ = TA + (PD • θJA)(1) where T A = Ambient temperature, °C Input low voltage VIL GND 0.8 V EXTAL, EXTCLK input high voltage VIHC 0.7*(VCC) VCC+0.3 V Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) Iin — 100 µA Input leakage current, Vin = 3.6V (Except TMS, TRST, DSCK and DSDI pins) IIn — 10 µA Input leakage current, Vin = 0V (Except TMS, TRST, DSCK and DSDI pins) IIn — 10 µA Input capacitance Cin — 20 pF Output high voltage, IOH = -2.0 mA, VDDH = 3.0V except XTAL, XFC, and open-drain pins VOH 2.4 — V Output low voltage CLKOUT 3 IOL = 3.2 mA 1 IOL = 5.3 mA 2 IOL = 7.0 mA PA[14]/USBOE, PA[12]/TXD2 IOL = 8.9 mA TS, TA, TEA, BI, BB, HRESET, SRESET VOL — 0.5 V 1 A[6:31], TSIZ0/REG, TSIZ1, D[0:31], DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1], IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, PA[15]/USBRXD, PA[13]/RXD2, PA[9]/L1TXDA/SMRXD2, PA[8]/L1RXDA/SMTXD2, PA[7]/CLK1/TIN1/L1RCLKA/BRGO1, PA[6]/CLK2/TOUT1/TIN3, PA[5]/CLK3/TIN2/L1TCLKA/BRGO2, PA[4]/CLK4/TOUT2/TIN4, PB[31]/SPISEL, PB[30]/SPICLK/TXD3, PB[29]/SPIMOSI /RXD3, PB[28]/SPIMISO/BRGO3, PB[27]/I2CSDA/BRGO1, PB[26]/I2CSCL/BRGO2, PB[25]/SMTXD1/TXD3, PB[24]/SMRXD1/RXD3, PB[23]/SMSYN1/SDACK1, PB[22]/SMSYN2/SDACK2, PB[19]/L1ST1, PB[18]/RTS2/L1ST2, PB[17]/L1ST3, PB[16]/L1RQa/L1ST4, PC[15]/DREQ0/L1ST5, PC[14]/DREQ1/RTS2/L1ST6, PC[13]/L1ST7/RTS3, PC[12]/L1RQa/L1ST8, PC[11]/USBRXP, PC[10]/TGATE1/USBRXN, PC[9]/CTS2, PC[8]/CD2/TGATE1, PC[7]/USBTXP, PC[6]/USBTXN, PC[5]/CTS3/L1TSYNCA/SDACK1, PC[4]/CD3/L1RSYNCA, PD[15], PD[14], PD[13], PD[12], PD[11], PD[10], PD[9], PD[8], PD[7], PD[6], PD[5], PD[4], PD[3] 2 BDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR, WE2/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1, OP2/MODCK1/STS, OP3/MODCK2/DSDO 3 The MPC850 IBIS model must be used to accurately model the behavior of the Clkout output driver for the full and half drive setting. Due to the nature of the Clkout output buffer, IOH and IOL for Clkout should be extracted from the IBIS model at any output voltage level. Table 5. DC Electrical Specifications (continued) Characteristic Symbol Min Max Unit

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