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PCA9543APW,118

PCA9543APW,118

PCA9543APW,118

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Part Number PCA9543APW,118
Manufacturer NXP
Description IC I2C SWITCH 2CH 14-TSSOP
Datasheet PCA9543APW,118 Datasheet
Package 14-TSSOP (0.173", 4.40mm Width)
In Stock 198 piece(s)
Unit Price $ 0.6885 *
Lead Time To be Confirmed
Estimated Delivery Time Jan 21 - Jan 26 (Choose Expedited Shipping)
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Part Number # PCA9543APW,118 (Interface - Specialized) is manufactured by NXP and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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PCA9543APW,118 Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Interface - Specialized
Datasheet PCA9543APW,118Datasheet
Package14-TSSOP (0.173", 4.40mm Width)
Series-
Applications2-Channel I2C Multiplexer
InterfaceI2C
Voltage - Supply2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Package / Case14-TSSOP (0.173", 4.40mm Width)
Supplier Device Package14-TSSOP
Mounting TypeSurface Mount

PCA9543APW,118 Datasheet

Page 1

Page 2

1. General description The PCA9543A/43B is a bidirectional translating switch, controlled by the I2C-bus. The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any individual SCx/SDx channels or combination of channels can be selected, determined by the contents of the programmable control register. Two interrupt inputs, INT0 and INT1, one for each of the downstream pairs, are provided. One interrupt output, INT, which acts as an AND of the two interrupt inputs, is provided. An active LOW reset input allows the PCA9543X to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected, as does the internal power-on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9543X. This allows the use of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. The PCA9543A and PCA9543B are identical except for the fixed portion of the slave address. 2. Features and benefits  1-of-2 bidirectional translating switches  I2C-bus interface logic; compatible with SMBus standards  2 active LOW interrupt inputs  Active LOW interrupt output  Active LOW reset input  2 address pins allowing up to 4 devices on the I2C-bus  Alternate address versions A and B allow up to a total of 12 devices on the bus for larger systems or to resolve address conflicts  Channel selection via I2C-bus, in any combination  Power-up with all switch channels deselected  Low Ron switches  Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses  No glitch on power-up  Supports hot insertion  Low standby current  Operating power supply voltage range of 2.3 V to 5.5 V PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset Rev. 8 — 3 April 2014 Product data sheet

Page 3

NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset 5 V tolerant inputs  0 Hz to 400 kHz clock frequency  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Packages offered: SO14, TSSOP14 3. Ordering information 3.1 Ordering options Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9543AD PCA9543A SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 PCA9543APW PA9543A TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 PCA9543BPW PA9543B TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature PCA9543AD PCA9543AD,112 SO14 Standard marking * IC’s tube - DSC bulk pack 1140 Tamb = 40 C to +85 C PCA9543AD,118 SO14 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9543APW PCA9543APW,112 TSSOP14 Standard marking * IC’s tube - DSC bulk pack 2400 Tamb = 40 C to +85 C PCA9543APW,118 TSSOP14 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9543BPW PCA9543BPW,118 TSSOP14 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 CPCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 2 of 28

Page 4

NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset4. Block diagram Fig 1. Block diagram of PCA9543A/43B SWITCH CONTROL LOGIC PCA9543A/43B POWER-ON RESET 002aab180 SC0 SC1 SD0 SD1 VSS VDD RESET I2C-BUS CONTROL INPUT FILTER SCL SDA A0 A1 INTERRUPT LOGIC INT0 to INT1 INTPCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 3 of 28

Page 5

NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset5. Pinning information 5.1 Pinning 5.2 Pin description Fig 2. Pin configuration for SO14 Fig 3. Pin configuration for TSSOP14 PCA9543AD A0 VDD A1 SDA RESET SCL INT0 INT SD0 SC1 SC0 SD1 VSS INT1 002aab178 1 2 3 4 5 6 7 8 10 9 12 11 14 13 VDD SDA SCL INT SC1 SD1 INT1 A0 A1 RESET INT0 SD0 SC0 VSS PCA9543APW PCA9543BPW 002aab179 1 2 3 4 5 6 7 8 10 9 12 11 14 13 Table 3. Pin description Symbol Pin Description A0 1 address input 0 A1 2 address input 1 RESET 3 active LOW reset input INT0 4 active LOW interrupt input 0 SD0 5 serial data 0 SC0 6 serial clock 0 VSS 7 supply ground INT1 8 active LOW interrupt input 1 SD1 9 serial data 1 SC1 10 serial clock 1 INT 11 active LOW interrupt output SCL 12 serial clock line SDA 13 serial data line VDD 14 supply voltagePCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 4 of 28

Page 6

NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset6. Functional description Refer to Figure 1 “Block diagram of PCA9543A/43B”. 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9543A/43B is shown in Figure 4. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. The PCA9543B is an alternate address version, if needed for larger systems or to resolve address conflicts. The data sheet will reference the PCA9543A, but the PCA9543B functions identically except for the slave address. 6.1.1 Address maps Fig 4. Slave address PCA9543A Fig 5. Slave address PCA9543B 002aab169 1 1 1 0 0 A1 A0 R/W fixed hardware selectable 002aab799 1 1 1 1 0 A1 A0 R/W fixed hardware selectable Table 4. PCA9543A address map Pin connectivity Address of PCA9543A Address byte value 7-bit hexadecimal address without R/W A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read VSS VSS 1 1 1 0 0 0 0 - E0h E1h 70h VSS VDD 1 1 1 0 0 0 1 - E2h E3h 71h VDD VSS 1 1 1 0 0 1 0 - E4h E5h 72h VDD VDD 1 1 1 0 0 1 1 - E6h E7h 73hPCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 5 of 28

Page 7

NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9543A/43B, which will be stored in the control register. If multiple bytes are received by the PCA9543A/43B, it will save the last byte received. This register can be written and read via the I2C-bus. 6.2.1 Control register definition One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9543A/43B has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Bits INT0, INT1, D6 and D7 are all writable, but will read the chip status. INT0 and INT1 indicate the state of the corresponding interrupt input. D7 and D6 always read 0. See Section 6.2.2. Table 5. PCA9543B address map Pin connectivity Address of PCA9543B Address byte value 7-bit hexadecimal address without R/W A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read VSS VSS 1 1 1 1 0 0 0 - F0h F1h 78h VSS VDD 1 1 1 1 0 0 1 - F2h F3h 79h VDD VSS 1 1 1 1 0 1 0 - F4h F5h 7Ah VDD VDD 1 1 1 1 0 1 1 - F6h F7h 7Bh Fig 6. Control register 002aab181 X X INT 1 INT 0 X X B1 B0 channel selection bits (read/write) 7 6 5 4 3 2 1 0 interrupt bits (read/write), but reads back chip status; bit 6 and bit 7 always read 0 channel 0 channel 1 INT0 INT1PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 6 of 28

Page 8

NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance. 6.2.2 Interrupt handling The PCA9543A/43B provides 2 interrupt inputs, one for each channel, and one open-drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9543A/43B and the interrupt output will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the control register. Bit 4 and bit 5 of the control register corresponds to the INT0 and INT1 inputs of the PCA9543A/43B, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9543A/43B and read the contents of the control register to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9543A/43B to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general-purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VDD through a pull-up resistor. Remark: Two interrupts can be active at the same time. D6 and D7 always read 0. 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A/43B will reset its registers and I2C-bus state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor. Table 6. Control register: Write — channel selection; Read — channel status D7 D6 INT1 INT0 D3 D2 B1 B0 Command X X X X X X X 0 channel 0 disabled 1 channel 0 enabled X X X X X X 0 X channel 1 disabled 1 channel 1 enabled 0 0 0 0 0 0 0 0 no channel selected; power-up/reset default state Table 7. Control register: Read — interrupt 7 6 INT1 INT0 3 2 B1 B0 Command 0 0 X 0 X X X X no interrupt on channel 0 1 interrupt on channel 0 0 0 0 X X X X X no interrupt on channel 1 1 interrupt on channel 1PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 7 of 28

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NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9543A/43B in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9543A/43B registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device. 6.5 Voltage translation The pass gate transistors of the PCA9543A/43B are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another. Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 11 “Static characteristics” of this data sheet). In order for the PCA9543A/43B to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9543A/43B supply voltage is 3.5 V or lower, so the PCA9543A/43B supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 14). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches. (1) maximum (2) typical (3) minimum Fig 7. Pass gate voltage versus supply voltage VDD (V) 2.0 5.54.53.0 4.0 002aaa964 3.0 2.0 4.0 5.0 Vo(sw) (V) 1.0 3.5 5.02.5 (1) (2) (3)PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 8 of 28

Page 10

NXP Semiconductors PCA9543A/43B 2-channel I2C-bus switch with interrupt logic and reset7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8). 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9). Fig 8. Bit transfer mba607 data line stable; data valid change of data allowed SDA SCL Fig 9. Definition of START and STOP conditions mba608 SDA SCL P STOP condition S START conditionPCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 3 April 2014 9 of 28

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