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X9110TV14IZ-2.7T1

hotX9110TV14IZ-2.7T1

X9110TV14IZ-2.7T1

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Part Number X9110TV14IZ-2.7T1
Manufacturer Renesas Electronics America
Description IC XDCP 1024-TAP 100K 14-TSSOP
Datasheet X9110TV14IZ-2.7T1 Datasheet
Package 14-TSSOP (0.173", 4.40mm Width)
In Stock 3,816 piece(s)
Unit Price $ 6.4000 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jan 30 - Feb 4 (Choose Expedited Shipping)
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Part Number # X9110TV14IZ-2.7T1 (Data Acquisition - Digital Potentiometers) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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X9110TV14IZ-2.7T1 Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital Potentiometers
Datasheet X9110TV14IZ-2.7T1Datasheet
Package14-TSSOP (0.173", 4.40mm Width)
SeriesXDCP™
TaperLinear
ConfigurationPotentiometer
Number of Circuits1
Number of Taps1024
Resistance (Ohms)100k
InterfaceSPI
Memory TypeNon-Volatile
Voltage - Supply2.7 V ~ 5.5 V
FeaturesSelectable Address
Tolerance±20%
Temperature Coefficient (Typ)±300 ppm/°C
Resistance - Wiper (Ohms) (Typ)150
Operating Temperature-40°C ~ 85°C
Package / Case14-TSSOP (0.173", 4.40mm Width)
Supplier Device Package14-TSSOP

X9110TV14IZ-2.7T1 Datasheet

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FN8158 Rev 5.00 October 28, 2016 X9110 Dual Supply/Low Power/1024-Tap/SPI Bus, Single Digitally-Controlled (XDCP™) Potentiometer DATASHEETThe X9110 integrates a Single Digitally Controlled Potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile data registers that can be directly written to, and read by, the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Related Literature • For a full list of related documents, visit our website - X9110 product page Features • 1024 resistor taps – 10-bit resolution • SPI serial interface for write, read, and transfer operations of the potentiometer • Wiper resistance, 40Ωtypical at 5V • Four nonvolatile data registers • Nonvolatile storage of multiple wiper positions • Power-on recall, loads saved wiper position on power-up • Standby current <5µA maximum • System VCC: 2.7V to 5.5V operation • Analog V+/V-: -5V to +5V • 100kΩend-to-end resistance • 100 year data retention • Endurance: 100,000 data changes per bit per register • 14 Ld TSSOP • Dual supply version of the X9111 • Low power CMOS • Pb-free (RoHS compliant) FIGURE 1. FUNCTIONAL DIAGRAM RH RL BUS RW INTERFACE CONTROL POT VCC VSS SPI BUS ADDRESS DATA STATUS WRITE READ WIPER 1024-TAPSTRANSFER NC NC 100kΩPOWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3)CONTROL INTERFACE V+ V- ANDFN8158 Rev 5.00 Page 1 of 18 October 28, 2016

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X9110Applications Circuit Level Applications • Vary the gain of a voltage amplifier • Provide programmable DC reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the DC biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits System Level Applications • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems Ordering Information PART NUMBER (Notes 2, 3) PART MARKING VCC LIMITS (V) POTENTIOMETER RANGE (kΩ) TEMP RANGE (°C) PACKAGE (RoHS COMPLIANT) PKG. DWG. # X9110TV14Z (Note 1) X9110 TVZ 5 ±10 100 0 to +70 14 Ld TSSOP M14.173 X9110TV14IZ X9110 TVZI -40 to +85 14 Ld TSSOP M14.173 X9110TV14Z-2.7 X9110 TVZF 2.7 to 5.5 0 to +70 14 Ld TSSOP M14.173 X9110TV14IZ-2.7 (Note 1) X9110 TVZG -40 to +85 14 Ld TSSOP M14.173 NOTES: 1. Add “T1” suffix for 2.5k unit tape and reel option. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see product information page for X9110. For more information on MSL, see tech brief TB363.FN8158 Rev 5.00 Page 2 of 18 October 28, 2016

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X9110Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out on the falling edge of the serial clock. SERIAL INPUT (SI) SI is the serial data input pin. All opcodes, byte addresses and data to be written to the potentiometer pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9110. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. Detailed Functional Diagram FIGURE 2. DETAILED FUNCTIONAL DIAGRAM CS SCK A0 SO SI HOLD WP INTERFACE AND CONTROL CIRCUITRY V- V+VCC VSS DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW 1024-TAPS 100kΩ CONTROL POWER ON RECALL Pin Configuration X9110 14 LD TSSOP TOP VIEW Pin Descriptions PIN (TSSOP) SYMBOL FUNCTION 1 V+ Analog Supply Voltage 2 SO Serial Data Output 3 A0 Device Address 4 SCK Serial Clock 5 WP Hardware Write Protect 6 SI Serial Data Input 7 VSS System Ground 8 V- Analog Supply Voltage 9 CS Chip Select 10 HOLD Device Select. Pause the Serial Bus VCC RL VSS 1 2 3 4 5 6 7 8 14 13 12 11 10 9 A0 RWSCK CS RH SO V+ SI HOLDWP V- 11 RW Wiper Terminal of the Potentiometer 12 RH High Terminal of the Potentiometer 13 RL Low Terminal of the Potentiometer 14 VCC System Supply Voltage Pin Descriptions (Continued) PIN (TSSOP) SYMBOL FUNCTIONFN8158 Rev 5.00 Page 3 of 18 October 28, 2016

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X9110If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A0) The address input is used to set the 8-bit slave address. A match in the slave address serial data stream A0 must be made with the address input (A0) in order to initiate communication with the X9110. CHIP SELECT (CS) When CS is HIGH, the X9110 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9110, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. ANALOG SUPPLY VOLTAGES (V+ AND V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Principles of Operation Device Description SERIAL INTERFACE The X9110 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked-in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9110 is comprised of a resistor array (Figure 3). The array contains the equivalent of 1023 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). SERIAL DATA PATH FROM INTERFACE REGISTER 0 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER RH RL R W 10 10 C O U N T E R D E C O D E WIPER (WCR) (DR0) CIRCUITRY REGISTER 1 (DR1) REGISTER 2 (DR2) REGISTER 3 (DR3) FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM If WCR = 000[HEX] then RW = RL If WCR = 3FF[HEX] then RW = RH R FN8158 Rev 5.00 Page 4 of 18 October 28, 2016

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X9110At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within the individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. WIPER COUNTER REGISTER (WCR) The X9110 contains a Wiper Counter Register (see Table 1) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The content of the WCR can be altered in one of three ways: (1) it may be written directly by the host via the write Wiper Counter Register instruction (serial load); (2) it may be written indirectly by transferring the content of one of four associated Data Registers via the XFR Data Register; (3) it is loaded with the content of its data register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its content is lost when the X9110 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR) The potentiometer has four 10-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. DR[9:0] is used to store one of the 1024 wiper position (0~1023) (see Table 2). STATUS REGISTER (SR) This 1-bit status register is used to store the system status (see Table 3). WIP: Write In Progress status bit, read only. • When WIP = 1, indicates that high-voltage write cycle is in progress. • When WIP = 0, indicates that no high-voltage write cycle is in progress. TABLE 3. STATUS REGISTER, SR (1-BIT) TABLE 4. IDENTIFICATION BYTE FORMAT TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used to store the current wiper position (Volatile, V) WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V V V (MSB) (LSB) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Nonvolatile, NV) BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NV NV NV NV NV NV NV NV NV NV (MSB) (LSB) WIP (LSB) ID3 ID2 ID1 ID0 0 0 A0 R/W 0 1 0 1 (MSB) (LSB) DEVICE TYPE IDENTIFIER INTERNAL SLAVE ADDRESS READ OR WRITE BITFN8158 Rev 5.00 Page 5 of 18 October 28, 2016

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X9110TABLE 5. INSTRUCTION BYTE FORMAT Device Instructions Identification Byte (ID and A) The first byte sent to the X9110 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9110; this is fixed as 0101[B] (refer to Table 4). The A0 bit in the ID byte is the internal slave address. The physical device address is defined by the state of the A0 input pin. The slave address is externally specified by the user. The X9110 compares the serial data stream with the address input state; a successful compare of the address bit is required for the X9110 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A0 input can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is used to set the device to either read or write mode. Instruction Byte and Register Selection The next byte sent to the X9110 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 5. Five of the seven instructions are four bytes in length. These instructions are: 1. Read Wiper Counter Register – This register reads the current wiper position of the selected pot. 2. Write Wiper Counter Register – This register changes current wiper position of the selected pot. 3. Read Data Register – This register reads the contents of the selected data register. 4. Write Data Register – This register writes a new value to the selected data register. 5. Read Status – This command returns the contents of the WIP bit, which indicates if the internal write cycle is in progress. The basic sequence of the four byte instructions is illustrated in Figure 5 on page 7. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. The Read Status Register instruction is the only unique format (see Figure 6 on page 7). Two instructions require a two-byte sequence to complete (see Figure 4 on page 7). These instructions transfer data between the host and the X9110; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: 1. XFR Data Register to Wiper Counter Register – This register transfers the content of one specified Data Register to the associated Wiper Counter Register. 2. XFR Wiper Counter Register to Data Register – This register transfers the content of the specified Wiper Counter Register to the specified associated Data Register. See “Instruction Format” on page 8 for more details. Write in Process (WIP bit) The content of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process (WIP) bit. The WIP bit is read with a Read Status command (see Figure 6). Power-Up and Power-Down Requirements At all times, the V+ voltage must be greater than or equal to the voltage at RH or RL, and the voltage at RH or RL must be greater than or equal to the voltage at V-. During power-up and power-down, VCC, V+, and V- must reach their final values within 1ms of each other. I2 I1 I0 0 RB RA 0 0 (MSB) (LSB) INSTRUCTION OPCODE REGISTER SELECTION RB RA REGISTER 0 0 1 1 0 1 0 1 DR0 DR1 DR2 DR3FN8158 Rev 5.00 Page 6 of 18 October 28, 2016

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X9110ID3 ID2 ID1 ID0 0 0 A0 I2 I1 I0 RB RA SCK SI CS 0 1 0 1 R/W DEVICE ID INTERNAL INSTRUCTION OPCODEADDRESS REGISTER 0 0 0 0 ADDRESS 0 0 0 FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE ID3 ID2 ID1 ID0 0 A0 R/W I2 0 0 SCK SI 0 0 X X 0 0 X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 CS I1 I0 0 RB RA 0 1 0 1 0 X X X DEVICE ID INTERNAL ADDRESS INSTRUCTION OPCODE REGISTER ADDRESS WIPER POSITION 0 FIGURE 5. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) ID3 ID2 ID1 ID0 0 A0 R/W I2 0 0 SCK SI 1 0 X X 0 0 X X X WIP CS I1 I0 0 RB RA 0 1 0 1 0 X X X DEVICE ID INTERNAL ADDRESS INSTRUCTION OPCODE REGISTER ADDRESS STATUS BIT X X 0 0 0 0 0 0 0 0 0 FIGURE 6. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)FN8158 Rev 5.00 Page 7 of 18 October 28, 2016

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X9110Instruction Format TABLE 6. INSTRUCTION SET INSTRUCTION INSTRUCTION SET OPERATIONR/W I2 I1 I0 0 RB RA 0 0 Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter Register Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register pointed to RB-RA Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to RB-RA XFR Data Register to Wiper Counter Register 1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by RB-RA to the Wiper Counter Register XFR Wiper Counter Register to Data Register 0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register to the Data Register pointed to by RB-RA Read Status (WIP bit) 1 0 1 0 0 0 0 0 1 Read the status of the internal write cycle, by checking the WIP bit (read status register). NOTE: 1/0 = data is one or zero Read Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Wiper Position (Sent by X9110 on SO) Wiper Position (sent by X9110 on SO) CS Rising Edge 0 1 0 1 0 0 A0 R / W = 1 1 0 0 0 0 0 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 Write Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Wiper Position (Sent by Master on SI) Wiper Position (Sent by Master on SI) CS Rising Edge 0 1 0 1 0 0 A0 R / W = 0 1 0 1 0 0 0 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 Read Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Wiper Position (Sent by X9110 on SO) Wiper Position (sent by X9110 on SO) CS Rising Edge 0 1 0 1 0 0 A0 R / W = 1 1 0 1 0 RB RA 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 FN8158 Rev 5.00 Page 8 of 18 October 28, 2016

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X9110Write Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address Wiper Position or Data (Sent by Master on SI) Wiper Position or Data (Sent by Master on SI) CS Rising Edge H IG H -V O LT A G E W R IT E C YC LE 0 1 0 1 0 0 A0 R / W = 0 1 1 0 0 RB RA 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 Transfer Data Register (DR) to Wiper Counter Register (WCR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address CS Rising Edge 0 1 0 1 0 0 A0 R / W = 1 1 1 0 0 RB RA 0 0 Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Address CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0 0 A0 R / W = 0 1 1 1 0 RB RA 0 0 Read Status Register (SR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode Register Addresses Status Data (Sent by Slave on SO) Status Data (Sent by Slave on SO) CS Rising Edge 0 1 0 1 0 0 A0 R / W = 1 0 1 0 X 0 0 0 1 X X X X X X X X 0 0 0 0 0 0 0 WIP NOTES: 4. “A0”: stands for the device address sent by the master. 5. WCRx refers to wiper position data in the Wiper Counter Register 6. “X”: Do not care.FN8158 Rev 5.00 Page 9 of 18 October 28, 2016

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