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XC7K325T-3FFG900E

hotXC7K325T-3FFG900E

XC7K325T-3FFG900E

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Part Number XC7K325T-3FFG900E
Manufacturer Xilinx Inc.
Description IC FPGA 500 I/O 900FCBGA
Datasheet XC7K325T-3FFG900E Datasheet
Package 900-BBGA, FCBGA
In Stock 369 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 29 - Nov 3 (Choose Expedited Shipping)
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Part Number # XC7K325T-3FFG900E (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Xilinx Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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XC7K325T-3FFG900E Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet XC7K325T-3FFG900EDatasheet
Package900-BBGA, FCBGA
SeriesKintex?-7
Number of LABs/CLBs25475
Number of Logic Elements/Cells326080
Total RAM Bits16404480
Number of I/O500
Number of Gates-
Voltage - Supply0.97 V ~ 1.03 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 100°C (TJ)
Package / Case900-BBGA, FCBGA
Supplier Device Package900-FCBGA (31x31)

XC7K325T-3FFG900E Datasheet

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DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 1 © 2011–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Introduction Kintex®-7 FPGAs are available in -3, -2, -1, -1L, and -2L speed grades, with -3 having the highest performance. The -2L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -2 devices. The -2L industrial (I) temperature devices operate only at VCCINT = 0.95V. The -2L extended (E) temperature devices can operate at either VCCINT = 0.9V or 1.0V. The -2LE devices when operated at VCCINT = 1.0V, and the -2LI devices when operated at VCCINT = 0.95V, have the same speed specifications as the -2 speed grade, except where noted. When the -2LE devices are operated at VCCINT = 0.9V, the speed specifications, static power, and dynamic power are reduced. The -1L military (M) temperature devices have the same speed specifications as the -1 military temperature devices and are screened for lower maximum static power. Kintex-7 FPGA DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except for the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade military temperature device are the same as for a -1 speed grade commercial temperature device). However, only selected speed grades and/or devices are available in each temperature range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Available device and package combinations can be found in: • 7 Series FPGAs Overview (DS180) • Defense-Grade 7 Series FPGAs Overview (DS185) This Kintex-7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/documentation. DC Characteristics Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 Product Specification Table 1: Absolute Maximum Ratings (1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage –0.5 1.1 V VCCAUX Auxiliary supply voltage –0.5 2.0 V VCCBRAM Supply voltage for the block RAM memories –0.5 1.1 V VCCO Output drivers supply voltage for HR I/O banks –0.5 3.6 V Output drivers supply voltage for HP I/O banks –0.5 2.0 V VCCAUX_IO Auxiliary supply voltage –0.5 2.06 V VREF Input reference voltage –0.5 2.0 V VIN (2)(3)(4) I/O input voltage for HR I/O banks –0.40 VCCO + 0.55 V I/O input voltage for HP I/O banks –0.55 VCCO + 0.55 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(5) –0.40 2.625 V VCCBATT Key memory battery backup supply –0.5 2.0 V Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 2 GTX Transceiver VMGTAVCC Analog supply voltage for the GTX transmitter and receiver circuits –0.5 1.1 V VMGTAVTT Analog supply voltage for the GTX transmitter and receiver termination circuits –0.5 1.32 V VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers –0.5 1.935 V VMGTREFCLK GTX transceiver reference clock absolute input voltage –0.5 1.32 V VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTX transceiver column –0.5 1.32 V VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating – 14 mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 12 mA IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND – 6.5 mA IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating – 14 mA IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT – 12 mA XADC VCCADC XADC supply relative to GNDADC –0.5 2.0 V VREFP XADC reference input relative to GNDADC –0.5 2.0 V Temperature TSTG Storage temperature (ambient) –65 150 °C TSOL Maximum soldering temperature for Pb/Sn component bodies (6) – +220 °C Maximum soldering temperature for Pb-free component bodies (6) – +260 °C Tj Maximum junction temperature (6) – +125 °C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. The lower absolute voltage specification always applies. 3. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471). 4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5. 5. See Table 10 for TMDS_33 specifications. 6. For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475). Table 2: Recommended Operating Conditions (1)(2) Symbol Description Min Typ Max Units FPGA Logic VCCINT (3) For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: internal supply voltage 0.97 1.00 1.03 V For -2LE (0.9V) devices: internal supply voltage 0.87 0.90 0.93 V For -2LI (0.95V) devices: internal supply voltage 0.93 0.95 0.97 V VCCBRAM (3) For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: block RAM supply voltage 0.97 1.00 1.03 V For -2LE (0.9V) devices: block RAM supply voltage 0.87 0.90 1.03 V For -2LI (0.95V) devices: block RAM supply voltage 0.93 0.95 0.97 V VCCAUX Auxiliary supply voltage 1.71 1.80 1.89 V VCCO (4)(5) Supply voltage for HR I/O banks 1.14 – 3.465 V Supply voltage for HP I/O banks 1.14 – 1.89 V Table 1: Absolute Maximum Ratings (1) (Cont’d) Symbol Description Min Max Units Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 3 VCCAUX_IO (6) Auxiliary supply voltage when set to 1.8V 1.71 1.80 1.89 V Auxiliary supply voltage when set to 2.0V 1.94 2.00 2.06 V VIN (7) I/O input voltage –0.20 – VCCO + 0.2 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(8) –0.20 – 2.625 V IIN (9) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. – – 10 mA VCCBATT (10) Battery voltage 1.0 – 1.89 V GTX Transceiver VMGTAVCC (11) Analog supply voltage for the GTX transceiver QPLL frequency range ≤ 10.3125 GHz(12)(13) 0.97 1.0 1.08 V Analog supply voltage for the GTX transceiver QPLL frequency range > 10.3125 GHz 1.02 1.05 1.08 V VMGTAVTT (11) Analog supply voltage for the GTX transmitter and receiver termination circuits 1.17 1.2 1.23 V VMGTVCCAUX (11) Auxiliary analog QPLL voltage supply for the transceivers 1.75 1.80 1.85 V VMGTAVTTRCAL (11) Analog supply voltage for the resistor calibration circuit of the GTX transceiver column 1.17 1.2 1.23 V XADC VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V VREFP Externally supplied reference voltage 1.20 1.25 1.30 V Temperature Tj Junction temperature operating range for commercial (C) temperature devices 0 – 85 °C Junction temperature operating range for extended (E) temperature devices 0 – 100 °C Junction temperature operating range for industrial (I) temperature devices –40 – 100 °C Junction temperature operating range for military (M) temperature devices –55 – 125 °C Notes: 1. All voltages are relative to ground. 2. For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide (UG483). 3. VCCINT and VCCBRAM should be connected to the same supply. 4. Configuration data is retained even if VCCO drops to 0V. 5. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), and 3.3V (HR I/O only) at ±5%. 6. For more information, refer to the VCCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471). 7. The lower absolute voltage specification always applies. 8. See Table 10 for TMDS_33 specifications. 9. A total of 200 mA per bank should not be exceeded. 10. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. 11. Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476). 12. For data rates ≤ 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption. 13. For lower power consumption, VMGTAVCC should be 1.0V ±3% over the entire CPLL frequency range. Table 2: Recommended Operating Conditions (1)(2) (Cont’d) Symbol Description Min Typ Max Units Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 4 Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 – – V IREF VREF leakage current per pin – – 15 µA IL Input or output leakage current per pin (sample-tested) – – 15 µA CIN (2) Die input capacitance at the pad – – 8 pF IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V 90 – 330 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V 68 – 250 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V 34 – 220 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V 23 – 150 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V 12 – 120 µA IRPD Pad pull-down (when selected) @ VIN = 3.3V 68 – 330 µA Pad pull-down (when selected) @ VIN = 1.8V 45 – 180 µA ICCADC Analog supply current, analog circuits in powered up state – – 25 mA IBATT (3) Battery supply current – – 150 nA RIN_TERM (4) Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40) 28 40 55 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50) 35 50 65 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60) 44 60 83 Ω n Temperature diode ideality factor – 1.010 – – r Temperature diode series resistance – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. This measurement represents the die capacitance at the pad, not including the package. 3. Maximum value specified for worst case process at 25°C. 4. Termination resistance to a VCCO/2 level. Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks (1)(2) AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C VCCO + 0.55 100 –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 VCCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.20 VCCO + 0.85 1.02 –0.85 0.09 VCCO + 0.90 0.49 –0.90 0.04 Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 5 VCCO + 0.95 0.24 –0.95 0.02 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks (1)(2) AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C VCCO + 0.55 100 –0.55 100 VCCO + 0.60 50.0 (3) –0.60 50.0(3) VCCO + 0.65 50.0 (3) –0.65 50.0(3) VCCO + 0.70 47.0 –0.70 50.0 (3) VCCO + 0.75 21.2 –0.75 50.0 (3) VCCO + 0.80 9.71 –0.80 50.0 (3) VCCO + 0.85 4.51 –0.85 28.4 VCCO + 0.90 2.12 –0.90 12.7 VCCO + 0.95 1.01 –0.95 5.79 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. 3. For UI lasting less than 20 µs. Table 6: Typical Quiescent Supply Current Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LM -1M -2LI -2LE ICCINTQ Quiescent VCCINT supply current XC7K70T 241 241 241 N/A N/A N/A 187 mA XC7K160T 474 474 474 N/A N/A 271 368 mA XC7K325T 810 810 810 N/A N/A 463 629 mA XC7K355T 993 993 993 N/A N/A 568 771 mA XC7K410T 1080 1080 1080 N/A N/A 618 838 mA XC7K420T 1313 1313 1313 N/A N/A 751 1019 mA XC7K480T 1313 1313 1313 N/A N/A 751 1019 mA XQ7K325T N/A 810 810 810 810 463 629 mA XQ7K410T N/A 1080 1080 N/A 1080 618 838 mA Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks (1)(2) (Cont’d) AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 6 ICCOQ Quiescent VCCO supply current XC7K70T 1 1 1 N/A N/A N/A 1 mA XC7K160T 1 1 1 N/A N/A 1 1 mA XC7K325T 1 1 1 N/A N/A 1 1 mA XC7K355T 1 1 1 N/A N/A 1 1 mA XC7K410T 1 1 1 N/A N/A 1 1 mA XC7K420T 1 1 1 N/A N/A 1 1 mA XC7K480T 1 1 1 N/A N/A 1 1 mA XQ7K325T N/A 1 1 1 1 1 1 mA XQ7K410T N/A 1 1 N/A 1 1 1 mA ICCAUXQ Quiescent VCCAUX supply current XC7K70T 21 21 21 N/A N/A N/A 21 mA XC7K160T 40 40 40 N/A N/A 36 40 mA XC7K325T 68 68 68 N/A N/A 61 68 mA XC7K355T 75 75 75 N/A N/A 67 75 mA XC7K410T 85 85 85 N/A N/A 76 85 mA XC7K420T 99 99 99 N/A N/A 89 99 mA XC7K480T 99 99 99 N/A N/A 89 99 mA XQ7K325T N/A 68 68 68 68 68 68 mA XQ7K410T N/A 85 85 N/A 85 85 85 mA ICCAUX_IOQ Quiescent VCCAUX_IO supply current XC7K70T N/A N/A N/A N/A N/A N/A N/A mA XC7K160T 2 2 2 N/A N/A 1 2 mA XC7K325T 2 2 2 N/A N/A 1 2 mA XC7K355T N/A N/A N/A N/A N/A N/A N/A mA XC7K410T 2 2 2 N/A N/A 1 2 mA XC7K420T N/A N/A N/A N/A N/A N/A N/A mA XC7K480T N/A N/A N/A N/A N/A N/A N/A mA XQ7K325T N/A 2 2 2 2 2 2 mA XQ7K410T N/A 2 2 N/A 2 2 2 mA Table 6: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LM -1M -2LI -2LE Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 7 Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: • The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. • The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power- up and power-down. • When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down. • When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down. There is no recommended sequence for supplies not shown. Table 7 shows the minimum current, in addition to ICCQ, that are required by Kintex-7 devices for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. ICCBRAMQ Quiescent VCCBRAM supply current XC7K70T 6 6 6 N/A N/A N/A 6 mA XC7K160T 14 14 14 N/A N/A 8 14 mA XC7K325T 19 19 19 N/A N/A 10 19 mA XC7K355T 31 31 31 N/A N/A 17 31 mA XC7K410T 34 34 34 N/A N/A 19 34 mA XC7K420T 41 41 41 N/A N/A 23 41 mA XC7K480T 41 41 41 N/A N/A 23 41 mA XQ7K325T N/A 19 19 19 19 19 19 mA XQ7K410T N/A 34 34 N/A 34 34 34 mA Notes: 1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO resources. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions other than those specified. Table 6: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LM -1M -2LI -2LE Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 8 Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate current drain on these supplies. DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: Power-On Current for Kintex-7 Devices Device ICCINTMIN ICCAUXMIN ICCOMIN ICCAUX_IOMIN ICCBRAMMIN Units XC7K70T ICCINTQ + 450 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 40 mA XC7K160T ICCINTQ + 550 ICCAUXQ + 50 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 40 mA XC7K325T ICCINTQ + 600 ICCAUXQ + 80 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 40 mA XC7K355T ICCINTQ + 1450 ICCAUXQ + 109 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 81 mA XC7K410T ICCINTQ + 1500 ICCAUXQ + 125 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 90 mA XC7K420T ICCINTQ + 2200 ICCAUXQ + 180 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 108 mA XC7K480T ICCINTQ + 2200 ICCAUXQ + 180 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 108 mA XQ7K325T ICCINTQ + 600 ICCAUXQ + 80 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 40 mA XQ7K410T ICCINTQ + 1500 ICCAUXQ + 125 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 90 mA Table 8: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms TVCCAUX_IO Ramp time from GND to 90% of VCCAUX_IO 0.2 50 ms TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms TVCCO2VCCAUX Allowed time per power cycle for VCCO – VCCAUX > 2.625V TJ = 125°C (1) – 300 msTJ = 100°C (1) – 500 TJ = 85°C (1) – 800 TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms TMGTVCCAUX Ramp time from GND to 90% of VMGTVCCAUX 0.2 50 ms Notes: 1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. Table 9: SelectIO DC Input and Output Levels (1)(2) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8 –8 HSTL_I_12 –0.300 VREF – 0.080 VREF + 0.080 VCCO + 0.300 25% VCCO 75% VCCO 6.3 –6.3 HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8 –8 HSTL_II –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16 –16 HSTL_II_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16 –16 Send Feedback

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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 www.xilinx.com Product Specification 9 HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1 LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 3 Note 3 LVCMOS15, LVDCI_15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 25% VCCO 75% VCCO Note 4 Note 4 LVCMOS18, LVDCI_18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5 LVCMOS25 –0.300 0.700 1.700 VCCO + 0.300 0.400 VCCO – 0.400 Note 6 Note 6 LVCMOS33 –0.300 0.800 2.000 3.450 0.400 VCCO – 0.400 Note 6 Note 6 LVTTL –0.300 0.800 2.000 3.450 0.400 2.400 Note 7 Note 7 MOBILE_DDR –0.300 20% VCCO 80% VCCO VCCO + 0.300 10% VCCO 90% VCCO 0.1 –0.1 PCI33_3 –0.400 30% VCCO 50% VCCO VCCO + 0.500 10% VCCO 90% VCCO 1.5 –0.5 SSTL12 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 14.25 –14.25 SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 13.0 –13.0 SSTL135_R –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.9 –8.9 SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 13.0 –13.0 SSTL15_R –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 8.9 –8.9 SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470 8 –8 SSTL18_II –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600 13.4 –13.4 Notes: 1. Tested according to relevant specifications. 2. 3.3V and 2.5V standards are only supported in HR I/O banks. 3. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks. 4. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks. 5. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks. 6. Supported drive strengths of 4, 8, 12, or 16 mA 7. Supported drive strengths of 4, 8, 12, 16, or 24 mA 8. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471). Table 9: SelectIO DC Input and Output Levels (1)(2) (Cont’d) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA Send Feedback

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