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ZL2006ALNFT

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ZL2006ALNFT

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Part Number ZL2006ALNFT
Manufacturer Intersil
Description IC REG CTRLR BUCK PMBUS 36QFN
Datasheet ZL2006ALNFT Datasheet
Package 36-VFQFN Exposed Pad
In Stock 23,386 piece(s)
Unit Price $ 4.2160 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 26 - Oct 1 (Choose Expedited Shipping)
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Part Number # ZL2006ALNFT (PMIC - Voltage Regulators - DC DC Switching Controllers) is manufactured by Intersil and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ZL2006ALNFT Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - DC DC Switching Controllers
Datasheet ZL2006ALNFTDatasheet
Package36-VFQFN Exposed Pad
SeriesDigital-DC?
Output TypeTransistor Driver
FunctionStep-Down
Output ConfigurationPositive
TopologyBuck
Number of Outputs1
Output Phases1
Voltage - Supply (Vcc/Vdd)3 V ~ 5.5 V
Frequency - Switching200kHz ~ 1.4MHz
Duty Cycle (Max)95%
Synchronous RectifierYes
Clock SyncYes
Serial InterfacesI2C, PMBus, SMBus
Control FeaturesCurrent Limit, Enable, Soft Start, Tracking
Operating Temperature-40°C ~ 85°C (TA)
Package / Case36-VFQFN Exposed Pad
Supplier Device Package36-QFN (6x6)

ZL2006ALNFT Datasheet

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ZL2006 Adaptive Digital DC-DC Controller with Drivers and Current Sharing FN6850 Rev. 1.00 Page 1 of 45 December 15, 2010 FN76850 Rev. 1.00 December 15, 2010 DATASHEET Description The ZL2006 is a digital DC-DC controller with integrated MOSFET drivers. Current sharing allows multiple devices to be connected in parallel to source loads with very high current demands. Adaptive performance optimization algorithms improve power conversion efficiency across the entire load range. Zilker Labs Digital-DC™ technology enables a blend of power conversion performance and power management features. The ZL2006 is designed to be a flexible building block for DC power and can be easily adapted to designs ranging from a single-phase power supply operating from a 3.3 V input to a multi-phase supply operating from a 12 V input. The ZL2006 eliminates the need for complicated power supply managers as well as numerous external discrete components. All operating features can be configured by simple pin- strap/resistor selection or through the SMBus™ serial interface. The ZL2006 uses the PMBus™ protocol for communication with a host controller and the Digital- DC bus for communication between other Zilker Labs devices. Features Power Conversion  Efficient synchronous buck controller  Adaptive light load efficiency optimization  3 V to 14 V input range  0.54 V to 5.5 V output range (with margin)  ±1% output voltage accuracy  Internal 3 A MOSFET drivers  Fast load transient response  Current sharing and phase interleaving  Snapshot™ parameter capture  RoHS compliant (6 x 6 mm) QFN package Power Management  Digital soft start / stop  Precision delay and ramp-up  Power good / enable  Voltage tracking, sequencing, and margining  Voltage / current / temperature monitoring  I2C/SMBus interface, PMBus compatible  Output voltage and current protection  Internal non-volatile memory (NVM) Applications  Servers / storage equipment  Telecom / datacom equipment  Power supplies (memory, DSP, ASIC, FPGA) NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ZL6100

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ZL2006 FN6850 Rev. 1.00 Page 2 of 45 December 15, 2010 Figure 1. Block Diagram Figure 2. Efficiency vs. Load Current CURRENT SENSE LDO TEMP SENSOR V SS VTRK MGN VR VDD BST GH SW ISENA ISENB POWER DRIVER XTEMP PWM GL I2C SCL SDA SALRT SA MANAGEMENT EN PG CFG UVLODLY ILIMFC MONITOR CONTROLLER V25 SYNC VSEN+ PGND SGND DGND ADC NON- VOLATILE MEMORY DDC VSEN- Load Current (A) E ff ic ie n c y ( % ) 65 70 80 75 85 95 90 100 2 140 64 8 1210 60 55 50 16 18 20 VIN = 12V fSW = 400kHz Circuit of Figure 4 VOUT = 3.3V VOUT = 1.5V

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ZL2006 FN6850 Rev. 1.00 Page 3 of 45 December 15, 2010 Table of Contents 1. Electrical Characteristics ............................................................................................................................................................. 4 2. Pin Descriptions ........................................................................................................................................................................... 8 3. Typical Application Circuit ....................................................................................................................................................... 10 4. ZL2006 Overview ...................................................................................................................................................................... 11 4.1 Digital-DC Architecture ..................................................................................................................................................... 11 4.2 Power Conversion Overview .............................................................................................................................................. 12 4.3 Power Management Overview ............................................................................................................................................ 13 4.4 Multi-mode Pins ................................................................................................................................................................. 14 5. Power Conversion Functional Description.................................................................................................................................... 15 5.1 Internal Bias Regulators and Input Supply Connections .................................................................................................... 15 5.2 High-side Driver Boost Circuit ........................................................................................................................................... 15 5.3 Output Voltage Selection .................................................................................................................................................... 15 5.4 Start-up Procedure .............................................................................................................................................................. 18 5.5 Soft Start Delay and Ramp Times ...................................................................................................................................... 18 5.6 Power Good ........................................................................................................................................................................ 19 5.7 Switching Frequency and PLL ........................................................................................................................................... 20 5.8 Power Train Component Selection ..................................................................................................................................... 21 5.9 Current Limit Threshold Selection ..................................................................................................................................... 25 5.10 Loop Compensation ............................................................................................................................................................ 28 5.11 Adaptive Compensation ...................................................................................................................................................... 29 5.12 Non-linear Response (NLR) Settings ................................................................................................................................. 29 5.13 Efficiency Optimized Driver Dead-time Control ................................................................................................................ 29 5.14 Adaptive Diode Emulation ................................................................................................................................................. 30 5.15 Adaptive Frequency Control ............................................................................................................................................... 30 6. Power Management Functional Description .............................................................................................................................. 31 6.1 Input Undervoltage Lockout ............................................................................................................................................... 31 6.2 Output Overvoltage Protection ........................................................................................................................................... 31 6.3 Output Pre-Bias Protection ................................................................................................................................................. 32 6.4 Output Overcurrent Protection ............................................................................................................................................ 33 6.5 Thermal Overload Protection .............................................................................................................................................. 33 6.6 Voltage Tracking ................................................................................................................................................................ 33 6.7 Voltage Margining .............................................................................................................................................................. 34 6.8 I2C/SMBus Communications .............................................................................................................................................. 35 6.9 I2C/SMBus Device Address Selection ................................................................................................................................ 35 6.10 Digital-DC Bus ................................................................................................................................................................... 36 6.11 Phase Spreading .................................................................................................................................................................. 36 6.12 Output Sequencing .............................................................................................................................................................. 37 6.13 Fault Spreading ................................................................................................................................................................... 37 6.14 Temperature Monitoring Using the XTEMP Pin ................................................................................................................ 38 6.15 Active Current Sharing ....................................................................................................................................................... 38 6.16 Phase Adding/Dropping ...................................................................................................................................................... 39 6.17 Monitoring via I2C/SMBus ................................................................................................................................................. 40 6.18 Snapshot™ Parameter Capture ........................................................................................................................................... 40 6.19 Non-Volatile Memory and Device Security Features ......................................................................................................... 41 7. Package Dimensions .................................................................................................................................................................. 42 8. Ordering Information ................................................................................................................................................................. 43 9. Related Tools and Documentation ............................................................................................................................................. 43 10. Revision History ........................................................................................................................................................................ 44

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ZL2006 FN6850 Rev. 1.00 Page 4 of 45 December 15, 2010 1. Electrical Characteristics Table 1. Absolute Maximum Ratings Operating beyond these limits may cause permanent damage to the device. Functional operation beyond the Recommended Operating Conditions is not implied. Voltage measured with respect to SGND. Parameter Pin Value Unit DC supply voltage VDD - 0.3 to 17 V MOSFET drive reference VR - 0.3 to 6.5 V 120 mA 2.5 V logic reference V25 - 0.3 to 3 V 120 mA Logic I/O voltage CFG, DLY(0,1), DDC, EN, FC(0,1), ILIM(0,1), MGN, PG, SA(0,1), SALRT, SCL, SDA, SS, SYNC, UVLO, V(0,1) - 0.3 to 6.5 V Analog input voltages ISENB, VSEN, VTRK, XTEMP - 0.3 to 6.5 V ISENA - 1.5 to 30 V High side supply voltage BST - 0.3 to 30 V Boost to switch voltage BST - SW - 0.3 to 8 V High side drive voltage GH (VSW-0.3) to (VBST+0.3) V Low side drive voltage GL (PGND-0.3) to (VR+0.3) V Switch node continuous SW (PGND-0.3) to 30 V Switch node transient (<100ns) SW (PGND-5) to 30 V Ground differential DGND – SGND, PGND - SGND - 0.3 to 0.3 V Junction temperature – - 55 to 150 °C Storage temperature – - 55 to 150 °C Lead temperature (Soldering, 10 s) All 300 °C Table 2. Recommended Operating Conditions and Thermal Information Parameter Symbol Min Typ Max Unit Input supply voltage range, VDD (See Figure 9) VDD tied to VR 3.0 – 5.5 V VR floating 4.5 – 14 V Output voltage range1 VOUT 0.54 – 5.5 V Operating junction temperature range TJ - 40 – 125 °C Junction to ambient thermal impedance2 ΘJA – 35 – °C/W Junction to case thermal impedance3 ΘJC – 5 – °C/W Notes: 1. Includes margin limits 2. ΘJA is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground plane using multiple vias. 3. For ΘJC, the “case” temperature is measured at the center of the exposed metal pad

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ZL2006 FN6850 Rev. 1.00 Page 5 of 45 December 15, 2010 Table 3. Electrical Specifications VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C. Parameter Conditions Min (Note 10) Typ Max (Note 10) Unit Input and Supply Characteristics IDD supply current at fSW = 200 kHz IDD supply current at fSW = 1.4 MHz GH, GL no load; MISC_CONFIG[7] = 1 – – 16 25 30 50 mA mA IDDS shutdown current EN = 0 V No I2C/SMBus activity – 6.5 8 mA VR reference output voltage VDD > 6 V, IVR < 50 mA 4.5 5.2 5.5 V V25 reference output voltage VR > 3 V, IV25 < 50 mA 2.25 2.5 2.75 V Output Characteristics Output voltage adjustment range1 VIN > VOUT 0.6 – 5.0 V Output voltage set-point resolution Set using resistors – 10 – mV Set using I2C/SMBus – ±0.025 – % FS2 Output voltage accuracy3 Includes line, load, temp - 1 – 1 % VSEN input bias current VSEN = 5.5 V – 110 200 µA Current sense differential input voltage (ground referenced) VISENA - VISENB - 100 – 100 mV Current sense differential input voltage (VOUT referenced) (VOUT must be less than 4.0 V) VISENA - VISENB - 50 – 50 mV Current sense input bias current Ground referenced - 100 – 100 µA Current sense input bias current (VOUT referenced, VOUT < 4.0 V) ISENA - 1 – 1 µA ISENB - 100 – 100 µA Soft start delay duration range4 Set using DLY pin or resistor 2 – 200 ms Set using I2C/SMBus 0.002 – 500 s Soft start delay duration accuracy Turn-on delay (precise mode) 4,5 Turn-on delay (normal mode) 6 Turn-off delay 6 – – – ±0.25 - 0.25/+4 - 0.25/+4 – – – ms ms ms Soft start ramp duration range Set using SS pin or resistor 0 – 200 ms Set using I2C 0 – 200 ms Soft start ramp duration accuracy – 100 – µs Notes: 1. Does not include margin limits. 2. Percentage of Full Scale (FS) with temperature compensation applied. 3. VOUT measured at the termination of the VSEN+ and VSEN- sense points. 4. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to approx 2 ms, where in normal mode it may vary up to 4 ms. 5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable. 6. The devices may require up to a 4 ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable signal.

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ZL2006 FN6850 Rev. 1.00 Page 6 of 45 December 15, 2010 Table 3. Electrical Characteristics (continued) VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C. Parameter Conditions Min (Note 10) Typ Max (Note 10) Unit Logic Input/Output Characteristics Logic input bias current EN,PG,SCL,SDA,SALRT pins - 10 – 10 µA MGN input bias current - 1 – 1 mA Logic input low, VIL – – 0.8 V Logic input OPEN (N/C) Multi-mode logic pins – 1.4 – V Logic input high, VIH 2.0 – – V Logic output low, VOL IOL ≤ 4 mA – – 0.4 V Logic output high, VOH IOH ≥ -2 mA 2.25 – – V Oscillator and Switching Characteristics Switching frequency range 200 – 1400 kHz Switching frequency set-point accuracy Predefined settings (See Table 16) - 5 – 5 % Maximum PWM duty cycle Factory default 95 – – % Minimum SYNC pulse width 150 – – ns Input clock frequency drift tolerance External clock source - 13 – 13 % Gate Drivers High-side driver voltage (VBST - VSW) – 4.5 – V High-side driver peak gate drive current (pull down) (VBST - VSW) = 4.5 V 2 3 – A High-side driver pull-up resistance (VBST - VSW) = 4.5 V, (VBST - VGH) = 50 mV – 0.8 2 Ω High-side driver pull-down resistance (VBST - VSW) = 4.5 V, (VGH - VSW) = 50 mV – 0.5 2 Ω Low-side driver peak gate drive current (pull-up) VR = 5 V – 2.5 – A Low-side driver peak gate drive current (pull-down) VR = 5 V – 1.8 – A Low-side driver pull-up resistance VR = 5 V, (VR - VGL) = 50 mV – 1.2 2 Ω Low-side driver pull-down resistance VR = 5 V, (VGL - PGND) = 50 mV – 0.5 2 Ω Switching timing GH rise and fall time GL rise and fall time (VBST - VSW) = 4.5 V, CLOAD = 2.2 nF – 5 20 ns VR = 5 V, CLOAD = 2.2 nF – 5 20 ns Tracking VTRK input bias current VTRK = 5.5 V – 110 200 µA VTRK tracking ramp accuracy 100% Tracking, VOUT - VTRK - 100 – + 100 mV VTRK regulation accuracy 100% Tracking, VOUT - VTRK - 1 – 1 %

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ZL2006 FN6850 Rev. 1.00 Page 7 of 45 December 15, 2010 Table 3. Electrical Characteristics (continued) VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C. Parameter Conditions Min (Note 10) Typ Max (Note 10) Unit Fault Protection Characteristics UVLO threshold range Configurable via I2C/SMBus 2.85 – 16 V UVLO set-point accuracy - 150 – 150 mV UVLO hysteresis Factory default – 3 – % Configurable via I2C/SMBus 0 – 100 % UVLO delay – – 2.5 µs Power good VOUT low threshold Factory default – 90 – % VOUT Power good VOUT high threshold Factory default – 115 – % VOUT Power good VOUT hysteresis Factory default – 5 – % Power good delay Using pin-strap or resistor 7 0 – 200 ms Configurable via I2C/SMBus 0 – 500 s VSEN undervoltage threshold Factory default – 85 – % VOUT Configurable via I2C/SMBus 0 – 110 % VOUT VSEN overvoltage threshold Factory default – 115 – % VOUT Configurable via I2C/SMBus 0 – 115 % VOUT VSEN undervoltage hysteresis – 5 – % VOUT VSEN undervoltage/ overvoltage fault response time Factory default – 16 – µs Configurable via I2C/SMBus 5 – 60 µs Current limit set-point accuracy (VOUT referenced) – ±10 – % FS8 Current limit set-point accuracy (Ground referenced) – ±10 – % FS8 Current limit protection delay Factory default – 5 – tSW 9 Configurable via I2C/SMBus 1 – 32 tSW 9 Temperature compensation of current limit protection threshold Factory default 4400 ppm / °C Configurable via I2C/SMBus 100 12700 Thermal protection threshold (junction temperature) Factory default – 125 – °C Configurable via I2C/SMBus - 40 – 125 °C Thermal protection hysteresis – 15 – °C Notes: 7. Factory default Power Good delay is set to the same value as the soft start ramp time. 8. Percentage of Full Scale (FS) with temperature compensation applied 9. tSW = 1/fSW, where fSW is the switching frequency. 10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

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ZL2006 FN6850 Rev. 1.00 Page 8 of 45 December 15, 2010 2. Pin Descriptions SA1 ILIM0 ILIM1 SCL SDA SALRT DGND SA0 SYNC 36-Pin QFN 6 x 6 mm SW PGND GL VR ISENA ISENB VDD GH BST E N C F G M G N D D C X T E M P V 2 5 P G D L Y 0 D L Y 1 V 1 U V L O S S V S E N + V T R K V S E N - F C 0 V 0 F C 1 Exposed Paddle Connect to SGND 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 27 26 25 24 23 22 21 20 19 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 Figure 3. ZL2006 Pin Configurations (top view) Table 4. Pin Descriptions Pin Label Type1 Description 1 DGND PWR Digital ground. Common return for digital signals. Connect to low impedance ground plane. 2 SYNC I/O,M2 Clock synchronization input. Used to set switching frequency of internal clock or for synchronization to external frequency reference. 3 SA0 I, M Serial address select pins. Used to assign unique SMBus address to each IC or to enable certain management features. 4 SA1 5 ILIM0 I, M Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB. 6 ILIM1 7 SCL I/O Serial clock. Connect to external host and/or to other ZL2006s. 8 SDA I/O Serial data. Connect to external host and/or to other ZL2006s. 9 SALRT O Serial alert. Connect to external host if desired. 10 FC0 I Loop compensation selection pins. 11 FC1 12 V0 I Output voltage selection pins. Used to set VOUT set-point and VOUT max. 13 V1 14 UVLO I, M Undervoltage lockout selection. Sets the minimum value for VDD voltage to enable VOUT. 15 SS I, M Soft start pin. Set the output voltage ramp time during turn-on and turnoff. 16 VTRK I Tracking sense input. Used to track an external voltage source. 17 VSEN+ I Output voltage feedback. Connect to output regulation point. Notes: 1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. 2. The SYNC pin can be used as a logic pin, a clock input or a clock output.

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ZL2006 FN6850 Rev. 1.00 Page 9 of 45 December 15, 2010 Table 4. Pin Descriptions (continued) Pin Label Type1 Description 18 VSEN- I Output voltage feedback. Connect to load return or ground regulation point. 19 ISENB I Differential voltage input for current limit. 20 ISENA I Differential voltage input for current limit. High voltage tolerant. 21 VR PWR Internal 5V reference used to power internal drivers. 22 GL O Low side FET gate drive. 23 PGND PWR Power ground. Connect to low impedance ground plane. 24 SW PWR Drive train switch node. 25 GH O High-side FET gate drive. 26 BST PWR High-side drive boost voltage. 27 VDD3 PWR Supply voltage. 28 V25 PWR Internal 2.5 V reference used to power internal circuitry. 29 XTEMP I External temperature sensor input. Connect to external 2N3904 diode connected transistor. 30 DDC I/O Digital-DC Bus. (Open Drain) Communication between Zilker Labs devices. 31 MGN I Signal that enables margining of output voltage. 32 CFG I, M Configuration pin. Used to control the switching phase offset, sequencing and other management features. 33 EN I Enable input. Active high signal enables PWM switching. 34 DLY0 I, M Softstart delay select. Sets the delay from when EN is asserted until the output voltage starts to ramp. 35 DLY1 36 PG O Power good output. ePad SGND PWR Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low impedance ground plane. Notes: 1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. Please refer to Section 4.4“Multi-mode Pins,” on page 14. 2. The SYNC pin can be used as a logic pin, a clock input or a clock output. 3. VDD is measured internally and the value is used to modify the PWM loop gain.

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Mere***** Hayer

August 22, 2020

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August 18, 2020

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August 17, 2020

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July 20, 2020

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July 13, 2020

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July 6, 2020

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July 4, 2020

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