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74LVTH16244MTDX

hot 74LVTH16244MTDX

74LVTH16244MTDX

For Reference Only

Part Number 74LVTH16244MTDX
Manufacturer Fairchild/ON Semiconductor
Description IC BUFF DVR TRI-ST 16BIT 48TSSOP
Datasheet 74LVTH16244MTDX Datasheet
Package 48-TFSOP (0.240", 6.10mm Width)
In Stock 80908 piece(s)
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74LVTH16244MTDX

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74LVTH16244MTDX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74LVTH16244MTDX Datasheet
Package48-TFSOP (0.240", 6.10mm Width)
Series74LVTH
Logic TypeBuffer, Non-Inverting
Number of Elements4
Number of Bits per Element4
Output TypePush-Pull
Current - Output High, Low32mA, 64mA
Voltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case48-TFSOP (0.240", 6.10mm Width)
Supplier Device Package48-TSSOP

74LVTH16244MTDX Datasheet

Page 1

Page 2

© 2005 Fairchild Semiconductor Corporation DS500151 www.fairchildsemi.com March 1999 Revised June 2005 7 4 L V T 1 6 2 4 4 • 7 4 L V T H 1 6 2 4 4 L o w V o lta g e 1 6 -B it B u ffe r/L in e D riv e r w ith 3 -S T A T E O u tp u ts 74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs General Description The LVT16244 and LVTH16244 contain sixteen non-invert- ing buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus ori- ented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVTH16244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16244 and LVTH16244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation Features ■ Input and output interface capability to systems at 5V VCC ■Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16244), also available without bushold feature (74LVT16244). ■Live insertion/extraction permitted ■Power Up/Down high impedance provides glitch-free bus loading ■Outputs source/sink 32 mA/64 mA ■Functionally compatible with the 74 series 16244 ■Latch-up performance exceeds 500 mA ■ESD performance: Human-body model !2000V Machine model !200V Charged-drive model !1000V ■Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Note 1: Ordering code “G” indicates Trays. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Order Number Package Number Package Description 74LVT16244G (Note 1)(Note 2) BGA54A (Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVT16244MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16244MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16244G (Note 1)(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVTH16244MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16244MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

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www.fairchildsemi.com 2 7 4 L V T 1 6 2 4 4 • 7 4 L V T H 1 6 2 4 4 Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) Logic Diagram Pin Descriptions FBGA Pin Assignments Truth Table H High Voltage Level L Low Voltage Level X Immaterial Z High Impedance Functional Description The LVT16244 and LVTH16244 contain sixteen non-invert- ing buffers with 3-STATE outputs. The device is nibble (4-bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Pin Names Description OEn Output Enable Inputs (Active LOW) I0–I15 Inputs O0–O15 Outputs NC No Connect 1 2 3 4 5 6 A O0 NC OE1 OE2 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE4 OE3 NC I15 Inputs Outputs OE1 I0–I3 O0–O3 L L L L H H H X Z Inputs Outputs OE2 I4–I7 O4–O7 L L L L H H H X Z Inputs Outputs OE3 I8–I11 O8–O11 L L L L H H H X Z Inputs Outputs OE4 I12–I15 O12–O15 L L L L H H H X Z

Page 4

3 www.fairchildsemi.com 7 4 L V T 1 6 2 4 4 • 7 4 L V T H 1 6 2 4 4 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol Parameter Value Conditions Units VCC Supply Voltage 0.5 to 4.6 V VI DC Input Voltage 0.5 to 7.0 V VO Output Voltage 0.5 to 7.0 Output in 3-STATE V 0.5 to 7.0 Output in HIGH or LOW State (Note 4) IIK DC Input Diode Current 50 VI  GND mA IOK DC Output Diode Current 50 VO  GND mA IO DC Output Current 64 VO ! VCC Output at HIGH State mA 128 VO ! VCC Output at LOW State ICC DC Supply Current per Supply Pin r64 mA IGND DC Ground Current per Ground Pin r128 mA TSTG Storage Temperature 65 to 150 qC Symbol Parameter Min Max Units VCC Supply Voltage 2.7 3.6 V VI Input Voltage 0 5.5 V IOH HIGH Level Output Current 32 mA IOL LOW Level Output Current 64 mA TA Free Air Operating Temperature 40 85 qC 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V 0 10 ns/V Symbol Parameter VCC TA 40qC to 85qC Units Conditions (V) Min Max VIK Input Clamp Diode Voltage 2.7 1.2 V II 18 mA VIH Input HIGH Voltage 2.7–3.6 2.0 V VO d 0.1V or VIL Input LOW Voltage 2.7–3.6 0.8 V VO t VCC  0.1V VOH Output HIGH Voltage 2.7–3.6 VCC  0.2 V IOH 100 PA 2.7 2.4 IOH 8 mA 3.0 2.0 IOH 32 mA VOL Output LOW Voltage 2.7 0.2 V IOL 100 PA 2.7 0.5 IOL 24 mA 3.0 0.4 IOL 16 mA 3.0 0.5 IOL 32 mA 3.0 0.55 IOL 64 mA II(HOLD) Bushold Input Minimum Drive 3.0 75 PA VI 0.8V (Note 5) 75 VI 2.0V II(OD) Bushold Input Over-Drive 3.0 500 PA (Note 6) (Note 5) Current to Change State 500 (Note 7) II Input Current 3.6 10 PA VI 5.5V Control Pins 3.6 r1 VI 0V or VCC Data Pins 3.6 5 VI 0V 1 VI VCC IOFF Power Off Leakage Current 0 r100 PA 0V d VI or VO d 5.5V IPU/PD Power Up/Down 0 – 1.5V r100 PA VO 0.5V to 3.0V 3-STATE Current VI GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC  VO d 5.5V

Page 5

www.fairchildsemi.com 4 7 4 L V T 1 6 2 4 4 • 7 4 L V T H 1 6 2 4 4 DC Electrical Characteristics (Continued) Note 5: Applies to bushold versions only (LVTH16244). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics (Note 9) Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 12) Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012. Symbol Parameter VCC TA 40qC to 85qC Units Conditions (V) Min Max ICCH Power Supply Current 3.6 0.19 mA Outputs High ICCL Power Supply Current 3.6 5.0 mA Outputs Low ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d VO d 5.5V, Outputs Disabled 'ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC  0.6V (Note 8) Other Inputs at VCC or GND Symbol Parameter VCC TA 25qC Units Conditions (V) Min Typ Max CL 50 pF, RL 500: VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Symbol Parameter TA 40qC to 85qC Units CL 50 pF, RL 500: VCC 3.3V r 0.3V VCC 2.7V Min Max Min Max tPLH Propagation Delay Data to Output 1.2 3.5 1.2 3.9 ns tPHL 1.2 3.5 1.2 3.9 tPZH Output Enable Time 1.2 4.0 1.2 5.0 ns tPZL 1.2 5.0 1.2 6.5 tPHZ Output Disable Time 2.0 4.7 2.0 5.2 ns tPLZ 1.5 4.2 1.5 4.4 tOSHL Output to Output Skew 1.0 1.0 ns tOSLH (Note 11) Symbol Parameter Conditions Typical Units CIN Input Capacitance VCC 0V, VI 0V or VCC 4 pF COUT Output Capacitance VCC 3.0V, VO 0V or VCC 8 pF

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5 www.fairchildsemi.com 7 4 L V T 1 6 2 4 4 • 7 4 L V T H 1 6 2 4 4 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A

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www.fairchildsemi.com 6 7 4 L V T 1 6 2 4 4 • 7 4 L V T H 1 6 2 4 4 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A

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