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74VHC125MX

hot 74VHC125MX

74VHC125MX

For Reference Only

Part Number 74VHC125MX
Manufacturer ON Semiconductor
Description IC BUF NON-INVERT 5.5V 14SOIC
Datasheet 74VHC125MX Datasheet
Package 14-SOIC (0.154", 3.90mm Width)
In Stock 345 piece(s)
Unit Price $ 0.2057 *
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74VHC125MX

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74VHC125MX Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Buffers, Drivers, Receivers, Transceivers
Datasheet 74VHC125MX Datasheet
Package14-SOIC (0.154", 3.90mm Width)
Series74VHC
Logic TypeBuffer, Non-Inverting
Number of Elements4
Number of Bits per Element1
Output Type3-State
Current - Output High, Low8mA, 8mA
Voltage - Supply2 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case14-SOIC (0.154", 3.90mm Width)
Supplier Device Package14-SOIC

74VHC125MX Datasheet

Page 1

Page 2

To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. Is Now Part of ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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7 4 V H C 1 2 5 — Q u a d B u ffe r w ith 3 -S T A T E O u tp u ts ©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC125 Rev. 1.4.0 December 2007 74VHC125 Quad Buffer with 3-STATE Outputs Features ■ High Speed: t PD = 3.8ns (Typ.) at V CC = 5V ■ Lower power dissipation: I CC = 4 µA (Max.) at T A = 25°C ■ High noise immunity: V NIH = V NIL = 28% V CC (Min.) ■ Power down protection is provided on all inputs ■ Low noise: V OLP = 0.8V (Max.) ■ Pin and function compatible with 74HC125 General Description The VHC125 contains four independent non-inverting buffers with 3-STATE outputs. It is an advanced high- speed CMOS device fabricated with silicon gate CMOS technology and achieves the high-speed operation simi- lar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74VHC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Page 4

©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC125 Rev. 1.4.0 2 7 4 V H C 1 2 5 — Q u a d B u ffe r w ith 3 -S T A T E O u tp u ts Connection Diagram Pin Description Logic Symbol IEEE/IEC Function Table H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial Pin Names Description A n , B n Inputs O n Outputs Inputs Output A n B n O n L L L L H H H X Z

Page 5

©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC125 Rev. 1.4.0 3 7 4 V H C 1 2 5 — Q u a d B u ffe r w ith 3 -S T A T E O u tp u ts Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Recommended Operating Conditions (1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Note: 1. Unused inputs must be held HIGH or LOW. They may not float. Symbol Parameter Rating V CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUT DC Output Voltage –0.5V to V CC + 0.5V I IK Input Diode Current –20mA I OK Output Diode Current ±20mA I OUT DC Output Current ±25mA I CC DC V CC / GND Current ±50mA T STG Storage Temperature –65°C to +150°C T L Lead Temperature (Soldering, 10 seconds) 260°C Symbol Parameter Rating V CC Supply Voltage 2.0V to +5.5V V IN Input Voltage 0V to +5.5V V OUT Output Voltage 0V to V CC T OPR Operating Temperature –40°C to +85°C t r , t f Input Rise and Fall Time, V CC = 3.3V ± 0.3V V CC = 5.0V ± 0.5V 0ns/V ∼ 100ns/V 0ns/V ∼ 20ns/V

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©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC125 Rev. 1.4.0 4 7 4 V H C 1 2 5 — Q u a d B u ffe r w ith 3 -S T A T E O u tp u ts DC Electrical Characteristics Noise Characteristics Note: 2. Parameter guaranteed by design. Symbol Parameter V CC (V) Conditions T A = Units 25°C –40°C to +85°C Min. Typ. Max. Min. Max. V IH HIGH Level Input Voltage 2.0 1.50 1.50 V 3.0–5.5 0.7 x V CC 0.7 x V CC V IL LOW Level Input Voltage 2.0 0.50 0.50 V 3.0–5.5 0.3 x V CC 0.3 x V CC V OH HIGH Level Output Voltage 2.0 V IN = V IH or V IL I OH = –50µA 1.9 2.0 1.9 V 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 I OH = –4mA 2.58 2.48 4.5 I OH = –8mA 3.94 3.80 V OL LOW Level Output Voltage 2.0 V IN = V IH or V IL I OL = 50µA 0.0 0.1 0.1 V 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 I OL = 4mA 0.36 0.44 4.5 I OL = 8mA 0.36 0.44 I OZ 3-STATE Output Off-State Current 5.5 V IN = V IH or V IL , V OUT = V CC or GND ±0.25 ±2.5 µA I IN Input Leakage Current 0–5.5 V IN = 5.5V or GND ±0.1 ±1.0 µA I CC Quiescent Supply Current 5.5 V IN = V CC or GND 4.0 40.0 µA Symbol Parameter V CC (V) Conditions T A = 25°C UnitsTyp. Limits V OLP (2) Quiet Output Maximum Dynamic V OL 5.0 C L = 50pF 0.5 0.8 V V OLV (2) Quiet Output Minimum Dynamic V OL 5.0 C L = 50pF –0.5 –0.8 V V IHD (2) Minimum HIGH Level Dynamic Input Voltage 5.0 C L = 50pF 3.5 V V ILD (2) Maximum HIGH Level Dynamic Input Voltage 5.0 CL = 50pF 1.5 V

Page 7

©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC125 Rev. 1.4.0 5 7 4 V H C 1 2 5 — Q u a d B u ffe r w ith 3 -S T A T E O u tp u ts AC Electrical Characteristics Notes: 3. Parameter guaranteed by design. tOSLH = |tPLHmax – tPLHmin|; tOSHL = |tPHLmax – tPHLmin|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD • VCC • fIN + ICC / 4 (per bit). Symbol Parameter VCC (V) Conditions TA = 25°C TA = –40°C to +85°C UnitsMin. Typ. Max. Min. Max. tPLH, tPHL Propagation Delay Time 3.3 ± 0.3 CL = 15pF 5.6 8.0 1.0 9.5 ns CL = 50pF 8.1 11.5 1.0 13.0 5.0 ± 0.5 CL = 15pF 3.8 5.5 1.0 6.5 ns CL = 50pF 5.3 7.5 1.0 8.5 tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 RL = 1kΩ CL = 15pF 5.4 8.0 1.0 9.5 ns CL = 50pF 7.9 11.5 1.0 13.0 5.0 ± 0.5 CL = 15pF 3.6 5.1 1.0 6.0 ns CL = 50pF 5.1 7.1 1.0 8.0 tPLZ, tPHZ 3-STATE Output Disable Time 3.3 ± 0.3 RL = 1kΩ CL = 50pF 9.5 13.2 1.0 15.0 ns 5.0 ± 0.5 CL = 50pF 6.1 8.8 1.0 10.0 tOSLH, tOSHL Output to Output Skew 3.3 ± 0.3 (3) CL = 50pF 1.5 1.5 ns 5.0 ± 0.5 CL = 50pF 1.0 1.0 CIN Input Capacitance VCC = Open 4 10 10 pF COUT Output Capacitance VCC = 5.0V 6 pF CPD Power Dissipation Capacitance (4) 14 pF

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FRONT VIEW TOP VIEW ALL LEAD TIPS NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. F. DRAWING FILE NAME: MKT-MTC14rev7. 0.43TYP 0.2 C B A 8 1 7 14 A B 3.2 6.4 PIN#1 IDENT 1.2 MAX 0.1 C ALL LEAD TIPS C 0.65 0.30 0.19 0.13 A B C 0.90 +0.15 -0.10 0.20 0.09 SEE DETAIL A GAGE PLANE 0.25 SEATING PLANE 0.09 MIN 0.09 MIN 1.00 DETAIL A RECOMMENDED LAND PATTERN 6.10 0.65 1.65 0.45

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1.70 5.60 1.27 0.65 1.501.25 1.75 MAX 0.250.10 C 4.003.80 8.758.50 6.00 (0.33) 0.510.35 7.62 1.27 1 PIN #1 IDENT. A B 0.250.19 A 0.500.25 x 45 R0.10 R0.10 (1.04) 0.36 8°0° 0.900.50 DETAIL A SCALE 16 : 1 GAGE PLANE SEATING PLANE TOP VIEW FRONT VIEW SIDE VIEW 14 7 8 1 7 8 LAND PATTERN RECOMMENDATION NOTES: A. CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS D. LAND PATTERN STANDARD: SOIC127P600X145-14M E. CONFORMS TO ASME Y14.5M, 2009 D. DRAWING FILENAME: MKT-M14Arev14 14 0.10 C 0.25 M C B A

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