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AD7248AQ

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AD7248AQ

For Reference Only

Part Number AD7248AQ
Manufacturer Analog Devices Inc.
Description IC DAC 12BIT W/REF 24-CDIP
Datasheet AD7248AQ Datasheet
Package 24-CDIP (0.300", 7.62mm)
In Stock 4,844 piece(s)
Unit Price $ 30.6694 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 2 - Jun 7 (Choose Expedited Shipping)
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Part Number # AD7248AQ (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7248AQ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet AD7248AQDatasheet
Package24-CDIP (0.300", 7.62mm)
SeriesDACPORT?
Number of Bits12
Number of D/A Converters1
Settling Time5µs, 10µs
Output TypeVoltage - Buffered
Differential OutputNo
Data InterfaceParallel
Reference TypeInternal
Voltage - Supply, Analog��14.25 V ~ 15.75 V
Voltage - Supply, Digital14.25 V ~ 15.75 V
INL/DNL (LSB)±1 (Max), ±1 (Max)
ArchitectureR-2R
Operating Temperature-25°C ~ 85°C
Package / Case24-CDIP (0.300", 7.62mm)
Supplier Device Package24-CDIP
Mounting Type-

AD7248AQ Datasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a LC 2MOS 12-Bit DACPORTs AD7245A/AD7248A FEATURES 12-Bit CMOS DAC with Output Amplifier and Reference Improved AD7245/AD7248: 12 V to 15 V Operation 1/2 LSB Linearity Grade Faster Interface—30 ns Typ Data Setup Time Extended Plastic Temperature Range (–40C to +85C) Single or Dual Supply Operation Low Power—65 mW Typ in Single Supply Parallel Loading Structure: AD7245A (8+4) Loading Structure: AD7248A GENERAL DESCRIPTION The AD7245A/AD7248A is an enhanced version of the industry standard AD7245/AD7248. Improvements include operation from 12 V to 15 V supplies, a ± 1/2 LSB linearity grade, faster interface times and better full scale and reference variations with VDD. Additional features include extended temperature range operation for commercial and industrial grades. The AD7245A/AD7248A is a complete, 12-bit, voltage output, digital-to-analog converter with output amplifier and Zener voltage reference on a monolithic CMOS chip. No external user trims are required to achieve full specified performance. Both parts are microprocessor compatible, with high speed data latches and double-buffered interface logic. The AD7245A accepts 12-bit parallel data that is loaded into the input latch on the rising edge of CS or WR. The AD7248A has an 8-bit-wide data bus with data loaded to the input latch in two write operations. For both parts, an asynchronous LDAC signal transfers data from the input latch to the DAC latch and updates the analog output. The AD7245A also has a CLR signal on the DAC latch which allows features such as power-on reset to be implemented. The on-chip 5 V buried Zener diode provides a low noise, tem- perature compensated reference for the DAC. For single supply operation, two output ranges of 0 V to 5 V and 0 V to 10 V are available, while these two ranges plus an additional ±5 V range are available with dual supplies. The output amplifiers are capa- ble of developing 10 V across a 2 kΩ load to GND. The AD7245A/AD7248A is fabricated in linear compatible CMOS (LC2MOS), an advanced, mixed technology process that combines precision bipolar circuits with low power CMOS logic. The AD7245A is available in a small, 0.3" wide, 24-lead DIP and SOIC and in 28-terminal surface mount packages. The AD7248A is packaged in a small, 0.3" wide, 20-lead DIP and SOIC and in 20-terminal surface mount packages. DACPORT is a registered trademark of Analog Devices, Inc. AD7245A FUNCTIONAL BLOCK DIAGRAM DB0 DB11 DGND VSSAGND VDD REF OUT ROFS RFB VOUT AD7245A VREF 2R 2R CONTROL LOGIC DAC DAC LATCH INPUT LATCH CS WR LDAC CLR AD7248A FUNCTIONAL BLOCK DIAGRAM DB7 DB0 DGND VSS CSMSB CSLSB LDAC WR AGND VDD REF OUT ROFS RFB VOUT AD7248A VREF 2R 2R CONTROL LOGIC DAC DAC LATCH 4-BIT INPUT LATCH 8-BIT INPUT LATCH PRODUCT HIGHLIGHTS 1. The AD7245A/AD7248A is a 12-bit DACPORT® on a single chip. This single chip design and small package size offer considerable space saving and increased reliability over multichip designs. 2. The improved interface times on the part allows easy, direct interfacing to most modern microprocessors. 3. The AD7245A/AD7248A features a wide power supply range allowing operation from 12 V supplies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

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A2 B2 T2 Parameter Version Version Version Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 12 12 12 Bits Relative Accuracy @ 25°C3 ±3/4 ±1/2 ±1/2 LSB max TMIN to TMAX ±1 ±3/4 ±3/4 LSB max TMIN to TMAX ±1/2 LSB max VDD = 15 V ± 10% Differential Nonlinearity3 ±1 ±1 ±1 LSB max Guaranteed Monotonic Unipolar Offset Error @ 25°C3 ±3 ±3 ±3 LSB max VSS = 0 V or –12 V to –15 V4 TMIN to TMAX ±5 ±5 ±5 LSB max Typical Tempco is ±3 ppm of FSR5/°C. Bipolar Zero Error @ 25°C3 ± 3 ± 2 ± 2 LSB max ROFS connected to REF OUT; VSS = –12 V to –15 V4 TMIN to TMAX ±5 ±4 ±4 LSB max Typical Tempco is ±3 ppm of FSR5/°C. DAC Gain Error3, 6 ±2 ±2 ±2 LSB max Full-Scale Output Voltage Error7 @ 25°C ±0.2 ±0.2 ±0.2 % of FSR max VDD = 15 V ∆Full Scale/∆VDD ±0.06 ±0.06 ±0.06 % of FSR/V max VDD = +12 V to +15 V4 ∆Full Scale/∆VSS ±0.01 ±0.01 ±0.01 % of FSR/V max VSS = –12 V to –15 V4 Full-Scale Temperature Coefficient8 ±40 ±30 ±40 ppm of FSR/°C max VDD = 15 V REFERENCE OUTPUT REF OUT @ 25°C 4.99/5.01 4.99/5.01 4.99/5.01 V min/V max VDD = 15 V ∆REF OUT/∆VDD 2 2 2 mV/V max VDD = 12 V to 15 V4 Reference Temperature Coefficient ±25 ±25 ±35 ppm/°C typ Reference Load Change (∆REF OUT vs. ∆I) –1 –1 –1 mV max Reference Load Current Change (0–100 µA) DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 0.8 V max Input Current, IIN ±10 ±10 ±10 µA max VIN = 0 V to VDD Input Capacitance9 8 8 8 pF max ANALOG OUTPUTS Output Range Resistors 15/30 15/30 15/30 kΩ min/kΩ max Output Voltage Ranges10 5, 10 5, 10 5, 10 V VSS = 0 V; Pin Strappable 5, 10, 5, 10, 5, 10, VSS = –12 V to –15 V; 4 Pin Strappable ±5 ±5 ±5 V DC Output Impedance 0.5 0.5 0.5 Ω typ AC CHARACTERISTICS9 Voltage Output Settling Time Settling Time to Within ±1/2 LSB of Final Value Positive Full-Scale Change 7 7 10 µs max DAC Latch All 0s to All 1s Negative Full-Scale Change 7 7 10 µs max DAC Latch All 1s to All 0s; VSS = –12 V to –15 V4 Output Voltage Slew Rate 2 2 1.5 V/µs min Digital Feedthrough3 10 10 10 nV-s typ Digital-to-Analog Glitch Impulse 30 30 30 nV-s typ POWER REQUIREMENTS VDD +10.8/ +10.8/ +10.8/ V min/ For Specified Performance Unless Otherwise Stated +16.5 +16.5 +16.5 V max VSS –10.8/ –10.8/ –10.8/ V min/ For Specified Performance Unless Otherwise Stated –16.5 –16.5 –16.5 V max IDD @ 25°C 9 9 9 mA max Output Unloaded; Typically 5 mA TMlN to TMAX 10 10 12 mA max Output Unloaded ISS (Dual Supplies) 3 3 5 mA max Output Unloaded; Typically 2 mA NOTES 1Power supply tolerance is ±10%. 2Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version; –55°C to +125°C. 3See Terminology. 4With appropriate power supply tolerances. 5FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and ± 5 V output ranges. 6This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for. 7This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and ±5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V range. It includes the effects of internal voltage reference, gain and offset errors. 8Full-Scale TC = ∆FS/∆T, where ∆FS is the full-scale change from TA = 25°C to TMIN or TMAX. 9Guaranteed by design and characterization, not production tested. 100 V to 10 V output range is available only when VDD ≥ +14.25 V. Specifications subject to change without notice. AD7245A/AD7248A–SPECIFICATIONS REV. B–2– (VDD = +12 V to +15 V, 1 VSS = O V or –12 V to –15 V, 1 AGND = DGND = O V, RL = 2 k, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)

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AD7245A/AD7248A REV. B –3– SWITCHING CHARACTERISTICS1 Parameter A, B Versions T Version Unit Conditions t1 @ 25°C 55 55 ns typ Chip Select Pulsewidth TMIN to TMAX 80 100 ns min t2 @ 25°C 40 40 ns typ Write Pulsewidth TMIN to TMAX 80 100 ns min t3 @ 25°C 0 0 ns min Chip Select to Write Setup Time TMIN to TMAX 0 0 ns min t4 @ 25°C 0 0 ns min Chip Select to Write Hold Time TMIN to TMAX 0 0 ns min t5 @ 25°C 40 40 ns typ Data Valid to Write Setup Time TMIN to TMAX 80 80 ns min t6 @ 25°C 10 10 ns min Data Valid to Write Hold Time TMIN to TMAX 10 10 ns min t7 @ 25°C 40 40 ns typ Load DAC Pulsewidth TMIN to TMAX 80 100 ns min t8 (AD7245A Only) @ 25°C 40 40 ns typ Clear Pulsewidth TMIN to TMAX 80 100 ns min NOTES 1Sample tested at 25°C to ensure compliance. 2Power supply tolerance is ±10%. ABSOLUTE MAXIMUM RATINGS1 VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VOUT to AGND 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD VOUT to VSS 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 24 V VOUT to VDD 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –32 V, 0 V REF OUT2 to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2The output may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. VOUT short circuit current is typically 80 mA. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE (VDD = +12 V to +15 V; 2 VSS = 0 V to –12 V to –15 V; 2 See Figures 5 and 7.)

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AD7245A/AD7248A REV. B–4– DAC GAIN ERROR DAC Gain Error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been allowed for. It is, therefore defined as: Measured Value—Offset—Ideal Value where the ideal value is calculated relative to the actual refer- ence value. UNIPOLAR OFFSET ERROR Unipolar Offset Error is a combination of the offset errors of the voltage mode DAC and the output amplifier and is measured when the part is configured for unipolar outputs. It is present for all codes and is measured with all 0s in the DAC register. BIPOLAR ZERO OFFSET ERROR Bipolar Zero Offset Error is measured when the part is config- ured for bipolar output and is a combination of errors from the DAC and output amplifier. It is present for all codes and is measured with a code of 2048 (decimal) in the DAC register. SINGLE SUPPLY LINEARITY AND GAIN ERROR The output amplifier of the AD7245A/AD7248A can have a true negative offset even when the part is operated from a single positive power supply. However, because the lower supply rail to the part is 0 V, the output voltage cannot actually go nega- tive. Instead the output voltage sits on the lower rail and this results in the transfer function shown. This is an offset effect and the transfer function would have followed the dotted line if the output voltage could have gone negative. Normally, linearity is measured after offset and full scale have been adjusted or allowed for. On the AD7245A/AD7248A the negative offset is allowed for by calculating the linearity from the code which the amplifier comes off the lower rail. This code is given by the negative offset specification. For example, the single supply linearity specification applies between Code 3 and Code 4095 for the 25°C specification and between Code 5 and Code 4095 over the TMIN to TMAX temperature range. Since gain error is also measured after offset has been allowed for, it is calculated between the same codes as the linearity error. Bipolar linearity and gain error are measured between Code 0 and Code 4095. 0V NEGATIVE OFFSET DAC CODE OUTPUT VOLTAGE TERMINOLOGY RELATIVE ACCURACY Relative Accuracy, or endpoint nonlinearity, is a measure of the actual deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB max over the operating temperature range ensures monotonicity. DIGITAL FEEDTHROUGH Digital Feedthrough is the glitch impulse injected from the digital inputs to the analog output when the inputs change state. It is measured with LDAC high and is specified in nV-s. AD7245A ORDERING GUIDE Temperature Relative Package Model1 Range Accuracy Option2 AD7245AAN –40°C to +85°C ±3/4 LSB N-24 AD7245ABN –40°C to +85°C ±1/2 LSB N-24 AD7245AAQ –40°C to +85°C ±3/4 LSB Q-24 AD7245ATQ3 –55°C to +125°C ±3/4 LSB Q-24 AD7245AAP –40°C to +85°C ±3/4 LSB P-28A AD7245AAR –40°C to +85°C ±3/4 LSB R-24 AD7245ABR –40°C to +85°C ±1/2 LSB R-24 AD7245ATE3 –55°C to +125°C ±3/4 LSB E-28A NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact our local sales office for military data sheet and availability. 2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. 3This grade will be available to /883B processing only. AD7248A ORDERING GUIDE Temperature Relative Package Model1 Range Accuracy Option2 AD7248AAN –40°C to +85°C ±3/4 LSB N-20 AD7248ABN –40°C to +85°C ±1/2 LSB N-20 AD7248AAQ –40°C to +85°C ±3/4 LSB Q-20 AD7248ATQ3 –55°C to +125°C ±3/4 LSB Q-20 AD7248AAP –40°C to +85°C ±3/4 LSB P-20A AD7248AAR –40°C to +85°C ±3/4 LSB R-20 AD7248ABR –40°C to +85°C ±1/2 LSB R-20 NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact our local sales office for military data sheet and availability. 2N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. 3This grade will be available to /883B processing only.

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AD7245A/AD7248A REV. B –5– AD7245A PIN FUNCTION DESCRIPTIONS (DIP PIN NUMBERS) Pin Mnemonic Description l VSS Negative Supply Voltage (0 V for single supply operation). 2 ROFS Bipolar Offset Resistor. This provides access to the on-chip application resistors and allows different output voltage ranges. 3 REF OUT Reference Output. The on-chip reference is provided at this pin and is used when configuring the part for bipolar outputs. 4 AGND Analog Ground. 5 DB11 Data Bit 11. Most Significant Bit (MSB). 6–11 DB10–DB5 Data Bit 10 to Data Bit 5. 12 DGND Digital Ground. 13–16 DB4–DB1 Data Bit 4 to Data Bit 1. 17 DB0 Data Bit 0. Least Significant Bit (LSB). 18 CS Chip Select Input (Active LOW). The device is selected when this input is active. Pin Mnemonic Description 19 WR Write Input (Active LOW). This is used in conjunction with CS to write data into the input latch of the AD7245A. 20 LDAC Load DAC Input (Active LOW). This is an asynchronous input which when active transfers data from the input latch to the DAC latch. 21 CLR Clear Input (Active LOW). When this input is active the contents of the DAC latch are reset to all 0s. 22 VDD Positive Supply Voltage. 23 RFB Feedback Resistor. This allows access to the amplifier’s feedback loop. 24 VOUT Output Voltage. Three different output voltage ranges can be chosen: 0 V to 5 V, 0 V to 10 V or –5 V to +5 V. AD7245A PIN CONFIGURATIONS DIP and SOIC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 AD7245A TOP VIEW (NOT TO SCALE) VSS ROFS REF OUT AGND (MSB) DB11 DB10 DB9 DB8 DB7 DB6 DB5 DGND DB4 DB3 DB2 DB1 DB0 (LSB) CS WR LDAC CLR VDD RFB VOUT LCCC 4 3 2 1 28 27 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 AGND DB11 DB10 NC DB9 DB8 DB7 D B 6 D B 5 D G N D N C D B 4 D B 3 D B 2 CLR LDAC WR NC CS DB0 DB1 R E F O U T R O F S V S S N C V O U T R F B V D D NC = NO CONNECT AD7245A TOP VIEW (NOT TO SCALE) PLCC 1234 5 6 7 AGND DB11 DB10 NC DB9 DB8 DB7 25 24 23 22 21 20 19 DB1 DB0 CS NC WR LDAC CLR 18171615141312 D B 2 D B 3 D B 4 N C D G N D D B 5 D B 6 V D D R F B V O U T N C V S S R O F S R E F O U T AD7245A TOP VIEW (NOT TO SCALE) NC = NO CONNECT 8 9 10 11 262728

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AD7245A/AD7248A REV. B–6– AD7248A PIN FUNCTION DESCRIPTIONS (ANY PACKAGE) Pin Mnemonic Description l VSS Negative Supply Voltage (0 V for single supply operation). 2 ROFS Bipolar Offset Resistor. This provides access to the on-chip application resistors and allows different output voltage ranges. 3 REF OUT Reference Output. The on-chip reference is provided at this pin and is used when configuring the part for bipolar outputs. 4 AGND Analog Ground. 5 DB7 Data Bit 7. 6 DB6 Data Bit 6. 7 DB5 Data Bit 5. 8 DB4 Data Bit 4. 9 DB3 Data Bit 3. 10 DGND Digital Ground. 11 DB2 Data Bit 2/Data Bit 10. 12 DB1 Data Bit 1/Data Bit 9. 13 DB0 Data Bit 0 (LSB)/Data Bit 8. Pin Mnemonic Description 14 CSMSB Chip Select Input for MS Nibble. (Active LOW). This selects the upper 4 bits of the input latch. Input data is right justified. 15 CSLSB Chip Select Input for LS byte. (Active LOW). This selects the lower 8 bits of the input latch. 16 WR Write Input. This is used in conjunction with CSMSB and CSLSB to load data into the input latch of the AD7248A. 17 LDAC Load DAC Input (Active LOW). This is an asynchronous input which when active transfers data from the input latch to the DAC latch. 18 VDD Positive Supply Voltage. 19 RFB Feedback Resistor. This allows access to the amplifier’s feedback loop. 20 VOUT Output Voltage. Three different output voltage ranges can be chosen: 0 V to 5 V, 0 V to 10 V or –5 V to +5 V. AD7248A PIN CONFIGURATIONS DIP and SOIC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AD7248A TOP VIEW (NOT TO SCALE) VSS ROFS REF OUT AGND (MSB) DB7 DB6 DB5 DB4 DB3 DGND DB2 DB1 DB0 (LSB) CSLSB WR LDAC VDD RFB VOUT CSMSB LCCC TOP VIEW (NOT TO SCALE) 20 19123 18 14 15 16 17 4 5 6 7 8 9 10 11 12 13 AGND (MSB) DB7 DB6 DB5 DB4 CSMSB CSLSB WR LDAC VDD R F B V O U T V S S R O F S R E F O U T AD7248A (L S B ) D B 0 D B 1 D B 2 D G N D D B 3 PLCC AGND (MSB) DB7 DB6 DB5 DB4 CSMSB CSLSB WR LDAC VDD R F B V O U T V S S R O F S R E F O U T 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 TOP VIEW (NOT TO SCALE) PIN 1 IDENTIFIER AD7248A (L S B ) D B 0 D B 1 D B 2 D G N D D B 3 3

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AD7245A/AD7248A REV. B –7– Typical Performance Characteristics– TEMPERATURE – C 5 4 0 –55 70 P O W E R S U P P LY C U R R E N T – m A –25 0 3 85 125 6 7 VDD = +15VIDD (VSS = –15V, VIN = V INL OR VINH) IDD (VSS = –15V, VIN = 0V OR VDD) IDD (VSS = 0V, V IN = 0V OR VDD) ISS (VSS = –15V) 2 1 25 TPC 1. Power Supply Current vs. Temperature FREQUENCY – Hz 100 50 10 50 2k100 n V H z 200 500 1k 20 20k5k 10k 50k 200 500 VDD = 15V VSS = 0V TA = 25C OUTPUT WITH ALL 0s ON DAC REFERENCE (DECOUPLED*) REFERENCE (NO DECOUPLING) *REFERENCE DECOUPLING COMPONENTS AS PER FIGURE 8 TPC 2. Noise Spectral Density vs. Frequency 100 90 10 0% 1mV 1s2V TPC 3. Positive-Going Settling Time (VDD = +15 V, VSS = –15 V) TEMPERATURE – C 5.005 5.010 –55 R E F E R E N C E V O L T A G E – V o lt s –25 0 25 70 85 125 5.000 4.995 TPC 4. Reference Voltage vs. Temperature 2k200 10k FREQUENCY – Hz 60 40 0 50 100 P S R R – d B 1k 20 20k 100k 80 *POWER SUPPLY DECOUPLING CAPACITORS ARE 10F AND 0.1F OUTPUT WITH ALL 0s ON DAC OUTPUT WITH ALL 1s ON DAC VDD = 15V WITH 100mV p-p SIGNAL DECOUPLING* NO DECOUPLING DECOUPLING NO DECOUPLING TPC 5. Power Supply Rejection Ration vs. Frequency 100 90 10 0% 1mV 1s2V TPC 6. Negative Going Settling Time (VDD = +15 V, VSS = –15 V)

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AD7245A/AD7248A REV. B–8– CIRCUIT INFORMATION D/A SECTION The AD7245A/AD7248A contains a 12-bit voltage mode digi- tal-to-analog converter. The output voltage from the converter has the same positive polarity as the reference voltage allowing single supply operation. The reference voltage for the DAC is provided by an on-chip buried Zener diode. The DAC consists of a highly stable, thin-film, R–2R ladder and twelve high-speed NMOS single-pole, double-throw switches. The simplified circuit diagram for this DAC is shown in Figure 1. R R R R R 2R 2R 2R 2R 2R2R DB0 DB1 DB9 DB10 DB11 VOUT RFB 2R2R ROFS AGND VREF SHOWN FOR ALL 1s ON DAC Figure 1. D/A Simplified Circuit Diagram The input impedance of the DAC is code dependent and can vary from 8 kΩ to infinity. The input capacitance also varies with code, typically from 50 pF to 200 pF. OP AMP SECTION The output of the voltage mode D/A converter is buffered by a noninverting CMOS amplifier. The user has access to two gain setting resistors which can be connected to allow different out- put voltage ranges (discussed later). The buffer amplifier is capable of developing up to 10 V across a 2 kΩ load to GND. The output amplifier can be operated from a single positive power supply by tying VSS = AGND = 0 V. The amplifier can also be operated from dual supplies to allow a bipolar output range of –5 V to +5 V. The advantages of having dual supplies for the unipolar output ranges are faster settling time to voltages near 0 V, full sink capability of 2.5 mA maintained over the entire output range and elimination of the effects of negative offset on the transfer characteristic (outlined previously). Figure 2 shows the sink capability of the amplifier for single supply operation. OUTPUT VOLTAGE – Volts 5 2 0 0 61 I S IN K – m A 2 3 4 5 7 8 9 10 1 3 4 TA = T MIN TO T MAX Figure 2. Typical Single Supply Sink Current vs. Output Voltage The small signal (200 mV p-p) bandwidth of the output buffer amplifier is typically 1 MHz. The output noise from the ampli- fier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz. The broadband noise from the amplifier has a typical peak-to- peak figure of 150 µV for a 1 MHz output bandwidth. There is no significant difference in the output noise between single and dual supply operation. VOLTAGE REFERENCE The AD7245A/AD7248A contains an internal low noise buried Zener diode reference which is trimmed for absolute accuracy and temperature coefficient. The reference is internally connected to the DAC. Since the DAC has a variable input impedance at its reference input the Zener diode reference is buffered. This buffered reference is available to the user to drive the circuitry required for bipolar output ranges. It can be used as a reference for other parts in the system provided it is externally buffered. The reference will give long-term stability comparable with the best discrete Zener reference diodes. The performance of the AD7245A/AD7248A is specified with internal reference, and all the testing and trimming is done with this reference. The reference should be decoupled at the REF OUT pin and recommended decoupling components are 10 µF and 0.1 µF capacitors in series with a 10 Ω resistor. A simplified schematic of the refer- ence circuitry is shown in Figure 3. VDD TO DAC AGND REF OUT IC IS TEMPERATURE COMPENSATION CURRENT V-TO-I IC Figure 3. Internal Reference DIGITAL SECTION The AD7245A/AD7248A digital inputs are compatible with either TTL or 5 V CMOS levels. All data inputs are static pro- tected MOS gates with typical input currents of less than 1 nA. The control inputs sink higher currents (150 µA max) as a result of the fast digital interfacing. Internal input protection of all logic inputs is achieved by on-chip distributed diodes. The AD7245A/AD7248A features a very low digital feedthrough figure of 10 nV-s in a 5 V output range. This is due to the volt- age mode configuration of the DAC. Most of the impulse is actually as a result of feedthrough across the package. INTERFACE LOGIC INFORMATION—AD7245A Table I shows the truth table for AD7245A operation. The part contains two 12-bit latches, an input latch and a DAC latch. CS and WR control the loading of the input latch while LDAC controls the transfer of information from the input latch to the DAC latch. All control signals are level triggered; and therefore, either or both latches may be made transparent, the input latch by keeping CS and WR “LOW”, the DAC latch by keeping LDAC “LOW.” Input data is latched on the rising edge of WR.

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AD7245A/AD7248A REV. B –9– The data held in the DAC latch determines the analog output of the converter. Data is latched into the DAC latch on the rising edge of LDAC. This LDAC signal is an asynchronous signal and is independent of WR. This is useful in many applications. However, in systems where the asynchronous LDAC can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. For example, if LDAC goes LOW while WR is “LOW,” then the LDAC signal must stay LOW for t7 or longer after WR goes high to ensure correct data is latched through to the output. Table I. AD7245A Truth Table CLR LDAC WR CS Function H L L L Both Latches are Transparent H H H X Both Latches are Latched H H X H Both Latches are Latched H H L L Input Latches Transparent H H g L Input Latches Latched H L H H DAC Latches Transparent H g H H DAC Latches Latched L X X X DAC Latches Loaded with all 0s g H H H DAC Latches Latched with All 0s and Output Remains at 0 V or –5 V g L L L Both Latches are Transparent and Output Follows Input Data H = High State, L = Low State, X = Don’t Care The contents of the DAC latch are reset to all 0s by a low level on the CLR line. With both latches transparent, the CLR line functions like a zero override with the output brought to 0 V in the unipolar mode and –5 V in the bipolar mode for the dura- tion of the CLR pulse. If both latches are latched, a “LOW” pulse on the CLR input latches all 0s into the DAC latch and the output remains at 0 V (or –5 V) after the CLR line has returned “HIGH.” The CLR line can be used to ensure power-up to 0 V on the AD7245A output in unipolar operation and is also use- ful, when used as a zero override, in system calibration cycles. Figure 4 shows the input control logic for the AD7245A and the write cycle timing for the part is shown in Figure 5. LDAC CLR WR CS DAC LATCH INPUT LATCH INPUT DATA Figure 4. AD7245A Input Control Logic CS WR LDAC DATA VALID DATA 5V 0V 5V 0V 5V 0V 5V 0V t3 t4 t5 t6 HIGH IMPEDANCE BUS NOTES 1. SEE TIMING SPECIFICATIONS. 2. ALL INPUT RISE AND FALL TIMES MEASURES FROM 10% TO 90% OF 5V, tr = tf = 5ns. 3. TIMING MEASUREMENT REFERENCE LEVEL IS VINH + V INL 2 4. IF LDAC IS ACTIVATED WHILE WR IS LOW, LDAC MUST STAY t1 t2 t7 LOW FOR t7 OR LONGER AFTER WR GOES HIGH. Figure 5. AD7245A Write Cycle Timing Diagram INTERFACE LOGIC INFORMATION—AD7248A The input loading structure on the AD7248A is configured for interfacing to microprocessors with an 8-bit wide data bus. The part contains two 12-bit latches—an input latch and a DAC latch. Only the data held in the DAC latch determines the ana- log output from the converter. The truth table for AD7248A operation is shown in Table II, while the input control logic diagram is shown in Figure 6. LDAC CSMSB CSLSB WR DAC LATCH UPPER 4 BITS OF INPUT LATCH LOWER 8 BITS OF INPUT LATCH DB7 – DB0 12 4 8 8 Figure 6. AD7248A Input Control Logic CSMSB, CSLSB and WR control the loading of data from the external data bus to the input latch. The eight data inputs on the AD7248A accept right justified data. This data is loaded to the input latch in two separate write operations. CSLSB and WR control the loading of the lower 8-bits into the 12-bit wide latch. The loading of the upper 4-bit nibble is controlled by CSMSB and WR. All control inputs are level triggered, and input data for either the lower byte or upper 4-bit nibble is latched into the input latches on the rising edge of WR (or either CSMSB or CSLSB). The order in which the data is loaded to the input latch (i.e., lower byte or upper 4-bit nibble first) is not important.

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Abel*****erson

May 22, 2020

good item, quick delivery, prefer to recommended.

Cor***** Tara

May 22, 2020

Excellent safe and secure packing. Fast ship out. Thanks

Mack*****erwood

May 15, 2020

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Garret*****amaniam

May 3, 2020

Great capacitors. very fast post very good communication.

Libe*****Xiong

May 1, 2020

Good! quick and convenient delivery. product tracking with good advice.

Nicko*****olland

April 23, 2020

These are high quality connectors. They work as you would expect them to. There is not much else you can say about them.

Mae*****mirez

April 22, 2020

Used it on my system it works perfect as I need.

Ansl*****arikh

April 16, 2020

Item sent as described. Showed up quickly. Worked as it said and would recommend again.

Zaniy*****ayton

April 9, 2020

You get the most update products online. You always give me the best choice.

Bayl*****aniel

April 9, 2020

Perfect, functional, arrived a weeks earlier, excellent Seller. Recommended

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