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AD7822BR

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AD7822BR

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Part Number AD7822BR
Manufacturer Analog Devices Inc.
Description IC ADC 8BIT 1CH 2MSPS 20-SOIC
Datasheet AD7822BR Datasheet
Package 20-SOIC (0.295", 7.50mm Width)
In Stock 558 piece(s)
Unit Price $ 9.2500 *
Lead Time Can Ship Immediately
Estimated Delivery Time Nov 2 - Nov 7 (Choose Expedited Shipping)
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Part Number # AD7822BR (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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AD7822BR Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet AD7822BRDatasheet
Package20-SOIC (0.295", 7.50mm Width)
Series-
Number of Bits8
Sampling Rate (Per Second)2M
Number of Inputs1
Input TypeSingle Ended
Data InterfaceParallel
ConfigurationMUX-S/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitecturePipelined
Reference TypeExternal, Internal
Voltage - Supply, Analog2.7 V ~ 3.3 V, 5V
Voltage - Supply, Digital2.7 V ~ 3.3 V, 5V
Features-
Operating Temperature-40°C ~ 85°C
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC
Mounting Type-

AD7822BR Datasheet

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3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel Sampling ADCs AD7822/AD7825/AD7829 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES 8-bit half-flash ADC with 420 ns conversion time One, four, and eight single-ended analog input channels Available with input offset adjust On-chip track-and-hold SNR performance given for input frequencies up to 10 MHz On-chip reference (2.5 V) Automatic power-down at the end of conversion Wide operating supply range 3 V ± 10% and 5 V ± 10% Input ranges 0 V to 2 V p-p, VDD = 3 V ± 10% 0 V to 2.5 V p-p, VDD = 5 V ± 10% Flexible parallel interface with EOC pulse to allow standalone operation APPLICATIONS Data acquisition systems, DSP front ends Disk drives Mobile communication systems, subsampling applications GENERAL DESCRIPTION The AD7822/AD7825/AD7829 are high speed, 1-, 4-, and 8-channel, microprocessor-compatible, 8-bit analog-to-digital converters with a maximum throughput of 2 MSPS. The AD7822/ AD7825/AD7829 contain an on-chip reference of 2.5 V (2% tolerance); a track-and-hold amplifier; a 420 ns, 8-bit half- flash ADC; and a high speed parallel interface. The converters can operate from a single 3 V ± 10% and 5 V ± 10% supply. The AD7822/AD7825/AD7829 combine the convert start and power-down functions at one pin, that is, the CONVST pin. This allows a unique automatic power-down at the end of a conversion to be implemented. The logic level on the CONVST pin is sampled after the end of a conversion when an EOC (end of conversion) signal goes high. If it is logic low at that point, the ADC is powered down. The AD7822 and AD7825 also have a separate power-down pin (see the Operating Modes section). The parallel interface is designed to allow easy interfacing to microprocessors and DSPs. Using only address decoding logic, the parts are easily mapped into the microprocessor address space. The EOC pulse allows the ADCs to be used in a stand- alone manner (see the Parallel Interface section.) FUNCTIONAL BLOCK DIAGRAM CONVST PARALLEL PORT VREF IN/OUT EOC RDCSAGNDVMID A01 A11 A22 VIN1 VIN24 VIN34 VIN44 VIN55 VIN65 VIN75 VIN85 COMP PD3 2.5V REF VDD CONTROL LOGIC DGND INPUT MUX T/H BUF DB0 DB7 1A0, A1 AD7825/AD7829 2A2 AD7829 3PD AD7822/AD7825 4VIN2 TO VIN4 AD7825/AD7829 5VIN5 TO VIN8 AD7829 8-BIT HALF FLASH ADC 0 13 21 -0 01 Figure 1. The AD7822 and AD7825 are available in 20-lead and 24-lead, 0.3" wide, plastic dual in-line packages (PDIP); 20-lead and 24-lead standard small outline packages (SOIC); and 20-lead and 24-lead thin shrink small outline packages (TSSOP). The AD7829 is available in a 28-lead, 0.6" wide PDIP; a 28-lead SOIC; and a 28-lead TSSOP. PRODUCT HIGHLIGHTS 1. Fast Conversion Time. The AD7822/AD7825/AD7829 have a conversion time of 420 ns. Faster conversion times maximize the DSP processing time in a real-time system. 2. Analog Input Span Adjustment. The VMID pin allows the user to offset the input span. This feature can reduce the requirements of single-supply op amps and take into account any system offsets. 3. FPBW (Full Power Bandwidth) of Track-and-Hold. The track-and-hold amplifier has an excellent high frequency performance. The AD7822/AD7825/AD7829 are capable of converting full-scale input signals up to a frequency of 10 MHz. This makes the parts ideally suited to subsampling applications. 4. Channel Selection. Channel selection is made without the necessity of writing to the part.

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AD7822/AD7825/AD7829 Rev. C | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ....................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Terminology ...................................................................................... 8 Circuit Information........................................................................ 10 Circuit Description..................................................................... 10 Typical Connection Diagram ................................................... 10 ADC Transfer Function............................................................. 11 Analog Input ............................................................................... 11 Power-Up Times......................................................................... 14 Power vs. Throughput................................................................ 15 Operating Modes........................................................................ 15 Parallel Interface......................................................................... 17 Microprocessor Interfacing........................................................... 18 AD7822/AD7825/AD7829 to 8051 ......................................... 18 AD7822/AD7825/AD7829 to PIC16C6x/PIC16C7x................ 18 AD7822/AD7825/AD7829 to ADSP-21xx ............................. 18 Interfacing Multiplexer Address Inputs .................................. 18 AD7822 Standalone Operation ................................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 25 REVISION HISTORY 8/06—Rev. B to Rev. C Changes to General Description .................................................... 1 Changes to Table 1............................................................................ 3 Changes to Typical Connection Diagram Section ..................... 10 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 25 10/01—Rev. A to Rev. B Changes to Power Requirements.................................................... 3 Changes to Pin Function Description ........................................... 5 Changes to Circuit Description ...................................................... 7 Changes to Typical Connection Diagram Section........................7 Changes to Analog Input Section....................................................8 Changes to Analog Input Selection Section...................................9 Changes to Power-Up Times Section .......................................... 10 Changes to Power vs. Throughput Section ................................. 11 Added AD7822 Stand-Alone Operation section ....................... 15 12/99—Rev. 0 to Rev. A

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AD7822/AD7825/AD7829 Rev. C | Page 3 of 28 SPECIFICATIONS VDD = 3 V ± 10%, VDD = 5 V ± 10%, GND = 0 V, VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted. Table 1. Parameter Version B Unit Test Condition/Comment DYNAMIC PERFORMANCE fIN = 30 kHz, fSAMPLE = 2 MHz Signal to (Noise + Distortion) Ratio1 48 dB min Total Harmonic Distortion1 −55 dB max Peak Harmonic or Spurious Noise1 −55 dB max Intermodulation Distortion1 fa = 27.3 kHz, fb = 28.3 kHz Second-Order Terms −65 dB typ Third-Order Terms −65 dB typ Channel-to-Channel Isolation1 −70 dB typ fIN = 20 kHz DC ACCURACY Resolution 8 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 8 Bits Integral Nonlinearity (INL)1 ±0.75 LSB max Differential Nonlinearity (DNL)1 ±0.75 LSB max Gain Error1 ±2 LSB max Gain Error Match1 ±0.1 LSB typ Offset Error1 ±1 LSB max Offset Error Match1 ±0.1 LSB typ ANALOG INPUTS2 See Analog Input section VDD = 5 V ± 10% Input voltage span = 2.5 V VIN1 to VIN8 Input Voltage VDD V max 0 V min VMID Input Voltage VDD − 1.25 V max Default VMID = 1.25 V 1.25 V min VDD = 3 V ± 10% Input voltage span = 2 V VIN1 to VIN8 Input Voltage VDD V max 0 V min VMID Input Voltage VDD − 1 V max Default VMID = 1 V 1 V min VIN Input Leakage Current ±1 μA max VIN Input Capacitance 15 pF max VMID Input Impedance 6 kΩ typ REFERENCE INPUT VREF IN/OUT Input Voltage Range 2.55 V max 2.5 V + 2% 2.45 V min 2.5 V − 2% Input Current 1 μA typ 100 μA max ON-CHIP REFERENCE Nominal 2.5 V Reference Error ±50 mV max Temperature Coefficient 50 ppm/°C typ LOGIC INPUTS Input High Voltage, VINH 2.4 V min VDD = 5 V ± 10% Input Low Voltage, VINL 0.8 V max VDD = 5 V ± 10% Input High Voltage, VINH 2 V min VDD = 3 V ± 10% Input Low Voltage, VINL 0.4 V max VDD = 3 V ± 10% Input Current, IIN ±1 μA max 10 nA typical, VIN = 0 V to VDD Input Capacitance, CIN 10 pF max

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AD7822/AD7825/AD7829 Rev. C | Page 4 of 28 Parameter Version B Unit Test Condition/Comment LOGIC OUTPUTS Output High Voltage, VOH ISOURCE = 200 μA 4 V min VDD = 5 V ± 10% 2.4 V min VDD = 3 V ± 10% Output Low Voltage, VOL ISINK = 200 μA 0.4 V max VDD = 5 V ± 10% 0.2 V max VDD = 3 V ± 10% High Impedance Leakage Current ±1 μA max High Impedance Capacitance 10 pF max CONVERSION RATE Track-and-Hold Acquisition Time 200 ns max See Circuit Description section Conversion Time 420 ns max POWER SUPPLY REJECTION VDD ± 10% ±1 LSB max POWER REQUIREMENTS VDD 4.5 V min 5 V ± 10%; for specified performance 5.5 V max VDD 2.7 V min 3 V ± 10%; for specified performance 3.3 V max IDD Normal Operation 12 mA max 8 mA typical Power-Down 5 μA max Logic inputs = 0 V or VDD 0.2 μA typ Power Dissipation VDD = 3 V Normal Operation 36 mW max 24 mW typical Power-Down 200 kSPS 9.58 mW typ 500 kSPS 23.94 mW typ 1 See the Terminology section of this data sheet. 2 Refer to the Analog Input section for an explanation of the analog input(s).

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AD7822/AD7825/AD7829 Rev. C | Page 5 of 28 TIMING CHARACTERISTICS VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted. Table 2. Parameter1, 2 5 V ± 10% 3 V ± 10% Unit Conditions/Comments t1 420 420 ns max Conversion time t2 20 20 ns min Minimum CONVST pulse width t3 30 30 ns min Minimum time between the rising edge of RD and the next falling edge of convert star t4 110 110 ns max EOC pulse width 70 70 ns min t5 10 10 ns max RD rising edge to EOC pulse high t6 0 0 ns min CS to RD setup time t7 0 0 ns min CS to RD hold time t8 30 30 ns min Minimum RD pulse width t93 10 20 ns max Data access time after RD low t104 5 5 ns min Bus relinquish time after RD high 20 20 ns max t11 10 10 ns min Address setup time before falling edge of RD t12 15 15 ns min Address hold time after falling edge of RD t13 200 200 ns min Minimum time between new channel selection and convert start tPOWER UP 25 25 μs typ Power-up time from rising edge of CONVST using on-chip reference tPOWER UP 1 1 μs max Power-up time from rising edge of CONVST using external 2.5 V reference 1 Sample tested to ensure compliance. 2 See Figure 24, Figure 25, and Figure 26. 3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and time required for an output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitances. TIMING DIAGRAM 200µA IOL 200µA IOH 2.1VTO OUTPUT PIN CL 50pF 01 3 21 -0 0 2 Figure 2. Load Circuit for Access Time and Bus Relinquish Time

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AD7822/AD7825/AD7829 Rev. C | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VDD to AGND −0.3 V to +7 V VDD to DGND −0.3 V to +7 V Analog Input Voltage to AGND VIN1 to VIN8 −0.3 V to VDD + 0.3 V Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V VMID Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C PDIP Package, Power Dissipation 450 mW θJA Thermal Impedance 105°C/W Lead Temperature, (Soldering, 10 sec) 260°C SOIC Package, Power Dissipation 450 mW θJA Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C TSSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 128°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

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AD7822/AD7825/AD7829 Rev. C | Page 7 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DB2 1 DB1 2 DB0 3 CONVST 4 DB320 DB419 DB518 DB617 CS 5 RD 6 DGND 7 DB716 AGND15 VDD14 EOC 8 VREF IN/OUT13 PD 9 VMID12 NC 10 VIN111 NC = NO CONNECT AD7822 TOP VIEW (Not to Scale) 0 13 21 -0 03 DB2 1 DB1 2 DB0 3 CONVST 4 DB324 DB423 DB522 DB621 CS 5 DB720 RD 6 AGND19 DGND 7 VDD18 EOC 8 VREF IN/OUT17 A1 9 VMID16 A0 10 VIN115 PD 11 VIN214 VIN4 12 VIN313 AD7825 TOP VIEW (Not to Scale) 01 32 1- 0 04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DB1 DB0 CONVST DGND RD CS DB2 DB4 DB5 DB6 VDD AGND DB7 EOC A2 A1 VIN6 VIN8 A0 VREF IN/OUT VMID VIN1 VIN5 VIN7 VIN4 VIN3 VIN2 DB3 AD7829 TOP VIEW (Not to Scale) 0 13 21 -0 0 5 Figure 3. Pin Configuration Figure 4. Pin Configuration Figure 5. Pin Configuration Table 4. Pin Function Descriptions Mnemonic Description VIN1 to VIN8 Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight analog input channels, respectively. The inputs have an input span of 2.5 V and 2 V depending on the supply voltage (VDD). This span can be centered anywhere in the range AGND to VDD using the VMID pin. The default input range (VMID unconnected) is AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V ± 10%). See the Analog Input section of the data sheet for more information. VDD Positive Supply Voltage, 3 V ± 10% and 5 V ± 10%. AGND Analog Ground. Ground reference for track-and-hold, comparators, reference circuit, and multiplexer. DGND Digital Ground. Ground reference for digital circuitry. CONVST Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The falling edge of this signal places the track-and-hold in hold mode. The track-and-hold goes into track mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of a conversion. If it is logic low, the AD7822/ AD7825/AD7829 powers down (see the Operating Modes section of the data sheet). EOC Logic Output. The end-of-conversion signal indicates when a conversion has finished. The signal can be used to interrupt a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section). CS Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7822/AD7825/AD7829. This is necessary if the ADC is sharing a common data bus with another device. PD Logic Input. The power-down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low places the AD7822 and AD7825 in power-down mode. The ADCs power up when PD is brought logic high again. RD Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic low to enable the data bus. A0 to A2 Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD signal goes low. DB0 to DB7 Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when both RD and CS go active low. VREF IN/OUT Analog Input and Output. An external reference can be connected to the AD7822/AD7825/AD7829 at this pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 μF capacitor. VMID The VMID pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog Input section).

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AD7822/AD7825/AD7829 Rev. C | Page 8 of 28 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the analog-to-digital converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for an 8-bit converter, this is 50 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7822/AD7825/AD7829, it is defined as 1 6532 V VVVVV THD 222 4 22 log20(dB) ++++ = where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, … . Intermodulation terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7822/AD7825/AD7829 are tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second- and third- order terms are of different significance. The second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in decibels (dB). Channel-to-Channel Isolation A measure of the level of crosstalk between channels. It is measured by applying a full-scale 20 kHz sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. The figure given is the worst case across all four or eight channels of the AD7825 and AD7829, respectively. Relative Accuracy or Endpoint Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity The difference between the measured and the ideal one LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the 128th code transition (01111111) to (10000000) from the ideal, that is, VMID. Offset Error Match The difference in offset error between any two channels. Zero-Scale Error The deviation of the first code transition (00000000) to (00000001) from the ideal; that is, VMID − 1.25 V + 1 LSB (VDD = 5 V ± 10%), or VMID − 1.0 V + 1 LSB (VDD = 3 V ± 10%). Full-Scale Error The deviation of the last code transition (11111110) to (11111111) from the ideal; that is, VMID + 1.25 V − 1 LSB (VDD = 5 V ± 10%), or VMID + 1.0 V − 1 LSB (VDD = 3 V ± 10%).

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AD7822/AD7825/AD7829 Rev. C | Page 9 of 28 Gain Error The deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, that is, VREF − 1 LSB, after the offset error has been adjusted out. Gain Error Match The difference in gain error between any two channels. Track-and-Hold Acquisition Time The time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the point at which the track-and-hold returns to track mode. This happens approximately 120 ns after the falling edge of CONVST. It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected VIN input of the AD7822/ AD7825/AD7829. It means that the user must wait for the duration of the track-and-hold acquisition time after a channel change/step input change to VIN before starting another conversion, to ensure that the part operates to specification. PSR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the converter linearity. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value.

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