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LPC1768FBD100,551

LPC1768FBD100,551

LPC1768FBD100,551

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Part Number LPC1768FBD100,551
Manufacturer NXP
Description IC MCU 32BIT 512KB FLASH 100LQFP
Datasheet LPC1768FBD100,551 Datasheet
Package 100-LQFP
In Stock 18,197 piece(s)
Unit Price $ 11.2500 *
Lead Time To be Confirmed
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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LPC1768FBD100,551 Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet LPC1768FBD100,551Datasheet
Package100-LQFP
SeriesLPC17xx
Core ProcessorARM? Cortex?-M3
Core Size32-Bit
Speed100MHz
ConnectivityCAN, Ethernet, I2C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, DMA, I2S, Motor Control PWM, POR, PWM, WDT
Number of I/O70
Program Memory Size512KB (512K x 8)
Program Memory TypeFLASH
EEPROM Size-
RAM Size64K x 8
Voltage - Supply (Vcc/Vdd)2.4 V ~ 3.6 V
Data ConvertersA/D 8x12b, D/A 1x10b
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C (TA)
Mounting Type-
Package / Case100-LQFP
Supplier Device Package100-LQFP (14x14)

LPC1768FBD100,551 Datasheet

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1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The Arm Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The LPC1769 operates at CPU frequencies of up to 120 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins. The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x Arm7-based microcontroller series. For additional documentation, see Section 19 “References”. 2. Features and benefits  Arm Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit (MPU) supporting eight regions is included.  Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).  Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.  On-chip SRAM includes:  32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. LPC1769/68/67/66/65/64/63 32-bit Arm Cortex®-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 9.8 — 4 May 2018 Product data sheet

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage.  Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.  Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays.  Split APB bus allows high throughput with few stalls between the CPU and DMA.  Serial interfaces:  Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on all parts, see Table 2.)  USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see Table 2.)  Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.  CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.)  SPI controller with synchronous, serial, full duplex communication and programmable data length.  Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.  Three enhanced I2C bus interfaces, one with an open-drain output supporting full I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.  I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. (Not available on all parts, see Table 2.)  Other peripherals:  70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.  12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.  10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. (Not available on all parts, see Table 2)  Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.  One motor control PWM with support for three-phase motor control.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 2 of 93

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Quadrature encoder interface that can monitor one external quadrature encoder.  One standard PWM/timer block with external count input.  RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.  Arm Cortex-M3 system tick timer, including an external clock input option.  Repetitive interrupt timer provides programmable and repeating timed interrupts.  Each peripheral has its own clock divider for further power savings.  Standard JTAG debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options. Boundary Scan Description Language (BSDL) is not available for this device.  Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.  Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Single 3.3 V power supply (2.4 V to 3.6 V).  Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.  Non-maskable Interrupt (NMI) input.  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock.  The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes.  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI).  Brownout detect with separate threshold for interrupt and forced reset.  Power-On Reset (POR).  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.  USB PLL for added flexibility.  Code Read Protection (CRP) with different security levels.  Unique device serial number for identification purposes.  Available as LQFP100 (14 mm  14 mm  1.4 mm), TFBGA1001 (9 mm  9 mm  0.7 mm), and WLCSP100 (5.07  5.07  0.53 mm) package. 1. LPC1768/65 only.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 3 of 93

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller3. Applications 4. Ordering information 4.1 Ordering options  eMetering  Alarm systems  Lighting  White goods  Industrial networking  Motor control Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.07  5.07  0.53 mm - LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 Table 2. Ordering options Ty p e n u m b er D ev ic e o rd er p a rt n u m b er F la s h ( kB ) SRAM in kB E th er n et U S B C A N I2 S D A C G P IO M ax im u m C P U o p er at in g f re q u en c y (M H z) C P U A H B S R A M 0 A H B S R A M 1 To ta l LPC1769FBD100 LPC1769FBD100,551 512 32 16 16 64 yes Device/Host/OTG 2 yes yes 70 120 LPC1768FBD100 LPC1768FBD100/CP32 512 32 16 16 64 yes Device/Host/OTG 2 yes yes 70 100 LPC1768FET100 LPC1768FET100Z 512 32 16 16 64 yes Device/Host/OTG 2 yes yes 70 100 LPC1768UK LPC1768UKZ 512 32 16 16 64 yes Device/Host/OTG 2 yes yes 70 100 LPC1767FBD100 LPC1767FBD100,551 512 32 16 16 64 yes no no yes yes 70 100 LPC1766FBD100 LPC1766FBD100,551 256 32 16 16 64 yes Device/Host/OTG 2 yes yes 70 100 LPC1765FBD100 LPC1765FBD100/3271 256 32 16 16 64 no Device/Host/OTG 2 yes yes 70 100 LPC1765FET100 LPC1765FET100,551 256 32 16 16 64 no Device/Host/OTG 2 yes yes 70 100 LPC1764FBD100 LPC1764FBD100,551 128 16 16 - 32 yes Device only 2 no no 70 100 LPC1763FBD100 LPC1763FBD100K 256 32 16 16 64 no no no yes yes 70 100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 4 of 93

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller5. Marking The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC176x: Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Table 3. Device revision table Revision identifier (R) Revision description ‘-’ Initial device revision ‘A’ Second device revision ‘B’ Third device revisionLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 5 of 93

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller6. Block diagram (1) Not available on all parts. See Table 2. Fig 1. Block diagram SRAM 32/64 kB ARM CORTEX-M3 TEST/DEBUG INTERFACE E M U L A T IO N T R A C E M O D U L E FLASH ACCELERATOR FLASH 512/256/128 kB DMA CONTROLLER ETHERNET CONTROLLER WITH DMA(1) USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS XTAL1 XTAL2 RESET clocks and controls JTAG interface debug port USB PHY SSP0 UART2/3 I2S(1) I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM QUADRATURE ENCODER SSP1 UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT PWM1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS 32 kHz OSCILLATOR APB slave group 1APB slave group 0 DAC(1) RTC POWER DOMAIN LPC1769/68/67/ 66/65/64/63 master master master 002aad944 slaveslave slave slave slave ROM slave MULTILAYER AHB MATRIX P0 to P4 SDA2 SCL2 SCK0 SSEL0 MISO0 MOSI0 SCK1 SSEL1 MISO1 MOSI1 RXD2/3 TXD2/3 PHA, PHB INDEX EINT[3:0] AOUT MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT 4 × MAT2 2 × MAT3 2 × CAP2 2 × CAP3 3 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1 RTCX2 VBAT PWM1[7:0] 2 × MAT0/1 2 × CAP0/1 RD1/2 TD1/2 SDA0/1 SCL0/1 AD0[7:0] SCK/SSEL MOSI/MISO 8 × UART1 RXD0/TXD0 P0, P2 PCAP1[1:0] RMII pins USB pins CLKOUT M P U = connected to DMALPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 6 of 93

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller7. Pinning information 7.1 Pinning Fig 2. Pin configuration LQFP100 package Fig 3. Pin configuration TFBGA100 package LPC176xFBD100 50 1 2 5 7 5 5 1 26 76 100 002aad945 002aaf723 LPC1768/65FET100 Transparent top view J G K H F E D C B A 2 4 6 8 101 3 5 7 9 ball A1 index areaLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 7 of 93

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 4. Pin configuration WLCSP100 package Transparent top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 LPC1768UK bump A1 index area aaa-009522 Table 4. Pin allocation table TFBGA100 Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 9 P0[7]/I2STX_CLK/ SCK1/MAT2[1] 10 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] 11 - 12 - Row B 1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 7 VSS 8 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 - Row C 1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7] 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK 7 P4[28]/RX_MCLK/ MAT2[0]/TXD3 8 P0[8]/I2STX_WS/ MISO1/MAT2[2] 9 VSS 10 VDD(3V3) 11 - 12 - Row D 1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/ AOUT/RXD3 4 n.c. 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ TD2/CAP2[1] 8 P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] 9 P2[4]/PWM1[5]/ DSR1/TRACEDATA[1] 10 P2[5]/PWM1[6]/ DTR1/TRACEDATA[0] 11 - 12 - Row E 1 VSSA 2 VDDA 3 VREFP 4 n.c. 5 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 6 P4[29]/TX_MCLK/ MAT2[1]/RXD3 7 P2[3]/PWM1[4]/ DCD1/TRACEDATA[2] 8 P2[6]/PCAP1[0]/ RI1/TRACECLKLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 8 of 93

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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 - Row F 1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/MCABORT/ PWM1[3]/SSEL0 6 P0[18]/DCD1/ MOSI0/MOSI 7 P2[9]/USB_CONNECT/ RXD2 8 P0[16]/RXD1/ SSEL0/SSEL 9 P0[17]/CTS1/ MISO0/MISO 10 P0[15]/TXD1/ SCK0/SCK 11 - 12 - Row G 1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D 5 P1[25]/MCOA1/ MAT1[1] 6 P1[29]/MCOB2/ PCAP1[1]/MAT0[1] 7 VSS 8 P0[21]/RI1/RD1 9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 - Row H 1 P1[30]/VBUS/ AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/ PWM1[2] 4 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] 5 P1[24]/MCI2/ PWM1[5]/MOSI0 6 VDD(REG)(3V3) 7 P0[10]/TXD2/ SDA2/MAT3[0] 8 P2[11]/EINT1/ I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin SymbolLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 9.8 — 4 May 2018 9 of 93

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