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AD7890BN-10

hot AD7890BN-10

AD7890BN-10

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Part Number AD7890BN-10
Manufacturer Analog Devices Inc.
Description IC DAS 12BIT 8CH 24-DIP
Datasheet AD7890BN-10 Datasheet
Package 24-DIP (0.300", 7.62mm)
In Stock 307 piece(s)
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AD7890BN-10 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Data Acquisition - ADCs/DACs - Special Purpose
Datasheet AD7890BN-10 Datasheet
Package24-DIP (0.300", 7.62mm)
Series-
TypeData Acquisition System (DAS)
Resolution (Bits)12 b
Sampling Rate (Per Second)117k
Data InterfaceSerial
Voltage Supply SourceSingle Supply
Voltage - Supply5V
Operating Temperature-40°C ~ 85°C
Mounting TypeThrough Hole
Package / Case24-DIP (0.300", 7.62mm)
Supplier Device Package24-PDIP

AD7890BN-10 Datasheet

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LC2MOS 8-Channel, 12-Bit Serial Data Acquisition System AD7890 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES Fast 12-bit ADC with 5.9 μs conversion time Eight single-ended analog input channels Selection of input ranges: ±10 V for AD7890-10 0 V to 4.096 V for AD7890-4 0 V to 2.5 V for AD7890-2 Allows separate access to multiplexer and ADC On-chip track/hold amplifier On-chip reference High-speed, flexible, serial interface Single supply, low-power operation (50 mW maximum) Power-down mode (75 μW typ) GENERAL DESCRIPTION The AD7890 is an 8-channel 12-bit data acquisition system. The part contains an input multiplexer, an on-chip track/hold amplifier, a high speed 12-bit ADC, a 2.5 V reference, and a high speed, serial interface. The part operates from a single 5 V supply and accepts an analog input range of ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The multiplexer on the part is independently accessible. This allows the user to insert an antialiasing filter or signal conditioning, if required, between the multiplexer and the ADC. This means that one antialiasing filter can be used for all eight channels. Connection of an external capacitor allows the user to adjust the time given to the multiplexer settling to include any external delays in the filter or signal conditioning circuitry. Output data from the AD7890 is provided via a high speed bidirectional serial interface port. The part contains an on-chip control register, allowing control of channel selection, conversion start, and power-down via the serial port. Versatile, high speed logic ensures easy interfacing to serial ports on microcontrollers and digital signal processors. In addition to the traditional dc accuracy specifications such as linearity, full-scale, and offset errors, the AD7890 is also specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio. FUNCTIONAL BLOCK DIAGRAM TRACK/HOLD 2kΩ AD7890 CEXT CONVST MUX OUT SHA IN REF OUT/ REF IN AGND AGND DGND SCLK TFS RFS DATA OUT DATA IN SMODE VIN1 VDD VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 1NO SCALING ON AD7890-2 CLOCK OUTPUT/CONTROL REGISTER 12-BIT ADC MUX 2.5V REFERENCE SIGNAL SCALING1 SIGNAL SCALING1 SIGNAL SCALING1 SIGNAL SCALING1 SIGNAL SCALING1 SIGNAL SCALING1 SIGNAL SCALING1 SIGNAL SCALING1 CLK IN 0 13 57 -0 01 Figure 1. Power dissipation in normal mode is low at 30 mW typical and the part can be placed in a standby (power-down) mode if it is not required to perform conversions. The AD7890 is fabricated in Analog Devices, Inc.’s Linear Compatible CMOS (LC2MOS) process, a mixed technology process that combines precision bipolar circuits with low power CMOS logic. The part is available in a 24-lead, 0.3" wide, plastic or ceramic dual-in-line package or in a 24-lead small outline package (SOIC_W). PRODUCT HIGHLIGHTS 1. Complete 12-Bit Data Acquisition System-on-a-Chip. The AD7890 is a complete monolithic ADC combining an 8-channel multiplexer, 12-bit ADC, 2.5 V reference, and a track/hold amplifier on a single chip. 2. Separate Access to Multiplexer and ADC. The AD7890 provides access to the output of the multiplexer allowing one antialiasing filter for 8 channels— a considerable savings over the 8 antialiasing filters required if the multiplexer is internally connected to the ADC. 3. High Speed Serial Interface. The part provides a high speed serial interface for easy connection to serial ports of microcontrollers and DSP processors.

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AD7890 Rev. C | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 9 Control Register.............................................................................. 10 Theory of Operation ...................................................................... 11 Converter Details........................................................................ 11 Circuit Description..................................................................... 11 Track/Hold Amplifier ................................................................ 12 Reference ..................................................................................... 13 Timing and Control ................................................................... 13 CEXT Functioning......................................................................... 16 Serial Interface ................................................................................ 17 Self-Clocking Mode ................................................................... 17 External Clocking Mode ........................................................... 18 Simplifying the Interface ........................................................... 19 Microprocessor/Microcontroller Interface ................................. 20 AD7890 to 8051 Interface ......................................................... 20 AD7890 to 68HC11 Interface ................................................... 20 AD7890 to ADSP-2101 Interface ............................................. 21 AD7890 to DSP56000 Interface ............................................... 21 AD7890 to TMS320C25/30 Interface...................................... 21 Antialiasing Filter ....................................................................... 22 Performance .................................................................................... 23 Linearity....................................................................................... 23 Noise ............................................................................................ 23 Dynamic Performance............................................................... 24 Effective Number of Bits ........................................................... 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 27 REVISION HISTORY 9/06—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Table 1............................................................................ 3 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 27 2/01—Rev. A to Rev. B

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AD7890 Rev. C | Page 3 of 28 SPECIFICATIONS VDD = 5 V, AGND = DGND = 0 V, REF IN = 2.5 V, fCLK IN = 2.5 MHz external, MUX OUT connect to SHA IN. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter A Versions1 B Versions S Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE Using external CONVST, any channel Signal to (Noise + Distortion) Ratio2 70 70 70 dB min fIN = 10 kHz sine wave, fSAMPLE = 100 kHz3 Total Harmonic Distortion (THD)2 −77 −77 −77 dB max fIN = 10 kHz sine wave, fSAMPLE = 100 kHz3 Peak Harmonic or Spurious Noise2 −78 −78 −78 dB max fIN = 10 kHz sine wave, fSAMPLE = 100 kHz3 Intermodulation Distortion fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 100 kHz3 2nd Order Terms −80 −80 −80 dB typ 3rd Order Terms −80 −80 −80 dB typ Channel-to-Channel Isolation2 −80 −80 −80 dB max fIN = 1 kHz sine wave DC ACCURACY Resolution 12 12 12 Bits Min. Resolution for Which No Missing Codes Are Guaranteed 12 12 12 Bits Relative Accuracy2 ±1 ±0.5 ±1 LSB max Differential Nonlinearity2 ±1 ±1 ±1 LSB max Positive Full-Scale Error2 ±2.5 ±2.5 ±2.5 LSB max Full-Scale Error Match4 2 2 2 LSB max AD7890-2, AD7890-4 Unipolar Offset Error2 ±2 ±2 ±2 LSB max Unipolar Offset Error Match 2 2 2 LSB max AD7890-10 Only Negative Full-Scale Error2 ±2 ±2 ±2 LSB max Bipolar Zero Error2 ±5 ±5 ±5 LSB max Bipolar Zero Error Match 2 2 2 LSB max ANALOG INPUTS AD7890-10 Input Voltage Range ±10 ±10 ±10 Volts Input Resistance 20 20 20 kΩ min AD7890-4 Input Voltage Range 0 to 4.096 0 to 4.096 0 to 4.096 Volts Input Resistance 11 11 11 kΩ min AD7890-2 Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Input Current 50 50 200 nA max MUX OUT OUTPUT Output Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Output Resistance AD7890-10, AD7890-4 3/5 3/5 3/5 kΩ min/kΩ max AD7890-2 2 2 2 kΩ max Assuming VIN is driven from low impedance SHA IN INPUT Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Input Current ±50 ±50 ±50 nA max REFERENCE OUTPUT/INPUT REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5% Input Impedance 1.6 1.6 1.6 kΩ min Resistor connected to internal reference node Input Capacitance5 10 10 10 pF max REF OUT Output Voltage 2.5 2.5 2.5 V nom REF OUT Error @ 25°C ±10 ±10 ±10 mV max TMIN to TMAX ±20 ±20 ±25 mV max REF OUT Temperature Coefficient 25 25 25 ppm/°C typ REF OUT Output Impedance 2 2 2 kΩ nom

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AD7890 Rev. C | Page 4 of 28 Parameter A Versions1 B Versions S Version Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 2.4 V min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 0.8 0.8 V max VDD = 5 V ± 5% Input Current, IIN ±10 ±10 ±10 μA max VIN = 0 V to VDD Input Capacitance, CIN5 10 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH 4.0 4.0 4.0 V min ISOURCE = 200 μA Output Low Voltage, VOL 0.4 0.4 0.4 V max ISINK = 1.6 mA Serial Data Output Coding AD7890-10 Twos Complement AD7890-4 Straight (Natural) Binary AD7890-2 Straight (Natural) Binary CONVERSION RATE Conversion Time 5.9 5.9 5.9 μs max fCLK IN = 2.5 MHz, MUX OUT, connected to SHA IN Track/Hold Acquisition Time2, 5 2 2 2 μs max POWER REQUIREMENTS VDD 5 5 5 V nom ± 5% for specified performance IDD (Normal Mode) 10 10 10 mA max Logic inputs = 0 V or VDD IDD (Standby Mode)6 @ 25°C 15 15 15 μA typ Logic inputs = 0 V or VDD Power Dissipation Normal Mode 50 50 50 mW max Typically 30 mW Standby Mode @ 25°C 75 75 75 μW typ 1 Temperature ranges are as follows: A, B Versions: −40°C to +85°C; S Version: −55°C to +125°C. 2 See the Terminology section. 3 This sample rate is only achievable when using the part in external clocking mode. 4 Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10. 5 Sample tested @ 25°C to ensure compliance. 6 Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current.

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AD7890 Rev. C | Page 5 of 28 TIMING SPECIFICATIONS VDD = 5 V ± 5%, AGND = DGND = 0 V, REF IN = 2.5 V, fCLK IN = 2.5 MHz external, MUX OUT connected to SHA IN. Parameter1 , 2 Limit at TMIN, TMAX (A, B, S Versions) Unit Conditions/Comments fCLKIN 3 100 kHz min Master Clock Frequency. For specified performance. 2.5 MHz max tCLKIN IN LO 0.3 × tCLK IN ns min Master Clock Input Low Time. tCLK IN HI 0 3 × tCLK IN ns min Master Clock Input High Time. tr4 25 ns max Digital Output Rise Time. Typically 10 ns. tf4 25 ns max Digital Output Fall Time. Typically 10 ns. tCONVERT 5.9 μs max Conversion Time. tCST 100 ns min CONVST Pulse Width. Self-Clocking Mode t1 tCLK IN HI + 50 ns max RFS Low to SCLK Falling Edge. t2 5 25 ns max RFS Low to Data Valid Delay. t3 tCLK IN HI ns nom SCLK High Pulse Width. t4 tCLK IN LO ns nom SCLK Low Pulse Width. t55 20 ns max SCLK Rising Edge to Data Valid Delay. t6 40 ns max SCLK Rising Edge to RFS Delay. t7 6 50 ns max Bus Relinquish Time after Rising Edge of SCLK. t8 0 ns min TFS Low to SCLK Falling Edge. tCLK IN + 50 ns max t9 0 ns min Data Valid to TFS Falling Edge Setup Time (A2 Address Bit). t10 20 ns min Data Valid to SCLK Falling Edge Setup Time. t11 10 ns min Data Valid to SCLK Falling Edge Hold Time. t12 20 ns min TFS to SCLK Falling Edge Hold Time. External Clocking Mode t13 20 ns min RFS Low to SCLK Falling Edge Setup Time. t145 40 ns max RFS Low to Data Valid Delay. t15 50 ns min SCLK High Pulse Width. t16 50 ns min SCLK Low Pulse Width. t175 35 ns max SCLK Rising Edge to Data Valid Delay. t18 20 ns min RFS to SCLK Falling Edge Hold Time. t196 50 ns max Bus Relinquish Time after Rising Edge of RFS. t19A6 90 ns max Bus Relinquish Time after Rising Edge of SCLK. t20 20 ns min TFS Low to SCLK Falling Edge Setup Time. t21 10 ns min Data Valid to SCLK Falling Edge Setup Time. t22 15 ns min Data Valid to SCLK Falling Edge Hold Time. t23 40 ns min TFS to SCLK Falling Edge Hold Time. 1 Sample tested at −25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 10 to Figure 13. 3 The AD7890 is production tested with fCLK IN at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz. 4 Specified using 10% and 90% points on waveform of interest. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. TO OUTPUT PIN 2.1V 1.6mA 200µA 50pF 0 13 57 -0 0 2 Figure 2. Load Circuit for Access Time and Bus Relinquish Time

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AD7890 Rev. C | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Parameter Rating VDD to AGND −0.3 V to +7 V VDD to DGND −0.3 V to +7 V Analog Input Voltage to AGND AD7890-10, AD7890-4 ±17 V AD7890-2 −5 V, +10 V Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (A, B Versions) −40°C to +85°C Extended (S Version) −55°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C PDIP Package, Power Dissipation 450 mW θJA Thermal Impedance 105°C/W Lead Temperature (Soldering, 10 sec) 260°C CERDIP Package, Power Dissipation 450 mW θJA Thermal Impedance 70°C/W Lead Temperature (Soldering, 10 sec) 300°C SOIC_W Package, Power Dissipation 450 mW θJA Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

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AD7890 Rev. C | Page 7 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 REF OUT/REF IN CONVST TFS RFS DATA OUT DATA IN VDD VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 AD7890 TOP VIEW (Not to Scale) AGND AGND SHA IN MUX OUT DGND CLK IN SCLK CEXT SMODE 01 35 7 -0 0 3 Figure 3. Pin Configuration Table 2. Pin Function Descriptions Pin No. Mnemonic Description 1 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC. 2 SMODE Control Input. Determines whether the part operates in its external clocking (slave) or self-clocking (master) serial mode. With SMODE at a logic low, the part is in its self-clocking serial mode with RFS and SCLK as outputs. This self-clocking mode is useful for connection to shift registers or to serial ports of DSP processors. With SMODE at a logic high, the part is in its external clocking serial mode with SCLK and RFS as inputs. This external clocking mode is useful for connection to the serial port of microcontrollers, such as the 8xC51 and the 68HCxx, and for connection to the serial ports of DSP processors. 3 DGND Digital Ground. Ground reference for digital circuitry. 4 CEXT External Capacitor. An external capacitor is connected to this pin to determine the length of the internal pulse (see the Control Register section). Larger capacitances on this pin extend the pulse to allow for settling time delays through an external antialiasing filter or signal conditioning circuitry. 5 CONVST Convert Start. Edge-triggered logic input. A low-to-high transition on this input puts the track/hold into hold and initiates conversion if the internal pulse has timed out (see the Control Register section). If the internal pulse is active when the CONVST goes high, the track/hold does not proceed to hold until the pulse times out. If the internal pulse times out when CONVST goes high, the rising edge of CONVST drives the track/hold into hold and initiates conversion. 6 CLK IN Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source for the conversion sequence. In the self-clocking serial mode, the SCLK output is derived from this CLK IN pin. 7 SCLK Serial Clock Input. In the external clocking (slave) mode (see the Serial Interface section), this is an externally applied serial clock used to load serial data to the control register and to access data from the output register. In the self-clocking (master) mode, the internal serial clock, which is derived from the clock input (CLK IN), appears on this pin. Once again, it is used to load serial data to the control register and to access data from the output register. 8 TFS Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling edge of this signal. 9 RFS Receive Frame Synchronization Pulse. In the external clocking mode, this pin is an active low logic input with RFS provided externally as a strobe or framing pulse to access serial data from the output register. In the self- clocking mode, it is an active low output, which is internally generated and provides a strobe or framing pulse for serial data from the output register. For applications which require that data be transmitted and received at the same time, RFS and TFS should be connected together. 10 DATA OUT Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three address bits of the control register and the 12 bits of conversion data. Serial data is valid on the falling edge of SCLK for sixteen edges after RFS goes low. Output coding from the ADC is twos complement for the AD7890-10 and straight binary for the AD7890-4 and AD7890-2. 11 DATA IN Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first five bits of serial data are loaded to the control register on the first five falling edges of SCLK after TFS goes low. Serial data on subsequent SCLK edges is ignored while TFS remains low. 12 VDD Positive Supply Voltage, 5 V ± 5%. 13 MUX OUT Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range from this output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The output impedance of this output is nominally 3.5 kΩ. If no external antialiasing filter is required, MUX OUT should be connected to SHA IN.

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AD7890 Rev. C | Page 8 of 28 Pin No. Mnemonic Description 14 SHA IN Track/Hold Input. The input to the on-chip track/hold is applied to this pin. It is a high impedance input and the input voltage range is 0 V to 2.5 V. 15 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC. 16 VIN1 Analog Input Channel 1. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 17 VIN2 Analog Input Channel 2. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 18 VIN3 Analog Input Channel 3. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 19 VIN4 Analog Input Channel 4. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 20 VIN5 Analog Input Channel 5. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 21 VIN6 Analog Input Channel 6. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 22 VIN7 Analog Input Channel 7. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 23 VIN8 Analog Input Channel 8. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to 4.096 V (AD7890-4) and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 24 REF OUT/REF IN Voltage Reference Output/Input. The part can be used with either its own internal reference or with an external reference source. The on-chip 2.5 V reference voltage is provided at this pin. When using this internal reference as the reference source for the part, REF OUT should decoupled to AGND with a 0.1 μF disc ceramic capacitor. The output impedance of this reference source is typically 2 kΩ. When using an external reference source as the reference voltage for the part, the reference source should be connected to this pin. This overdrives the internal reference and provides the reference source for the part. The REF IN input is buffered on-chip. The nominal reference voltage for correct operation of the AD7890 is 2.5 V.

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AD7890 Rev. C | Page 9 of 28 TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7890, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log20)dB( V VVVVV THD ++++ = where: V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7890 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 1 kHz signal to any one of the other seven inputs and determining how much that signal is attenuated in the channel of interest. The figure given is the worst case across all eight channels. Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Positive Full-Scale Error (AD7890-10) This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (4 × REF IN − 1 LSB) after the bipolar zero error has been adjusted out. Positive Full-Scale Error (AD7890-4) This is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal (1.638 × REF IN − 1 LSB) after the unipolar offset error has been adjusted out. Positive Full-Scale Error (AD7890-2) This is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal (REF IN − 1 LSB) after the unipolar offset error has been adjusted out. Bipolar Zero Error (AD7890-10) This is the deviation of the midscale transition (all 0s to all 1s) from the ideal 0 V (AGND). Unipolar Offset Error (AD7890-2, AD7890-4) This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal 0 V (AGND). Negative Full-Scale Error (AD7890-10) This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal (−4 × REF IN + 1 LSB) after bipolar zero error has been adjusted out. Track/Hold Acquisition Time Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected VIN input of the AD7890. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a channel change/step input change to VIN before starting another conversion, to ensure that the part operates to specification.

AD7890BN-10 Reviews

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Juli*****guire

January 15, 2020

The helper is super handy, especially if you work with medium size PCB boards as it allows to hold the board steady in every position. It feels pretty sturdy and of good quality.

Ryl*****Page

October 6, 2019

The capacitors were exactly the ones I wanted. Perfect fit.

Marc*****Jaggi

August 9, 2019

I am very happy with how Heisener do business. Will definitely buy their products in the future as I have confidence in their customer service.

Kassi*****mpton

August 2, 2019

Item works as described, fast delivery, nice contact!

Ces*****Bruce

July 17, 2019

These are high quality connectors. They work as you would expect them to. There is not much else you can say about them.

Mela*****Pope

June 30, 2019

Packing good, very happy with goods, Very fast delivery, good service. Thanks

Huxl*****ethi

June 20, 2019

It's so nice to have all these babies. I was using so many for projects, I decided to buy these. They'll definitely last me a while!

Con***** Rice

May 29, 2019

Excellent shopping cart process, various of products for selection and order fulfillment a good service quality. I rely on them heavily.

Derr*****Bajwa

April 11, 2019

It works fine and does what it has designed for. No regrets.

Fost*****olla

January 29, 2019

Not much to say. Nice and cheap, and haven't had a failure yet.

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