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AD8331ARQZ-R7

hot AD8331ARQZ-R7

AD8331ARQZ-R7

For Reference Only

Part Number AD8331ARQZ-R7
Manufacturer Analog Devices Inc.
Description IC AMP VAR GAIN 1CHAN 20QSOP
Datasheet AD8331ARQZ-R7 Datasheet
Package 20-SSOP (0.154", 3.90mm Width)
In Stock 2000 piece(s)
Unit Price $ 7.2485 *
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AD8331ARQZ-R7 Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Linear - Amplifiers - Special Purpose
Datasheet AD8331ARQZ-R7 Datasheet
Package20-SSOP (0.154", 3.90mm Width)
SeriesX-AMP?
TypeVariable Gain Amplifier
ApplicationsSignal Processing
Mounting TypeSurface Mount
Package / Case20-SSOP (0.154", 3.90mm Width)
Supplier Device Package20-QSOP

AD8331ARQZ-R7 Datasheet

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Ultralow Noise VGAs with Preamplifier and Programmable RIN Data Sheet AD8331/AD8332/AD8334 Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Ultralow noise preamplifier (preamp) Voltage noise = 0.74 nV/√Hz Current noise = 2.5 pA/√Hz 3 dB bandwidth AD8331: 120 MHz AD8332, AD8334: 100 MHz Low power AD8331: 125 mW/channel AD8332, AD8334: 145 mW/channel Wide gain range with programmable postamp −4.5 dB to +43.5 dB in LO gain mode 7.5 dB to 55.5 dB in HI gain mode Low output-referred noise: 48 nV/√Hz typical Active input impedance matching Optimized for 10-bit/12-bit ADCs Selectable output clamping level Single 5 V supply operation AD8332 and AD8334 available in lead frame chip scale package APPLICATIONS Ultrasound and sonar time-gain controls High performance automatic gain control (AGC) systems I/Q signal processing High speed, dual ADC drivers GENERAL DESCRIPTION The AD8331/AD8332/AD8334 are single-, dual-, and quad- channel, ultralow noise linear-in-dB, variable gain amplifiers (VGAs). Optimized for ultrasound systems, they are usable as a low noise variable gain element at frequencies up to 120 MHz. Included in each channel are an ultralow noise preamp (LNA), an X-AMP® VGA with 48 dB of gain range, and a selectable gain postamp with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs. Using a single resistor, the LNA input impedance can be adjusted to match a signal source without compromising noise performance. The 48 dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. FUNCTIONAL BLOCK DIAGRAM 03 19 9- 00 1 VOL VOH VMID LNA 48dB ATTENUATOR ENB INH LMD VINVIPLOPLON GAIN AD8331/AD8332/AD8334 + – CLAMP RCLMP HILOVCM 3.5dB OR 15.5dB 19dB PA VCM BIAS VGA BIAS AND INTERPOLATOR GAIN CONTROL INTERFACE 21dB Figure 1. Signal Path Block Diagram 60 50 40 30 20 10 0 –10 100k 1M 10M 100M 1G G A IN ( d B ) FREQUENCY (Hz) 03 19 9- 00 2 VGAIN = 1V VGAIN = 0.8V VGAIN = 0.6V VGAIN = 0.4V VGAIN = 0.2V VGAIN = 0V HI GAIN MODE Figure 2. Frequency Response vs. Gain Differential signal paths result in superb second- and third- order distortion performance and low crosstalk. The low output-referred noise of the VGA is advantageous in driving high speed differential ADCs. The gain of the postamp can be pin selected to 3.5 dB or 15.5 dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. The output can be limited to a user-selected clamping level, preventing input overload to a subsequent ADC. An external resistor adjusts the clamping level. The operating temperature range is −40°C to +85°C. The AD8331 is available in a 20-lead QSOP package, the AD8332 is available in 28-lead TSSOP and 32-lead LFCSP packages, and the AD8334 is available in a 64-lead LFCSP package.

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AD8331/AD8332/AD8334 Data Sheet Rev. I | Page 2 of 55 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 4 Absolute Maximum Ratings ............................................................ 7 ESD Caution .................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ........................................... 12 Test Circuits ..................................................................................... 20 Measurement Considerations ................................................... 20 Theory of Operation ...................................................................... 24 Overview ...................................................................................... 24 Low Noise Amplifier (LNA) ..................................................... 25 Variable Gain Amplifier ............................................................ 27 Postamplifier ............................................................................... 28 Applications Information .............................................................. 30 LNA—External Components .................................................... 30 Driving ADCs ............................................................................. 32 Overload ...................................................................................... 32 Optional Input Overload Protection ....................................... 32 Layout, Grounding, and Bypassing .......................................... 33 Multiple Input Matching ........................................................... 33 Disabling the LNA ...................................................................... 33 Ultrasound TGC Application ................................................... 34 High Density Quad Layout ....................................................... 34 AD8331 Evaluation Board ............................................................ 39 General Description ................................................................... 39 User-Supplied Optional Components ..................................... 39 Measurement Setup.................................................................... 39 Board Layout ............................................................................... 39 AD8331 Evaluation Board Schematics .................................... 40 AD8331 Evaluation Board PCB Layers ................................... 42 AD8332 Evaluation Board ............................................................ 43 General Description ................................................................... 43 User-Supplied Optional Components ..................................... 43 Measurement Setup.................................................................... 43 Board Layout ............................................................................... 43 Evaluation Board Schematics ................................................... 44 AD8332 Evaluation Board PCB Layers ................................... 46 AD8334 Evaluation Board ............................................................ 47 General Description ................................................................... 47 Configuring the Input Impedance ........................................... 48 Measurement Setup.................................................................... 48 Board Layout ............................................................................... 48 Evaluation Board Schematics ................................................... 49 AD8334 Evaluation Board PCB Layers ................................... 51 Outline Dimensions ....................................................................... 53 Ordering Guide .......................................................................... 55 REVISION HISTORY 5/2016—Rev. H to Rev. I Changes to Figure 5, and Table 5 .................................................... 9 Updated Outline Dimensions ....................................................... 54 Changes to Ordering Guide .......................................................... 55 3/2015—Rev. G to Rev. H Changes to Pin 29 Description; Table 6 ....................................... 11 Updated Figure 123, Figure 124, Figure 125; Outline Dimensions ...................................................................................... 53 Changes to Ordering Guide .......................................................... 55 10/2010—Rev. F to Rev. G Changes to Quiescent Current per Channel Parameter, Table 1 ................................................................................................ 6 Changes to Pin 1, Table 3 ................................................................. 8 Changes to Pin 1 and Pin 28, Table 4 and Pin 4 and Pin 5, Table 5 ................................................................................................ 9 Changes to Figure 6 and Table 6 ................................................... 10 Changes to Figure 33 ...................................................................... 16 Changes to Figure 64 ...................................................................... 22 Changes to Figure 70 ...................................................................... 24 Changes to Low Noise Amplifier (LNA) Section and Figure 74 .......................................................................................... 25 Changes to Figure 94 ...................................................................... 38 Changes to General Descriptions Section, Figure 95 Caption, Table 10, and Board Layout Section ............................................. 39 Changes to Figure 96 ...................................................................... 40 Changes to Figure 97 ...................................................................... 41 Changes to Figure 98 and Figure 103 .......................................... 42 Deleted AD8331 Bill of Materials Section and Table 11; Renumbered Sequentially ............................................................. 43 Changes to Figure 104 ................................................................... 43 Changes to Figure 106 ................................................................... 45 Changes to Figure 107 ................................................................... 46

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Data Sheet AD8331/AD8332/AD8334 Rev. I | Page 3 of 55 Changes to Figure 113 .................................................................... 47 Changes to Figure 114 and Board Layout Section ...................... 48 Deleted AD8332 Bill of Materials Section and Table 13; Renumbered Sequentially .............................................................. 48 Changes to Figure 115 .................................................................... 49 Changes to Figure 116 .................................................................... 50 Changes to Figure 117 to Figure 120 ............................................ 51 Changes to Figure 121 .................................................................... 52 Deleted AD8334 Bill of Materials Section and Table 15; Renumbered Sequentially .............................................................. 54 4/2008—Rev. E to Rev. F Changed RFB to RIZ Throughout...................................................... 4 Changes to Figure 1........................................................................... 1 Changes to Table 1, LNA and VGA Characteristics, Output Offset Voltage, Conditions ............................................................... 4 Changes to Quiescent Current per Channel and Power Down Current Parameters ........................................................................... 6 Changes to Table 2 ............................................................................ 7 Changes to Table 3, Pin 1 Description............................................ 8 Changes to Table 4, Pin 1 and Pin 28 Descriptions ...................... 9 Changes to Table 5, Pin 4 and Pin 5 Descriptions ........................ 9 Changes to Table 6, Pin 2, Pin 15, and Pin 20 Descriptions ...... 10 Changes to Table 6, Pin 61 Description ....................................... 11 Changes to Typical Performance Characteristics Section, Default Conditions .......................................................................... 12 Changes to Figure 25 ...................................................................... 15 Changes to Figure 39 ...................................................................... 17 Changes to Figure 55 Through Figure 68 ................................... 20 Changes to Theory of Operation, Overview Section ................. 24 Changes to Low Noise Amplifier Section and Figure 74 ........... 25 Changes to Active Impedance Matching Section, Figure 75, and Figure 77 ................................................................................... 26 Changes to Figure 78 ...................................................................... 27 Changes to Equation 6, Table 7, Figure 81, and Figure 82 ......... 30 Changes to Figure 83 ...................................................................... 31 Changes to Figure 88 ...................................................................... 32 Switched Figure 89 and Figure 90 ................................................. 33 Changes to Figure 89 ...................................................................... 33 Changes to Ultrasound TGC Application Section ..................... 34 Incorporated AD8331-EVAL Data Sheet, Rev. A ....................... 39 Changes to User-Supplied Optional Components Section and Measurement Setup Section ................................................... 39 Changes to Figure 95 ...................................................................... 39 Changes to Figure 97 ...................................................................... 41 Added Figure 98 .............................................................................. 42 Incorporated AD8332-EVALZ Data Sheet, Rev. D ..................... 44 Incorporated AD8334-EVAL Data Sheet, Rev. 0 ........................ 49 Updated Outline Dimensions ........................................................ 55 Changes to Ordering Guide ........................................................... 57 4/2006—Rev. D to Rev. E Added AD8334 ................................................................... Universal Changes to Figure 1 and Figure 2 .................................................... 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 7 Changes to Figure 7 through Figure 9 and Figure 12 ................. 12 Changes to Figure 13, Figure 14, Figure 16, and Figure 18 ....... 13 Changes to Figure 23 and Figure 24 ............................................. 14 Changes to Figure 25 through Figure 27...................................... 15 Changes to Figure 31 and Figure 33 through Figure 36 ............ 16 Changes to Figure 37 through Figure 42...................................... 17 Changes to Figure 43, Figure 44, and Figure 48 .......................... 18 Changes to Figure 49, Figure 50, and Figure 54 .......................... 19 Inserted Figure 56 and Figure 57 .................................................. 20 Inserted Figure 58, Figure 59, and Figure 61 ............................... 21 Changes to Figure 60 ...................................................................... 21 Inserted Figure 63 and Figure 65 .................................................. 22 Changes to Figure 64 ...................................................................... 22 Moved Measurement Considerations Section ............................ 23 Inserted Figure 67 and Figure 68 .................................................. 23 Inserted Figure 70 and Figure 71 .................................................. 24 Change to Figure 72 ........................................................................ 24 Changes to Figure 73 and Low Noise Amplifier Section ........... 25 Changes to Postamplifier Section ................................................. 28 Changes to Figure 80 ...................................................................... 29 Changes to LNA—External Components Section ...................... 30 Changes to Logic Inputs—ENB, MODE, and HILO Section ... 31 Changes to Output Decoupling and Overload Sections ............ 32 Changes to Layout, Grounding, and Bypassing Section ............ 33 Changes to Ultrasound TGC Application Section ..................... 34 Added High Density Quad Layout Section ................................. 34 Inserted Figure 94 ........................................................................... 38 Updated Outline Dimensions........................................................ 39 Changes to Ordering Guide ........................................................... 40 3/2006—Rev. C to Rev. D Updated Format ................................................................. Universal Changes to Features and General Description .............................. 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 6 Changes to Ordering Guide ........................................................... 34 11/2003—Rev. B to Rev. C Addition of New Part ......................................................... Universal Changes to Figures ............................................................. Universal Updated Outline Dimensions........................................................ 32 5/2003—Rev. A to Rev. B Edits to Ordering Guide ................................................................. 32 Edits to Ultrasound TGC Application Section ........................... 25 Added Figure 71, Figure 72, and Figure 73.................................. 26 Updated Outline Dimensions........................................................ 31 2/2003—Rev. 0 to Rev. A Edits to Ordering Guide ................................................................. 32

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AD8331/AD8332/AD8334 Data Sheet Rev. I | Page 4 of 55 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating, −4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit1 LNA CHARACTERISTICS Gain Single-ended input to differential output 19 dB Input to output (single-ended) 13 dB Input Voltage Range AC-coupled ±275 mV Input Resistance RIZ = 280 Ω 50 Ω RIZ = 412 Ω 75 Ω RIZ = 562 Ω 100 Ω RIZ = 1.13 kΩ 200 Ω RIZ = ∞ 6 kΩ Input Capacitance 13 pF Output Impedance Single-ended, either output 5 Ω −3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 130 MHz Slew Rate 650 V/µs Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.74 nV/√Hz Input Current Noise RIZ = ∞, HI or LO gain, f = 5 MHz 2.5 pA/√Hz Noise Figure f = 10 MHz, LOP output Active Termination Match RS = RIN = 50 Ω 3.7 dB Unterminated RS = 50 Ω, RIZ = ∞ 2.5 dB Harmonic Distortion at LOP1 or LOP2 VOUT = 0.5 V p-p, single-ended, f = 10 MHz HD2 −56 dBc HD3 −70 dBc Output Short-Circuit Current Pin LON, Pin LOP 165 mA LNA AND VGA CHARACTERISTICS −3 dB Small Signal Bandwidth VOUT = 0.2 V p-p AD8331 120 MHz AD8332, AD8334 100 MHz −3 dB Large Signal Bandwidth VOUT = 2 V p-p AD8331 110 MHz AD8332, AD8334 90 MHz Slew Rate AD8331 LO gain 300 V/µs HI gain 1200 V/µs AD8332, AD8334 LO gain 275 V/µs HI gain 1100 V/µs Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.82 nV/√Hz Noise Figure VGAIN = 1.0 V Active Termination Match RS = RIN = 50 Ω, f = 10 MHz, measured 4.15 dB RS = RIN = 200 Ω, f = 5 MHz, simulated 2.0 dB Unterminated RS = 50 Ω, RIZ = ∞, f = 10 MHz, measured 2.5 dB RS = 200 Ω, RIZ = ∞, f = 5 MHz, simulated 1.0 dB Output-Referred Noise AD8331 VGAIN = 0.5 V, LO gain 48 nV/√Hz VGAIN = 0.5 V, HI gain 178 nV/√Hz AD8332, AD8334 VGAIN = 0.5 V, LO gain 40 nV/√Hz VGAIN = 0.5 V, HI gain 150 nV/√Hz Output Impedance, Postamplifier DC to 1 MHz 1 Ω Output Signal Range, Postamplifier RL ≥ 500 Ω, unclamped, either pin VCM ± 1.125 V

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Data Sheet AD8331/AD8332/AD8334 Rev. I | Page 5 of 55 Parameter Test Conditions/Comments Min Typ Max Unit1 Differential 4.5 V p-p Output Offset Voltage AD8331 Differential, VGAIN = 0.5 V −50 ±5 +50 mV Common mode −125 −25 +100 mV AD8332, AD8334 Differential, 0.05 V ≤ VGAIN ≤ 1.0 V −20 ±5 +20 mV Common mode −125 –25 +100 mV Output Short-Circuit Current 45 mA Harmonic Distortion VGAIN = 0.5 V, VOUT = 1 V p-p, HI gain AD8331 HD2 f = 1 MHz −88 dBc HD3 −85 dBc HD2 f = 10 MHz −68 dBc HD3 −65 dBc AD8332, AD8334 HD2 f = 1 MHz −82 dBc HD3 −85 dBc HD2 f = 10 MHz −62 dBc HD3 −66 dBc Input 1 dB Compression Point VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz to 10 MHz 1 dBm Two-Tone Intermodulation Distortion (IMD3) AD8331 VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz −80 dBc VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz −72 dBc AD8332, AD8334 VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz −78 dBc VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz −74 dBc Output Third-Order Intercept AD8331 VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz 38 dBm VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz 33 dBm AD8332, AD8334 VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz 35 dBm VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz 32 dBm Channel-to-Channel Crosstalk (AD8332, AD8334) VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz −98 dB Overload Recovery VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 ns Group Delay Variation 5 MHz < f < 50 MHz, full gain range ±2 ns ACCURACY Absolute Gain Error2 0.05 V < VGAIN < 0.10 V −1 +0.5 +2 dB 0.10 V < VGAIN < 0.95 V −1 ±0.3 +1 dB 0.95 V < VGAIN < 1.0 V −2 −1 +1 dB Gain Law Conformance3 0.1 V < VGAIN < 0.95 V ±0.2 dB Channel-to-Channel Gain Matching 0.1 V < VGAIN < 0.95 V ±0.1 dB GAIN CONTROL INTERFACE (Pin GAIN) Gain Scaling Factor 0.10 V < VGAIN < 0.95 V 48.5 50 51.5 dB/V Gain Range LO gain −4.5 to +43.5 dB HI gain 7.5 to 55.5 dB Input Voltage (VGAIN) Range 0 to 1.0 V Input Impedance 10 MΩ Response Time 48 dB gain change to 90% full scale 500 ns COMMON-MODE INTERFACE (PIN VCMx) Input Resistance4 Current limited to ±1 mA 30 Ω Output CM Offset Voltage VCM = 2.5 V −125 −25 +100 mV Voltage Range VOUT = 2.0 V p-p 1.5 to 3.5 V

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AD8331/AD8332/AD8334 Data Sheet Rev. I | Page 6 of 55 Parameter Test Conditions/Comments Min Typ Max Unit1 ENABLE INTERFACE (PIN ENB, PIN ENBL, PIN ENBV) Logic Level to Enable Power 2.25 5 V Logic Level to Disable Power 0 1.0 V Input Resistance Pin ENB 25 kΩ Pin ENBL 40 kΩ Pin ENBV 70 kΩ Power-Up Response Time VINH = 30 mV p-p 300 µs VINH = 150 mV p-p 4 ms HILO GAIN RANGE INTERFACE (PIN HILO) Logic Level to Select HI Gain Range 2.25 5 V Logic Level to Select LO Gain Range 0 1.0 V Input Resistance 50 kΩ OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR LO GAIN) Accuracy HILO = LO RCLMP = 2.74 kΩ, VOUT = 1 V p-p (clamped) ±50 mV HILO = HI RCLMP = 2.21 kΩ, VOUT = 1 V p-p (clamped) ±75 mV MODE INTERFACE (PIN MODE) Logic Level for Positive Gain Slope 0 1.0 V Logic Level for Negative Gain Slope 2.25 5 V Input Resistance 200 kΩ POWER SUPPLY (PIN VPS1, PIN VPS2, PIN VPSV, PIN VPSL, PIN VPOS) Supply Voltage 4.5 5.0 5.5 V Quiescent Current per Channel AD8331 20 25 mA AD8332 22 27.5 32 mA AD8334 24 29.5 34 Power Dissipation per Channel No signal AD8331 125 mW AD8332, AD8334 138 mW Power-Down Current VGA and LNA disabled AD8331 50 240 400 µA AD8332 50 300 600 µA AD8334 50 600 1200 µA LNA Current AD8331 (ENBL) Each channel 7.5 11 15 mA AD8332, AD8334 (ENBL) Each channel 7.5 12 15 mA VGA Current AD8331 (ENBV) 7.5 14 20 mA AD8332, AD8334 (ENBV) 7.5 17 20 mA PSRR VGAIN = 0 V, f = 100 kHz −68 dB 1 All dBm values are referred to 50 Ω. 2 The absolute gain refers to the theoretical gain expression in Equation 1. 3 Best-fit to linear-in-dB curve. 4 The current is limited to ±1 mA typical.

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Data Sheet AD8331/AD8332/AD8334 Rev. I | Page 7 of 55 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Voltage Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V Input Voltage (INHx) VS + 200 mV ENB, ENBL, ENBV, HILO Voltage VS + 200 mV GAIN Voltage 2.5 V Power Dissipation RU Package1 (AD8332) 0.96 W CP-32 Package (AD8332) 1.97 W RQ Package1 (AD8331) 0.78 W CP-64 Package (AD8334) 0.91 W Temperature Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C θJA RU Package1 (AD8332) 68°C/W CP-32 Package22 (AD8332) 33°C/W RQ Package1 (AD8331) 83°C/W CP-64 Package3 (AD8334) 24.2°C/W 1 4-layer JEDEC board (2S2P). 2 Exposed pad soldered to board, nine thermal vias in pad—JEDEC, 4-layer board J-STD-51-9. 3 Exposed pad soldered to board, 25 thermal vias in pad—JEDEC, 4-layer board J-STD-51-9. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

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AD8331/AD8332/AD8334 Data Sheet Rev. I | Page 8 of 55 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 03 19 9- 00 3MODE VIP GAIN VIN LOP COML LMD LON VPSL INH 1 2 3 4 5 6 7 8 9 10 RCLMP COMM VOH ENBV VCM VPOS VOL HILO ENBL COMM20 19 18 17 16 15 14 13 12 11 AD8331 TOP VIEW (Not to Scale) PIN 1 INDICATOR Figure 3. 20-Lead QSOP Pin Configuration (AD8331) Table 3. 20-Lead QSOP Pin Function Description (AD8331) Pin No. Mnemonic Description 1 LMD LNA Midsupply Bypass Pin; Connect a Capacitor for Midsupply HF Bypass 2 INH LNA Input 3 VPSL LNA 5 V Supply 4 LON LNA Inverting Output 5 LOP LNA Noninverting Output 6 COML LNA Ground 7 VIP VGA Noninverting Input 8 VIN VGA Inverting Input 9 MODE Gain Slope Logic Input 10 GAIN Gain Control Voltage 11 VCM Common-Mode Voltage 12 RCLMP Output Clamping Level 13 HILO Gain Range Select (HI or LO) 14 VPOS VGA 5 V Supply 15 VOH Noninverting VGA Output 16 VOL Inverting VGA Output 17 COMM VGA Ground 18 ENBV VGA Enable 19 ENBL LNA Enable 20 COMM VGA Ground

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Data Sheet AD8331/AD8332/AD8334 Rev. I | Page 9 of 55 03 19 9- 00 4 VCM2 RCLMP COMM VOL2 VOH2 VIP2 GAIN VIN2 LOP2 COM2 LMD2 LON2 VPS2 INH2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 COM1 LOP1 LMD1 LON1 VPS1 INH1 VOH1 ENB VIP1 VCM1 VIN1 VPSV VOL1 HILO 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AD8332 TOP VIEW (Not to Scale) PIN 1 INDICATOR Figure 4. 28-Lead TSSOP Pin Configuration (AD8332) 24 COMM 23 VOH1 22 VOL1 21 VPSV 20 NC 19 VOL2 18 VOH2 17 COMM 1 2 3 4 5 6 7 8 LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2 9 10 11 12 13 14 15 16 LO P2 C O M 2 VI P2 VI N 2 VC M 2 M O D E G A IN R C LM P 32 31 30 29 28 27 26 25 LO P1 C O M 1 VI P1 VI N 1 VC M 1 H IL O EN B L EN B V AD8332 TOP VIEW (Not to Scale) 03 19 9- 00 5 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 5. 32-Lead LFCSP Pin Configuration (AD8332) Table 4. 28-Lead TSSOP Pin Function Description (AD8332) Pin No. Mnemonic Description 1 LMD2 CH 2 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass 2 INH2 CH2 LNA Input 3 VPS2 CH2 Supply LNA 5 V 4 LON2 CH2 LNA Inverting Output 5 LOP2 CH2 LNA Noninverting Output 6 COM2 CH2 LNA Ground 7 VIP2 CH2 VGA Noninverting Input 8 VIN2 CH2 VGA Inverting Input 9 VCM2 CH2 Common-Mode Voltage 10 GAIN Gain Control Voltage 11 RCLMP Output Clamping Resistor 12 VOH2 CH2 Noninverting VGA Output 13 VOL2 CH2 Inverting VGA Output 14 COMM VGA Ground (Both Channels) 15 VPSV VGA Supply 5 V (Both Channels) 16 VOL1 CH1 Inverting VGA Output 17 VOH1 CH1 Noninverting VGA Output 18 ENB Enable—VGA/LNA 19 HILO VGA Gain Range Select (HI or LO) 20 VCM1 CH1 Common-Mode Voltage 21 VIN1 CH1 VGA Inverting Input 22 VIP1 CH1 VGA Noninverting Input 23 COM1 CH1 LNA Ground 24 LOP1 CH1 LNA Noninverting Output 25 LON1 CH1 LNA Inverting Output 26 VPS1 CH1 LNA Supply 5 V 27 INH1 CH1 LNA Input 28 LMD1 CH 1 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass Table 5. 32-Lead LFCSP Pin Function Description (AD8332) Pin No. Mnemonic Description 1 LON1 CH1 LNA Inverting Output 2 VPS1 CH1 LNA Supply 5 V 3 INH1 CH1 LNA Input 4 LMD1 CH 1 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass 5 LMD2 CH 2 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass 6 INH2 CH2 LNA Input 7 VPS2 CH2 LNA Supply 5 V 8 LON2 CH2 LNA Inverting Output 9 LOP2 CH2 LNA Noninverting Output 10 COM2 CH2 LNA Ground 11 VIP2 CH2 VGA Noninverting Input 12 VIN2 CH2 VGA Inverting Input 13 VCM2 CH2 Common-Mode Voltage 14 MODE Gain Slope Logic Input 15 GAIN Gain Control Voltage 16 RCLMP Output Clamping Level Input 17 COMM VGA Ground 18 VOH2 CH2 Noninverting VGA Output 19 VOL2 CH2 Inverting VGA Output 20 NC No Connect 21 VPSV VGA Supply 5 V 22 VOL1 CH1 Inverting VGA Output 23 VOH1 CH1 Noninverting VGA Output 24 COMM VGA Ground 25 ENBV VGA Enable 26 ENBL LNA Enable 27 HILO VGA Gain Range Select (HI or LO) 28 VCM1 CH1 Common-Mode Voltage 29 VIN1 CH1 VGA Inverting Input 30 VIP1 CH1 VGA Noninverting Input 31 COM1 CH1 LNA Ground 32 LOP1 CH1 LNA Noninverting Output EPAD Exposed Pad. The exposed pad must be soldered to the PCB ground to ensure proper heat dissipation, noise, and mechanical strength benefits.

AD8331ARQZ-R7 Reviews

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Emm***** Cook

October 8, 2019

Worked very well! I would highly recommend buying.

Tinle*****llips

September 18, 2019

Works just like the original one and even has the correct connectors installed.

Ayli*****chanan

September 8, 2019

Excellent service and product arrives in reasonable shipping rates. Well done!

Dari*****ardin

July 23, 2019

Thousands of in stock parts with low cost shipping and standard quality.

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July 6, 2019

I am satisfied with Heisener company

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May 30, 2019

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May 30, 2019

Great communication. A pleasure to do business with.

Keit*****msey

May 9, 2019

Perfectly functioning!! on time and as described!

Bentl*****charia

March 18, 2019

Every time I order, I get it correctly filled and faster than most of website. For a friendly use operate system, you guys are the best!

Ariy*****errero

March 7, 2019

Excellent Seller,great product and Super Fast Shipping! Highly recommended A+++

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