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AD9915BCPZ

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AD9915BCPZ

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Part Number AD9915BCPZ
Manufacturer Analog Devices Inc.
Description IC DDS 16B 2.5GHZ 88LFCSP
Datasheet AD9915BCPZ Datasheet
Package 88-VFQFN Exposed Pad, CSP
In Stock 738 piece(s)
Unit Price $ 159.1 *
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AD9915BCPZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Interface - Direct Digital Synthesis (DDS)
Datasheet AD9915BCPZ Datasheet
Package88-VFQFN Exposed Pad, CSP
Series-
Resolution (Bits)12 b
Master fclk2.5GHz
Tuning Word Width (Bits)32 b
Voltage - Supply1.8V, 3.3V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case88-VFQFN Exposed Pad, CSP
Supplier Device Package88-LFCSP-VQ (12x12)

AD9915BCPZ Datasheet

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2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC Data Sheet AD9915 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 2.5 GSPS internal clock speed Integrated 12-bit DAC Frequency tuning resolution to 135 pHz 16-bit phase tuning resolution 12-bit amplitude scaling Programmable modulus Automatic linear and nonlinear frequency sweeping capability 32-bit parallel datapath interface 8 frequency/phase offset profiles Phase noise: −128 dBc/Hz (1 kHz offset at 978 MHz) Wideband SFDR < −57 dBc Serial or parallel input/output control 1.8 V/3.3 V power supplies Software and hardware controlled power-down 88-lead LFCSP package PLL REF CLK multiplier Phase modulation capability Amplitude modulation capability Multichip synchronization APPLICATIONS Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulator Fast frequency hopping FUNCTIONAL BLOCK DIAGRAM 12-BIT DAC2.5GSPS DDS CORE TIMING AND CONTROL AD9915 HIGH SPEED PARALLEL MODULATION PORT LINEAR SWEEP BLOCK SERIAL OR PARALLEL DATA PORT REF CLK MULTIPLIER 10 83 7- 00 1 Figure 1.

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AD9915 Data Sheet Rev. F | Page 2 of 47 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Absolute Maximum Ratings ............................................................ 8 Thermal Performance .................................................................. 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 16 Theory of Operation ...................................................................... 17 Single Tone Mode ....................................................................... 17 Profile Modulation Mode .......................................................... 17 Digital Ramp Modulation Mode .............................................. 17 Parallel Data Port Modulation Mode ....................................... 17 Programmable Modulus Mode ................................................. 17 Mode Priority .............................................................................. 18 Functional Block Detail ................................................................. 19 DDS Core ..................................................................................... 19 12-Bit DAC Output .................................................................... 20 DAC Calibration Output ........................................................... 20 Reconstruction Filter ................................................................. 20 Clock Input (REF_CLK/REF_CLK) ........................................ 21 PLL Lock Indication .................................................................. 22 Output Shift Keying (OSK) ....................................................... 22 Digital Ramp Generator (DRG) ............................................... 23 Power-Down Control ................................................................ 27 Programming and Function Pins ................................................. 28 Serial Programming ....................................................................... 31 Control Interface—Serial Input/Output ................................. 31 General Serial Input/Output Operation .................................. 31 Instruction Byte .......................................................................... 31 Serial Input/Output Port Pin Descriptions ............................. 31 Serial Input/Output Timing Diagrams .................................... 32 MSB/LSB Transfers .................................................................... 32 Parallel Programming (8-/16-Bit) ................................................ 33 Multiple Chip Synchronization .................................................... 34 Register Map and Bit Descriptions .............................................. 36 Register Bit Descriptions ........................................................... 41 Outline Dimensions ....................................................................... 47 Ordering Guide .......................................................................... 47 REVISION HISTORY 6/2016—Rev. E to Rev. F Changes to Figure 17 and Figure 19 ............................................. 14 1/2016—Rev. D to Rev. E Changes to DDS Core Section ...................................................... 19 Change to Figure 30 ....................................................................... 19 Updated Outline Dimensions ....................................................... 47 1/2014—Rev. C to Rev. D Change to Maximum DAC Calibration Time Parameter ........... 5 Change to Figure 23 ....................................................................... 15 Changes to DAC Calibration Output Section ............................. 20 Change to Address 0x02, Table 16 ................................................ 36 Changes to Table 19 ........................................................................ 43 11/2013—Rev. B to Rev. C Changes to Table 2 ............................................................................ 5 Changes to Programming and Function Pins Section .............. 30 7/2013—Rev. A to Rev. B Change to CMOS Logic Outputs Parameter, Table 1 ................... 4 Changes to Table 2 ............................................................................. 7 Changes to DDS Core Section ...................................................... 19 Changes to Phase-Locked Loop (PLL) Multiplier Section ....... 21 Changed PLL Charge Pump Section to PLL Charge Pump/ Total Feedback Divider Section; Changes to Table 8, PLL Loop Filter Components Section, and Figure 34 ....................... 22 Change to Table 16 ......................................................................... 36 Changes to Bits [15:8], Table 19 ................................................... 43 8/2012—Rev. 0 to Rev. A Changed External Clock Frequency from 3.5 GHz to 2.5 GHz and Differential Input Voltage Unit from mV p-p to V p-p ........ 4 Updated Outline Dimensions ....................................................... 47 7/2012—Revision 0: Initial Version

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Data Sheet AD9915 Rev. F | Page 3 of 47 GENERAL DESCRIPTION The AD9915 is a direct digital synthesizer (DDS) featuring a 12-bit DAC. The AD9915 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency agile analog output sinusoidal waveform at up to 1.0 GHz. The AD9915 enables fast frequency hopping and fine tuning resolution (64-bit capable using programmable modulus mode). The AD9915 also offers fast phase and amplitude hopping capability. The frequency tuning and control words are loaded into the AD9915 via a serial or parallel input/output port. The AD9915 also supports a user defined linear sweep mode of operation for generating linear swept waveforms of frequency, phase or amplitude. A high speed, 32-bit parallel data input port is included, enabling high data rates for polar modulation schemes and fast reprogramming of the phase, frequency, and amplitude tuning words. The AD9915 is specified to operate over the extended industrial temperature range (see the Absolute Maximum Ratings section). 32 F0 TO F3 D0 TO D31 PS[2:0] I/O_UPDATE POWER- DOWN CONTROL E X T _P W R _D W N DAC_RSET AOUT AOUT OSK DROVER DRCTL DRHOLD SYNC_CLK A θ CLOCK AMPLITUDE (A) FREQUENCY (ω) PHASE (θ)DIGITAL RAMP GENERATOR 2 4 MULTICHIP SYNCHRONIZATION SYSCLK PLL REF_CLK REF_CLK AD9915 OUTPUT SHIFT KEYING DATA ROUTE AND PARTITION CONTROL 3 INTERNAL CLOCK TIMING AND CONTROL ω Acos (ωt + θ) Asin (ωt + θ) S Y N C _O U T S Y N C _I N L O O P _F IL T E R M A S T E R _R E S E T DAC 12-BIT DDS INTERNAL PROGRAMMING REGISTERS 10 83 7- 00 2 Figure 2. Detailed Block Diagram

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AD9915 Data Sheet Rev. F | Page 4 of 47 SPECIFICATIONS DC SPECIFICATIONS AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE DVDD_I/O 3.135 3.30 3.465 V Pin 16, Pin 83 DVDD 1.71 1.80 1.89 V Pin 6, Pin 23, Pin 73 AVDD (3.3 V) 3.135 3.30 3.465 V Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 AVDD (1.8 V) 1.71 1.80 1.89 V Pin 32, Pin 56, Pin 57 SUPPLY CURRENT See also the total power dissipation specifications IDVDD_I/O 20 mA Pin 16, Pin 83 IDVDD 270 mA Pin 6, Pin 23, Pin 73 IAVDD(3.3V) 640 mA Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 IAVDD(1.8V) 148 mA Pin 32, Pin 56, Pin 57 TOTAL POWER DISSIPATION Base DDS Power, PLL Disabled 2138 2797 mW 2.5 GHz, single-tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled Base DDS Power, PLL Enabled 2237 2890 mW 2.5 GHz, single-tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled Linear Sweep Additional Power 28 mW Modulus Additional Power 20 mW Amplitude Scaler Additional Power 138 mW Manual or automatic Full Power-Down Mode 400 616 mW Using either the power-down and enable register or the EXT_PWR_DWN pin CMOS LOGIC INPUTS Input High Voltage (VIH) 2.0 DVDD_I/O V Input Low Voltage (VIL) 0.8 V Input Current (IINH, IINL) ±60 ±200 µA At VIN = 0 V and VIN = DVDD_I/O Maximum Input Capacitance (CIN) 3 pF CMOS LOGIC OUTPUTS Output High Voltage (VOH) 2.7 DVDD_I/O V IOH = 1 mA Output Low Voltage (VOL) 0.4 V IOL = 1 mA REF CLK INPUT CHARACTERISTICS REF CLK inputs must always be ac-coupled (both single- ended and differential) REF CLK Multiplier Bypassed Input Capacitance 1 pF Single-ended, each pin Input Resistance 1.4 kΩ Differential Internally Generated DC Bias Voltage 2 V Differential Input Voltage 0.8 1.5 V p-p REF CLK Multiplier Enabled Input Capacitance 1 pF Single-ended, each pin Input Resistance 1.4 kΩ Differential Internally Generated DC Bias Voltage 2 V Differential Input Voltage 0.8 1.5 V p-p

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Data Sheet AD9915 Rev. F | Page 5 of 47 AC SPECIFICATIONS AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD3 (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments REF CLK INPUT Input frequency range REF CLK Multiplier Bypassed Input Frequency Range 500 2500 MHz Maximum fOUT is 0.4 × fSYSCLK Duty Cycle 45 55 % Minimum Differential Input Level 632 mV p-p Equivalent to 316 mV swing on each leg System Clock (SYSCLK) PLL Enabled VCO Frequency Range 2400 2500 MHz VCO Gain (KV) 60 MHz/V Maximum PFD Rate 125 MHz CLOCK DRIVERS SYNC_CLK Output Driver Frequency Range 156 MHz Duty Cycle 45 50 55 % Rise Time/Fall Time (20% to 80%) 650 ps SYNC_OUT Output Driver 10 pF load Frequency Range 6.5 MHz Duty Cycle 33 66 % CFR2 register, Bit 9 = 1 Rise Time (20% to 80%) 1350 ps 10 pF load Fall Time (20% to 80%) 1670 ps 10 pF load DAC OUTPUT CHARACTERISTICS Output Frequency Range (1st Nyquist Zone) 0 1250 MHz Output Resistance 50 Ω Single-ended (each pin internally terminated to AVDD (3.3 V)) Output Capacitance 1 pF Full-Scale Output Current 20.48 mA Range depends on DAC RSET resistor Gain Error −10 +10 % FS Output Offset 0.6 μA Voltage Compliance Range AVDD − 0.50 AVDD + 0.50 V Wideband SFDR See the Typical Performance Characteristics section 122.5 MHz Output −67 dBc 0 MHz to 1250 MHz 305.3 MHz Output −66 dBc 0 MHz to 1250 MHz 497.5 MHz Output −59 dBc 0 MHz to 1250 MHz 978.2 MHz Output −60 dBc 0 MHz to 1250 MHz Narrow-Band SFDR See the Typical Performance Characteristics section 122.5 MHz Output −95 dBc ±500 kHz 305.3 MHz Output −95 dBc ±500 kHz 497.5 MHz Output −95 dBc ±500 kHz 978.2 MHz Output −92 dBc ±500 kHz DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power-Down 45 ns Power-down mode loses DAC/PLL calibration settings Time Required to Leave Power-Down 250 ns Must recalibrate DAC/PLL Minimum Master Reset time 24 SYSCLK cycles Maximum DAC Calibration Time (tCAL) 188 µs See the DAC Calibration Output section for formula; Bit 6 in Register 0x1B = 0 Maximum PLL Calibration Time (tREF_CLK) 16 ms PFD rate = 25 MHz 8 ms PFD rate = 50 MHz Maximum Profile Toggle Rate 2 SYNC_CLK period

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AD9915 Data Sheet Rev. F | Page 6 of 47 Parameter Min Typ Max Unit Test Conditions/Comments PARALLEL PORT TIMING Write Timing Address Setup Time to WR Active 1 ns Address Hold Time to WR Inactive 0 ns Data Setup Time to WR Inactive 3.8 ns Data Hold Time to WR Inactive 0 ns WR Minimum Low Time 2.1 ns WR Minimum High Time 3.8 ns Minimum WR Time 10.5 ns Read Timing Address to Data Valid 92 ns Address Hold to RD Inactive 0 ns RD Active to Data Valid 69 ns RD Inactive to Data Tristate 50 ns RD Minimum Low Time 69 ns RD Minimum High Time 50 ns SERIAL PORT TIMING SCLK Clock Rate (1/tCLK ) 80 MHz SCLK duty cycle = 50% SCLK Pulse Width High, tHIGH 1.5 ns SCLK Pulse Width Low, tLOW 5.1 ns SDIO to SCLK Setup Time, tDS 4.9 ns SDIO to SCLK Hold Time, tDH 0 ns SCLK Falling Edge to Valid Data on SDIO/SDO, tDV 78 ns CS to SCLK Setup Time, tS 4 ns CS to SCLK Hold Time, tH 0 ns CS Minimum Pulse Width High, tPWH 4 ns DATA PORT TIMING D[31:0] Setup Time to SYNC_CLK 2 ns D[31:0] Hold Time to SYNC_CLK 0 ns F[3:0] Setup Time to SYNC_CLK 2 ns F[3:0] Hold Time to SYNC_CLK 0 ns IO_UPDATE Pin Setup Time to SYNC_CLK 2 ns IO_UPDATE Pin Hold Time to SYNC_CLK 0 ns Profile Pin Setup Time to SYNC_CLK 2 ns Profile Pin Hold Time to SYNC_CLK 0 ns DR_CTL/DR_HOLD Setup Time to SYNC_CLK 2 ns DR_CTL/DR_HOLD Hold Time to SYNC_CLK 0 ns

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Data Sheet AD9915 Rev. F | Page 7 of 47 Parameter Min Typ Max Unit Test Conditions/Comments DATA LATENCY (PIPELINE DELAY) SYSCLK cycles = fS = system clock frequency in GHz Single Tone Mode or Profile Mode (Matched Latency Disabled) Frequency 222 SYSCLK cycles OSK disabled 238 SYSCLK cycles OSK enabled Phase 206 SYSCLK cycles OSK disabled 222 SYSCLK cycles OSK enabled Amplitude 78 SYSCLK cycles OSK enabled Single Tone Mode or Profile Mode (Matched Latency Enabled) Frequency 222 SYSCLK cycles OSK disabled 238 SYSCLK cycles OSK enabled Phase 222 SYSCLK cycles OSK disabled 238 SYSCLK cycles OSK enabled Amplitude 238 SYSCLK cycles OSK enabled Modulation Mode with 32-Bit Parallel Port (Match Latency Disabled) Frequency 222 SYSCLK cycles OSK disabled 238 SYSCLK cycles OSK enabled Phase 206 SYSCLK cycles OSK disabled 222 SYSCLK cycles OSK enabled Amplitude 78 SYSCLK cycles OSK enabled Modulation Mode with 32-Bit Parallel Port (Match Latency Enabled) Frequency 222 SYSCLK cycles OSK disabled 238 SYSCLK cycles OSK enabled Phase 222 SYSCLK cycles OSK disabled 238 SYSCLK cycles OSK enabled Amplitude 238 SYSCLK cycles OSK enabled Sweep Mode (Match Latency Disabled) Frequency 238 SYSCLK cycles OSK disabled 254 SYSCLK cycles OSK enabled Phase 222 SYSCLK cycles OSK disabled 238 SYSCLK cycles OSK enabled Amplitude 94 SYSCLK cycles OSK enabled Sweep Mode (Match Latency Enabled) Frequency 238 SYSCLK cycles OSK disabled 254 SYSCLK cycles OSK enabled Phase 238 SYSCLK cycles OSK disabled 254 SYSCLK cycles OSK enabled Amplitude 254 SYSCLK cycles OSK enabled

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AD9915 Data Sheet Rev. F | Page 8 of 47 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating AVDD (1.8 V), DVDD (1.8 V) Supplies 2 V AVDD (3.3 V), DVDD_I/O (3.3 V) Supplies 4 V Digital Input Voltage −0.7 V to +4 V Digital Output Current 5 mA Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (10 sec Soldering) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL PERFORMANCE Table 4. Symbol Description Value1 Unit JA Junction-to-ambient thermal resistance (still air) per JEDEC JESD51-2 24.1 °C/W JMA Junction-to-ambient thermal resistance (1.0 m/sec airflow) per JEDEC JESD51-6 21.3 °C/W JMA Junction-to-ambient thermal resistance (2.0 m/sec air flow) per JEDEC JESD51-6 20.0 °C/W JB Junction-to-board thermal resistance (still air) per JEDEC JESD51-8 13.3 °C/W JB Junction-to-board characterization parameter (still air) per JEDEC JESD51-6 12.8 °C/W JC Junction-to-case thermal resistance 2.21 °C/W JT Junction-to-top-of-package characterization parameter (still air) per JEDEC JESD51-2 0.23 °C/W 1 Results are from simulations. PCB is JEDEC multilayer. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. ESD CAUTION

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Data Sheet AD9915 Rev. F | Page 9 of 47 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D17 D16 D15/A7 D14/A6 D13/A5 DVDD (1.8V) DGND D12/A4 D11/A3 D10/A2 D9/A1 D8/A0 D7 D6 D5 DVDD_I/O (3.3V) 17DGND 18D4/SYNCIO 19D3/SDO 20D2/SDIO/WR 23 24 25 26 27 28 29 30 31 32 33 34 36 37 D V D D ( 1. 8V ) D G N D P S 0 P S 1 P S 2 F 0 F 1 F 2 F 3 A V D D ( 1. 8V ) A G N D A V D D ( 3. 3V ) 35 A G N D A V D D ( 3. 3V ) A G N D 38 A G N D 39 A V D D ( 3. 3V ) 40 A V D D ( 3. 3V ) 41 A O U T 58 57 56 55 54 53 52 51 50 49 48 47 46 45 LOOP_FILTER 59 REF 60 AVDD (3.3V) 61 SYNC_OUT 62 SYNC_IN 63 DRCTL 64 DRHOLD 65 DROVER 66 OSK AVDD (1.8V) AVDD (1.8V) REF CLK REF CLK AVDD (3.3V) AVDD (3.3V) AGND AVDD (3.3V) AGND DAC_RSET AVDD (3.3V) AGND DAC_BP 78 77 76 75 74 73 72 71 70 69 68 67 D 23 79 D 22 80 D 21 81 D 20 82 S Y N C _C L K 83 D V D D _I /O ( 3. 3V ) 84 D G N D 85 M A S T E R _R E S E T 86 I/ O _U P D A T E 87 D 19 88 D 18 D 24 D 25 D 26 D G N D D V D D ( 1. 8V ) D 27 D 28 D 29 D 30 D 31 E X T _P W R _D W N NOTES 1. THE EPAD MUST BE SOLDERED TO GROUND. 21D1/SCLK/RD 22D0/CS/PWD 42 A O U T 43 A V D D ( 3. 3V ) 44 A G N D AD9915 TOP VIEW (Not to Scale) 10 83 7- 00 3 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic I/O1 Description 1, 2, 13 to 15, 68 to 72, 75 to 81, 87, 88 D5 to D7, D16 to D31, D27 to D31 I/O Parallel Port Pins. The 32-bit parallel port offers the option for serial or parallel programming of the internal registers. In addition, the parallel port can be configured to provide direct FSK, PSK, or ASK (or combinations thereof) modulation data. The 32-bit parallel port configuration is set by the state of the four function pins (F0 to F3). 3 D15/A7 I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. 4 D14/A6 I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. 5 D13/A5 I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. 8 D12/A4 I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. 9 D11/A3 I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. 10 D10/A2 I/O Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins (F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. 11 D9/A1 I/O Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins (F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers.

AD9915BCPZ Reviews

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Ali*****Hobbs

December 26, 2019

All items individually packed in anti static bags and properly labeled.

Dant*****drano

December 12, 2019

Quality electronic components plus fast response.Thank you.

Matt*****Barr

November 24, 2019

Fantastic Quality Control and Great Selection. Heisener Electronics has became to my No.1 Supplier for many years.

Hada***** Hegde

August 30, 2019

Fast shipping. Got it in few dayss from Hong Kong

Kade*****ller

August 30, 2019

Absolutely the best source for wire, connectors, terminal strips, panel lights, etc. for model railroaders. Web site is the best in the business.

Chai*****nson

August 26, 2019

I always have good experiences in dealing with Heisener Electronics. They have the components I need in stock, their search function is great, and shipping is fast and always as promised.

Maril*****hwartz

April 17, 2019

Used these for a solar project, and they are working great.

Aval*****Dyer

February 19, 2019

Order arrived to Estonia in 3 days. Item as described. Well packed.

Gem*****Golla

February 1, 2019

Tested one of them and works good.

Jasm*****Meyer

January 29, 2019

Good seller, incredible reliable.Item as described. Very professional

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