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ADF4360-9BCPZ

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ADF4360-9BCPZ

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Part Number ADF4360-9BCPZ
Manufacturer Analog Devices Inc.
Description IC SYNTHESIZER W/ADJ VCO 24LFCSP
Datasheet ADF4360-9BCPZ Datasheet
Package 24-WFQFN Exposed Pad, CSP
In Stock 4,106 piece(s)
Unit Price $ 7.3100 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 3 - Jun 8 (Choose Expedited Shipping)
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Part Number # ADF4360-9BCPZ (Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADF4360-9BCPZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet ADF4360-9BCPZDatasheet
Package24-WFQFN Exposed Pad, CSP
Series-
TypeFanout Distribution, Integer N Synthesizer (RF)
PLLYes
InputCMOS, TTL
OutputClock
Number of Circuits1
Ratio - Input:Output1:2
Differential - Input:OutputNo/No
Frequency - Max400MHz
Divider/MultiplierYes/No
Voltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case24-WFQFN Exposed Pad, CSP
Supplier Device Package24-LFCSP-WQ (4x4)

ADF4360-9BCPZ Datasheet

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Clock Generator PLL with Integrated VCO Data Sheet ADF4360-9 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Primary output frequency range: 65 MHz to 400 MHz Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable output power level 3-wire serial interface Digital lock detect Software power-down mode APPLICATIONS System clock generation Test equipment Wireless LANs CATV equipment GENERAL DESCRIPTION The ADF4360-9 is an integrated integer-N synthesizer and voltage-controlled oscillator (VCO). External inductors set the ADF4360-9 center frequency. This allows a VCO frequency range of between 65 MHz and 400 MHz. An additional divider stage allows division of the VCO signal. The CMOS level output is equivalent to the VCO signal divided by the integer value between 2 and 31. This divided signal can be further divided by 2, if desired. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM 14-BIT R COUNTER AVDD CLK DATA VTUNE CN CC RFOUTA RFOUTB LD CP VVCO L1 DIVOUT L2 LE DVDD RSET LOCK DETECT MULTIPLEXER MUTE CHARGE PUMPPHASE COMPARATOR 24-BIT DATA REGISTER ADF4360-9 13-BIT B COUNTER N = B VCO CORE DIVIDE-BY-A (2 TO 31) DIVIDE-BY-2 OUTPUT STAGE 24-BIT FUNCTION LATCH REFIN AGND DGND CPGND 07 13 9- 00 1 Figure 1.

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ADF4360-9 Data Sheet Rev. D | Page 2 of 24 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description ......................................................................... 10 Reference Input Section ............................................................. 10 N Counter .................................................................................... 10 R Counter .................................................................................... 10 PFD and Charge Pump .............................................................. 10 Lock Detect ................................................................................. 10 Input Shift Register .................................................................... 10 VCO ............................................................................................. 11 Output Stage ................................................................................ 12 DIVOUT Stage............................................................................ 12 Latch Structure ........................................................................... 13 Power-Up ..................................................................................... 17 Control Latch .............................................................................. 18 N Counter Latch ......................................................................... 19 R Counter Latch ......................................................................... 19 Applications Information .............................................................. 20 Choosing the Correct Inductance Value ................................. 20 Encode Clock for ADC .............................................................. 20 GSM Test Clock .......................................................................... 21 Interfacing ................................................................................... 22 PCB Design Guidelines for Chip Scale Package .................... 22 Output Matching ........................................................................ 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/2016—Rev. C to Rev. D Changed ADF4360 Family to ADF4360-9 and ADSP-21xx to ADSP-2181 ........................................... Throughout Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 11/2012—Rev. B to Rev. C Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 24 2/2012—Rev. A to Rev. B Added EPAD Note ............................................................................ 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 3/2008—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Figure 23 ...................................................................... 14 Changes to Output Matching Section .......................................... 23 1/2008—Revision 0: Initial Version

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Data Sheet ADF4360-9 Rev. D | Page 3 of 24 SPECIFICATIONS AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.1 Table 1. Parameter B Version Unit Test Conditions/Comments REFIN CHARACTERISTICS REFIN Input Frequency 10/250 MHz min/MHz max For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave, slew rate > 21 V/µs REFIN Input Sensitivity 0.7/AVDD V p-p min/V p-p max AC-coupled 0 to AVDD V max CMOS-compatible REFIN Input Capacitance 5.0 pF max REFIN Input Current ±60 µA max PHASE DETECTOR Phase Detector Frequency2 8 MHz max CHARGE PUMP ICP Sink/Source3 With RSET = 4.7 kΩ High Value 2.5 mA typ Low Value 0.312 mA typ RSET Range 2.7/10 kΩ min/kΩ max ICP Three-State Leakage Current 0.2 nA typ Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V ICP vs. Temperature 2 % typ VCP = 2.0 V LOGIC INPUTS Input High Voltage, VINH 1.5 V min Input Low Voltage, VINL 0.6 V max Input Current, IINH/IINL ±1 µA max Input Capacitance, CIN 3.0 pF max LOGIC OUTPUTS Output High Voltage, VOH DVDD − 0.4 V min CMOS output chosen Output High Current, IOH 500 µA max Output Low Voltage, VOL 0.4 V max IOL = 500 µA POWER SUPPLIES AVDD 3.0/3.6 V min/V max DVDD AVDD VVCO AVDD AIDD4 5 mA typ DIDD4 2.5 mA typ IVCO4, 5 12.0 mA typ ICORE = 5 mA IRFOUT4 3.5 to 11.0 mA typ RF output stage is programmable Low Power Sleep Mode4 7 µA typ RF OUTPUT CHARACTERISTICS5 Maximum VCO Output Frequency 400 MHz ICORE = 5 mA; depending on L1 and L2; see the Choosing the Correct Inductance Value section Minimum VCO Output Frequency 65 MHz VCO Output Frequency 90/108 MHz min/MHz max L1, L2 = 270 nH; see the Choosing the Correct Inductance Value section for other frequency values VCO Frequency Range 1.2 Ratio fMAX/fMIN VCO Sensitivity 2 MHz/V typ L1, L2 = 270 nH; see the Choosing the Correct Inductance Value section for other sensitivity values Lock Time6 400 µs typ To within 10 Hz of final frequency Frequency Pushing (Open Loop) 0.24 MHz/V typ Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load Harmonic Content (Second) −16 dBc typ

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ADF4360-9 Data Sheet Rev. D | Page 4 of 24 Parameter B Version Unit Test Conditions/Comments Harmonic Content (Third) −21 dBc typ Output Power5, 7 −9/0 dBm typ Using tuned load, programmable in 3 dB steps; see Figure 35 Output Power5, 8 −14/−9 dBm typ Using 50 Ω resistors to VVCO, programmable in 3 dB steps; see Figure 33 Output Power Variation ±3 dB typ VCO Tuning Range 1.25/2.5 V min/V max VCO NOISE CHARACTERISTICS VCO Phase Noise Performance9,10 −91 dBc/Hz typ At 10 kHz offset from carrier −117 dBc/Hz typ At 100 kHz offset from carrier −139 dBc/Hz typ At 1 MHz offset from carrier −140 dBc/Hz typ At 3 MHz offset from carrier −147 dBc/Hz typ At 10 MHz offset from carrier Normalized In-Band Phase Noise 10, 11 −218 dBc/Hz typ In-Band Phase Noise10, 11 −110 dBc/Hz typ At 1 kHz offset from carrier RMS Integrated Jitter12 1.4 ps typ Measured at RFOUTA Spurious Signals Due to PFD Frequency13 −75 dBc typ DIVOUT CHARACTERISTICS12 Integrated Jitter Performance (Integrated from 100 Hz to 1 GHz) VCO frequency = 320 MHz to 380 MHz DIVOUT = 180 MHz 1.4 ps rms A = 2, A output selected DIVOUT = 95 MHz 1.4 ps rms A = 2, A/2 output selected DIVOUT = 80 MHz 1.4 ps rms A = 2, A/2 output selected DIVOUT = 52 MHz 1.4 ps rms A = 3, A/2 output selected (VCO = 312 MHz, PFD = 1.6 MHz) DIVOUT = 45 MHz 1.4 ps rms A = 4, A/2 output selected DIVOUT = 10 MHz 1.6 ps rms A = 18, A/2 output selected (VCO = 360 MHz, PFD = 1.6 MHz) DIVOUT Duty Cycle A Output 1/A × 100 % typ Divide-by-A selected A/2 Output 50 % typ Divide-by-A/2 selected 1 Operating temperature range is −40°C to +85°C. 2 Guaranteed by design. Sample tested to ensure compliance. 3 ICP is internally modified to maintain constant loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V. 5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2. 6 Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 For more detail on using tuned loads, see the Output Matching section. 8 Using 50 Ω resistors to VVCO into a 50 Ω load. 9 The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH. 10 The phase noise is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. 11 fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN. 12 The jitter is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz, unless otherwise noted. 13 The spurious signals are measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides the REFIN for the synthesizer; fREFIN = 10 MHz at 0 dBm. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz.

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Data Sheet ADF4360-9 Rev. D | Page 5 of 24 TIMING CHARACTERISTICS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width 1 Refer to the Power-Up section for the recommended power-up procedure for this device. CLK DATA LE LE DB23 (MSB) DB22 DB2 DB1(CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 t2 t3 t7 t6 t4 t5 07 13 9- 00 2 Figure 2. Timing Diagram

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ADF4360-9 Data Sheet Rev. D | Page 6 of 24 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating AVDD to GND1 −0.3 V to +3.9 V AVDD to DVDD −0.3 V to +0.3 V VVCO to GND −0.3 V to +3.9 V VVCO to AVDD −0.3 V to +0.3 V Digital Input/Output Voltage to GND −0.3 V to VDD + 0.3 V Analog Input/Output Voltage to GND −0.3 V to VDD + 0.3 V REFIN to GND −0.3 V to VDD + 0.3 V Operating Temperature Range −40°C to + 85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance Paddle Soldered 50°C/W Paddle Not Soldered 88°C/W Lead Temperature, Soldering Reflow 260°C 1 GND = CPGND = AGND = DGND = 0 V. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of <1 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. TRANSISTOR COUNT The transistor count is 12,543 (CMOS) and 700 (bipolar). ESD CAUTION

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Data Sheet ADF4360-9 Rev. D | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 07 13 9- 00 3 CPGND AVDD AGND RFOUTA RFOUTB VVCO DATA CLK REFIN DGND CN RSET V T U N E A G N D L 1 L 2 A G N D C C C P L D A G N D D V D D D IV O U T L EPIN 1 IDENTIFIER NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 2 1 3 4 5 6 18 17 16 15 14 13 8 9 10 1 17 12 20 1921222324 ADF4360-9 TOP VIEW Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 2 AVDD Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must have the same value as DVDD. 3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO. 4 RFOUTA VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a description of the various output stages. 5 RFOUTB VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a description of the various output stages. 6 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VVCO must have the same value as AVDD. 7 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage. 9 L1 An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND. 10 L2 An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND. 12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor. 13 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is ICPmax = 11.75/RSET For example, RSET = 4.7 kΩ and ICPmax = 2.5 mA. 14 CN Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor. 15 DGND Digital Ground. 16 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 17 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 18 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. 19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, and the relevant latch is selected using the control bits. 20 DIVOUT This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A. Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output. 21 DVDD Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must have the same value as AVDD. 23 LD Lock Detect. The output on this pin is logic high to indicate that the device is in lock. Logic low indicates loss of lock. 24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the internal VCO. EP Exposed Pad. The exposed pad must be connected to AGND.

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ADF4360-9 Data Sheet Rev. D | Page 8 of 24 TYPICAL PERFORMANCE CHARACTERISTICS –20 –40 –60 –80 –100 –120 –140 –160 1k 10k 100k 1M 10M 07 13 9- 00 4 P H A S E N O IS E ( d B c/ H z) FREQUENCY (Hz) Figure 4. Open-Loop VCO Phase Noise at 218 MHz, L1, L2 = 56 nH –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k100 10k 100k 1k 10M 07 13 9- 00 5 P H A S E N O IS E ( d B c/ H z) FREQUENCY OFFSET (Hz) Figure 5. VCO Phase Noise, 360 MHz, 1 MHz PFD, 40 kHz Loop Bandwidth, RMS Jitter = 1.4 ps –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 P H A S E N O IS E ( d B c/ H z) 1k100 10k 100k 1M 10M 07 13 9- 00 6 FREQUENCY OFFSET (Hz) Figure 6. DIVOUT Phase Noise, 180 MHz, VCO = 360 MHz, PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps, Divide-by-A Selected, A = 2 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k100 10k 100k 1M 10M 07 13 9- 00 7 P H A S E N O IS E ( d B c/ H z) FREQUENCY (Hz) Figure 7. DIVOUT Phase Noise, 95 MHz, VCO = 380 MHz, PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps, Divide-by-A/2 Selected, A = 2 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 P H A S E N O IS E ( d B c/ H z) 1k100 10k 100k 1M 10M 07 13 9- 00 8 FREQUENCY OFFSET (Hz) Figure 8. DIVOUT Phase Noise, 80 MHz, VCO = 320 MHz, PFD Frequency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps, Divide-by-A/2 Selected, A = 2 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 P H A S E N O IS E ( d B c/ H z) 07 13 9- 00 9 Figure 9. DIVOUT Phase Noise, 52 MHz, VCO = 312 MHz, PFD Frequency = 1.6 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.4 ps, Divide-by-A/2 Selected, A = 3

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Data Sheet ADF4360-9 Rev. D | Page 9 of 24 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 P H A S E N O IS E ( d B c/ H z) 1k100 10k 100k 1M 10M 07 13 9- 01 0 FREQUENCY OFFSET (Hz) Figure 10. DIVOUT Phase Noise, 45 MHz, VCO = 360 MHz, PFD Frequency = 1.6 MHz, Loop Bandwidth = 60 kHz, Jitter = 1.4 ps, Divide-by-A/2 Selected, A = 2 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M 10M 07 13 9- 01 1 P H A S E N O IS E ( d B c/ H z) FREQUENCY OFFSET (Hz) +25°C –40°C +85°C Figure 11. DIVOUT Phase Noise over Temperature, 52 MHz, VCO = 312 MHz, PFD Frequency = 1 MHz, Loop Bandwidth = 60 kHz, Divide-by-A/2 Selected, A = 3 07 13 9- 01 2 CH1 500mV M 2.00ns A CH1 20mV 1 C1 FREQUENCY: 180MHz C1 + DUTY: 45.32% Figure 12. DIVOUT 180 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected, A = 2, Duty Cycle = ~50% 07 13 9- 01 3 CH1 500mV M 2.00ns 1 A CH1 20mV C1 FREQUENCY: 90MHz C1 + DUTY: 28.98% C1 PEAK TO PEAK: 1.55V Figure 13. DIVOUT 90 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected, A = 4, Duty Cycle = ~25% 07 13 9- 01 4 CH1 500mV M 5.00ns A CH1 920mV 1 C1 FREQUENCY: 36.01MHz C1 + DUTY: 13.13% C1 PEAK TO PEAK 1.28V Figure 14. DIVOUT 36 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected, A = 10, Duty Cycle = ~10% 07 13 9- 01 5 CH1 500mV M 12.5ns A CH1 920mV 1 C1 FREQUENCY: 36MHz C1 + DUTY: 49.41% Figure 15. DIVOUT 36 MHz Waveform, VCO = 360 MHz, Divide-by-A/2 Selected, A = 5, Duty Cycle = ~50%

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