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ADF5355BCPZ

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ADF5355BCPZ

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Part Number ADF5355BCPZ
Manufacturer Analog Devices Inc.
Description IC INTEGRATED SYNTH/VCO 32LFCSP
Datasheet ADF5355BCPZ Datasheet
Package 32-WFQFN Exposed Pad, CSP
In Stock 3,544 piece(s)
Unit Price $ 69.6800 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # ADF5355BCPZ (Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers) is manufactured by Analog Devices Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ADF5355BCPZ Specifications

ManufacturerAnalog Devices Inc.
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet ADF5355BCPZDatasheet
Package32-WFQFN Exposed Pad, CSP
Series-
Type-
PLLNo
InputClock
OutputClock
Number of Circuits1
Ratio - Input:Output1:2
Differential - Input:OutputYes/Yes
Frequency - Max13.6GHz
Divider/MultiplierYes/Yes
Voltage - Supply3.15 V ~ 3.45 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case32-WFQFN Exposed Pad, CSP
Supplier Device Package32-LFCSP-WQ (5x5)

ADF5355BCPZ Datasheet

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Microwave Wideband Synthesizer with Integrated VCO Data Sheet ADF5355 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES RF output frequency range: 54 MHz to 13,600 MHz Fractional-N synthesizer and integer-N synthesizer High resolution 38-bit modulus Phase frequency detector (PFD) operation to 125 MHz Reference frequency operation to 600 MHz Maintains frequency lock over −40°C to +85°C Low phase noise, voltage controlled oscillator (VCO) Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output Analog and digital power supplies: 3.3 V Charge pump and VCO power supplies: 5.0 V, typical Logic compatibility: 1.8 V Programmable dual modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function Analog and digital lock detect Supported in the ADIsimPLL design tool APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation GENERAL DESCRIPTION The ADF5355 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave VCO design permits frequency operation from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A series of frequency dividers at another frequency output permits operation from 54 MHz to 6800 MHz. The ADF5355 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable. Control of all on-chip registers is through a simple 3-wire interface. The ADF5355 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF5355 also contains hardware and software power-down modes. FUNCTIONAL BLOCK DIAGRAM MUXOUT CPOUT VBIAS REFIN CLK DATA LE AVDD CREG1 CREG2 DVDD VP AGND CE CPGND SDGND AGNDVCO RSET VVCO VTUNE VREF RFOUTB RFOUTA+ RFOUTA– VCO CORE PHASE COMPARATOR CHARGE PUMP OUTPUT STAGE OUTPUT STAGE PDBRF MULTIPLEXER 10-BIT R COUNTER ÷2 DIVIDER×2 DOUBLER FUNCTION LATCH DATA REGISTER INTEGER REG N COUNTER FRACTION REG THIRD-ORDER FRACTIONAL INTERPOLATOR MODULUS REG MULTIPLEXER LOCK DETECT ÷ 1/2/4/8/ 16/32/64 ADF5355 REFINA B VRF AGNDRF VREGVCO ×2 AVDD 12 71 4- 00 1 Figure 1. 4

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ADF5355 Data Sheet Rev. D | Page 2 of 38 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings ............................................................ 8 Transistor Count ........................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Circuit Description ......................................................................... 16 Reference Input ........................................................................... 16 RF N Divider ............................................................................... 16 Phase Frequency Detector (PFD) and Charge Pump ............ 17 MUXOUT and Lock Detect ...................................................... 17 Input Shift Registers ................................................................... 17 Program Modes .......................................................................... 18 VCO.............................................................................................. 18 Output Stage ................................................................................ 18 Register Maps .................................................................................. 20 Register 0 ..................................................................................... 22 Register 1 ..................................................................................... 23 Register 2 ..................................................................................... 24 Register 3 ..................................................................................... 25 Register 4 ..................................................................................... 26 Register 5 ..................................................................................... 27 Register 6 ..................................................................................... 28 Register 7 ..................................................................................... 30 Register 8 ..................................................................................... 31 Register 9 ..................................................................................... 31 Register 10 ................................................................................... 32 Register 11 ................................................................................... 32 Register 12 ................................................................................... 33 Register Initialization Sequence ............................................... 33 Frequency Update Sequence ..................................................... 33 RF Synthesizer—A Worked Example ...................................... 34 Reference Doubler and Reference Divider ............................. 34 Spurious Optimization and Fast Lock ..................................... 34 Optimizing Jitter ......................................................................... 35 Spur Mechanisms ....................................................................... 35 Lock Time.................................................................................... 35 Applications Information .............................................................. 36 Power Supplies ............................................................................ 36 Printed Circuit Board (PCB) Design Guidelines for a Chip- Scale Package .............................................................................. 36 Output Matching ........................................................................ 37 Outline Dimensions ....................................................................... 38 Ordering Guide .......................................................................... 38

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Data Sheet ADF5355 Rev. D | Page 3 of 38 REVISION HISTORY 8/2017—Rev. C to Rev D Changes to Frequency Update Sequence Section ....................... 34 Updated Outline Dimensions ........................................................ 38 Changes to Ordering Guide ........................................................... 38 4/2017—Rev. B to Rev C Changes to Figure 55 and Power Supplies Section ..................... 36 1/2017—Rev. A to Rev B Change to Features Section .............................................................. 1 Changes to Doubler Enabled Parameter and Endnote 3, Table 1 ..... 4 Changes to Table 2 ............................................................................ 7 Changes to Table 3 ............................................................................ 8 Changes to Table 4 ............................................................................ 9 Changes to Reference Input Section and Figure 32 Caption ..... 16 Changes to Table 6 .......................................................................... 19 Changes to Phase Resync Section ................................................. 25 Change to Reference Doubler Section .......................................... 26 Changes to Power-Down Section .................................................. 27 Changes to Negative Bleed Section ............................................... 28 Changes to Loss of Lock (LOL) Mode Section ............................ 30 Changes to Register Initialization Sequence Section and Frequency Update Sequence Section ................................................................. 33 Changes to Power Supplies Section and Figure 55 ..................... 36 2/2015—Rev. 0 to Rev. A Changed Register 5, Bit DB5 Value from 0 to 1 ........ Throughout Changed Register 5 Default Value from 0x00800005 to 0x00800025 .................................................................... Throughout Changed Register 8 Default Value from 0x102D4028 to 0x102D0428 ................................................................... Throughout Changes to Table 1 ............................................................................ 4 Changed Timing Diagram Section to Write Timing Diagram Section ................................................................................................ 7 Changes to Table 4 .......................................................................... 10 Changes to Figure 4 to Figure 6 .................................................... 11 Added Figure 7 to Figure 9; Renumbered Sequentially ............. 11 Changes to Figure 10 to Figure 18 ................................................ 12 Changes to Figure 20 ...................................................................... 13 Changes to Figure 23 and Figure 27 ............................................. 14 Changes to Figure 28 to Figure 30 and Figure 31 Caption ........ 15 Changes to Reference Input Section and INT, FRAC, MOD, and R Counter Relationship Section ............................................ 16 Changes to Phase Frequency Detector (PFD) and Charge Pump Section .............................................................................................. 17 Changes to VCO Section and Output Stage Section .................. 18 Changes to Automatic Calibration (AUTOCAL) Section ......... 22 Changes to Figure 43 ...................................................................... 24 Changes to MUXOUT Section ...................................................... 26 Changes to Reference Mode Section and Counter Reset Section .............................................................................................. 27 Changes to Negative Bleed Section ............................................... 28 Changes to Charge Pump Bleed Current Section ....................... 29 Changes to Register 9 Section, VCO Band Division Section, Timeout Section, Automatic Level Calibration Timeout Section, and Synthesizer Lock Timeout Section ........................................ 31 Changes to ADC Conversion Clock (ADC_CLK_DIV) Section .............................................................................................. 32 Changes to Phase Resync Clock Divider Value Section and Frequency Update Sequence Section............................................ 33 Changes to RF Synthesizer—A Worked Example Section ........ 34 Changes to Lock Time Section and Automatic Level Calibration Timeout Section ......................................................... 35 Added Lock Time—A Worked Example Section ....................... 35 10/2014—Revision 0: Initial Version

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ADF5355 Data Sheet Rev. D | Page 4 of 38 SPECIFICATIONS AVDD = DVDD = VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments REFINA/REFINB CHARACTERISTICS Input Frequency For f < 10 MHz, ensure slew rate > 21 V/µs Single-Ended Mode 10 250 MHz Differential Mode 10 600 MHz Doubler Enabled 100 MHz Doubler is set in Register 4, Bit DB26 Input Sensitivity Single-Ended Mode 0.4 AVDD V p-p REFINA biased at AVDD/2; ac coupling ensures AVDD/2 bias Differential Mode 0.4 1.8 V p-p LVDS and LVPECL compatible, REFINA/REFINB biased at 2.1 V; ac coupling ensures 2.1 V bias Input Capacitance Single-Ended Mode 6.9 pF Differential Mode 1.4 pF Input Current ±60 µA Single-ended reference programmed ±250 µA Differential reference programmed Phase Detector Frequency 125 MHz CHARGE PUMP (CP) Charge Pump Current, Sink/Source ICP RSET = 5.1 kΩ High Value 4.8 mA Low Value 0.3 mA RSET Range 5.1 kΩ Fixed Current Matching 3 % 0.5 V ≤ VCP1 ≤ VP − 0.5 V ICP vs. VCP 3 % 0.5 V ≤ VCP1 ≤ VP − 0.5 V ICP vs. Temperature 1.5 % VCP1 = 2.5 V LOGIC INPUTS Input High Voltage VINH 1.5 V Input Low Voltage VINL 0.6 V Input Current IINH/IINL ±1 µA Input Capacitance CIN 3.0 pF LOGIC OUTPUTS Output High Voltage VOH DVDD − 0.4 V 1.5 1.8 V 1.8 V output selected Output High Current IOH 500 µA Output Low Voltage VOL 0.4 V IOL2 = 500 µA POWER SUPPLIES See Table 6 Analog Power AVDD 3.15 3.45 V Digital Power and RF Supply Voltage DVDD, VRF AVDD Voltages must equal AVDD Charge Pump and VCO Supply Voltage VP, VVCO 4.75 5.0 5.25 V VP must equal VVCO Charge Pump Supply Power Current IP 8 9 DIDD + AIDD3 62 69 mA Output Dividers 6 to 36 mA Each output divide by 2 consumes 6 mA Supply Current IVCO 70 85 mA

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Data Sheet ADF5355 Rev. D | Page 5 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments RFOUTA±/RFOUTB Supply Current IRFOUTx± RFOUTA± output stage is programmable; enabling RFOUTB draws negligible extra current 16 20 mA −4 dBm setting 30 35 mA −1 dBm setting 42 50 mA 2 dBm setting 55 70 mA 5 dBm setting Low Power Sleep Mode 500 µA Hardware power-down selected 1000 µA Software power-down selected RF OUTPUT CHARACTERISTICS VCO Frequency Range 3400 6800 MHz Fundamental VCO range RFOUTB Output Frequency 6800 13600 MHz 2× VCO output (RFOUTB) RFOUTA+/RFOUTA− Output Frequency 53.125 6800 MHz VCO Sensitivity KV 15 MHz/V Frequency Pushing (Open-Loop) 15 MHz/V Frequency Pulling (Open-Loop) 0.5 MHz Voltage standing wave ratio (VSWR) = 2:1 RFOUTA+/RFOUTA− 30 MHz VSWR = 2:1 RFOUTB Harmonic Content Second −27 dBc Fundamental VCO output (RFOUTA+) −22 dBc Divided VCO output (RFOUTA+) Third −20 dBc Fundamental VCO output (RFOUTA+) −12 dBc Divided VCO output (RFOUTA+) Fundamental VCO Feedthrough −8 dBm RFOUTB = 10 GHz −55 dBc RFOUTA+/RFOUTA− = 1 GHz; VCO frequency = 4 GHz RF Output Power4 +8 dBm RFOUTA+ = 1 GHz; 7.5 nH inductor to VRF −3 dBm RFOUTA+/RFOUTA− = 6.8 GHz; 7.5 nH inductor to VRF 1 dBm RFOUTB = 6.8 GHz −1 dBm RFOUTB = 13.6 GHz RF Output Power Variation ±1 dB RFOUTA+/RFOUTA− = 5 GHz ±1 dB RFOUTB = 10 GHz RF Output Power Variation (over Frequency) ±6 dB RFOUTA+/RFOUTA− = 1 GHz to 6.8 GHz ±4 dB RFOUTB = 6.8 GHz to 13.6 GHz Level of Signal with RF Output Disabled −60 dBm RFOUTA+/RFOUTA− = 1 GHz −30 dBm RFOUTA+/RFOUTA− = 6.8 GHz −15 dBm RFOUTB = 6.8 GHz −17 dBm RFOUTB = 13.6 GHz NOISE CHARACTERISTICS Fundamental VCO Phase Noise Performance VCO noise in open-loop conditions −116 dBc/Hz 100 kHz offset from 3.4 GHz carrier −136 dBc/Hz 800 kHz offset from 3.4 GHz carrier −138 dBc/Hz 1 MHz offset from 3.4 GHz carrier −155 dBc/Hz 10 MHz offset from 3.4 GHz carrier −113 dBc/Hz 100 kHz offset from 5.0 GHz carrier −133 dBc/Hz 800 kHz offset from 5.0 GHz carrier −135 dBc/Hz 1 MHz offset from 5.0 GHz carrier −153 dBc/Hz 10 MHz offset from 5.0 GHz carrier −110 dBc/Hz 100 kHz offset from 6.8 GHz carrier −130 dBc/Hz 800 kHz offset from 6.8 GHz carrier −132 dBc/Hz 1 MHz offset from 6.8 GHz carrier −150 dBc/Hz 10 MHz offset from 6.8 GHz carrier

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ADF5355 Data Sheet Rev. D | Page 6 of 38 Parameter Symbol Min Typ Max Unit Test Conditions/Comments VCO 2× Phase Noise Performance VCO noise in open-loop conditions −110 dBc/Hz 100 kHz offset from 6.8 GHz carrier −130 dBc/Hz 800 kHz offset from 6.8 GHz carrier −132 dBc/Hz 1 MHz offset from 6.8 GHz carrier −149 dBc/Hz 10 MHz offset from 6.8 GHz carrier −107 dBc/Hz 100 kHz offset from 10 GHz carrier −127 dBc/Hz 800 kHz offset from 10 GHz carrier −129 dBc/Hz 1 MHz offset from 10 GHz carrier −147 dBc/Hz 10 MHz offset from 10 GHz carrier −103 dBc/Hz 100 kHz offset from 13.6 GHz carrier −124 dBc/Hz 800 kHz offset from 13.6 GHz carrier −126 dBc/Hz 1 MHz offset from 13.6 GHz carrier −144 dBc/Hz 10 MHz offset from 13.6 GHz carrier Normalized In-Band Phase Noise Floor Fractional Channel5 −221 dBc/Hz Integer Channel6 −223 dBc/Hz Normalized 1/f Noise, PN1_f7 −116 dBc/Hz 10 kHz offset; normalized to 1 GHz Integrated RMS Jitter 150 fs Spurious Signals due to PFD Frequency −80 dBc 1 VCP is the voltage at the CPOUT pin. 2 IOL is the output low current. 3 TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz. For the nominal DIDD + AIDD (62 mA): DIDD = 15 mA (typical), AIDD (Pin 5) = 24 mA (typical), AIDD (Pin 16) = 23 mA (typical). 4 RF output power using the EV-ADF5355SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins are terminated in 50 Ω. 5 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel. 6 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel. 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the ADIsimPLL design tool.

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Data Sheet ADF5355 Rev. D | Page 7 of 38 TIMING CHARACTERISTICS AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Write Timing Parameter Limit Unit Description fCLK 50 MHz max Serial peripheral interface CLK frequency t1 10 ns min LE setup time t2 5 ns min DATA to CLK setup time t3 5 ns min DATA to CLK hold time t4 10 ns min CLK high duration t5 10 ns min CLK low duration t6 5 ns min CLK to LE setup time t7 20 (or 2/fPFD, whichever is longer) ns min LE pulse width Write Timing Diagram CLK DATA LE DB31 (MSB) DB30 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 t2 t3 t7 t6 t4 t5 DB2 (CONTROL BIT C3) DB3 (CONTROL BIT C4) 1 2 7 14 -0 0 2 Figure 2. Write Timing Diagram

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ADF5355 Data Sheet Rev. D | Page 8 of 38 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Rating VRF, DVDD, AVDD to GND1, 2 −0.3 V to +3.6 V AVDD to DVDD −0.3 V to +0.3 V VP, VVCO to GND1 −0.3 V to +5.8 V CPOUT to GND1 −0.3 V to VP + 0.3 V Digital Input/Output Voltage to GND1 −0.3 V to DVDD + 0.3 V Analog Input/Output Voltage to GND1 −0.3 V to AVDD + 0.3 V REFINA, REFINB to GND1 −0.3 V to AVDD + 0.3 V REFINA to REFINB ±2.1 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C θJA, Thermal Impedance Paddle Soldered to GND1 27.3°C/W Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec Electrostatic Discharge (ESD) Charged Device Model 1000 V Human Body Model 2500 V 1 GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V. 2 Do not connect VRF to DVDD. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The ADF5355 is a high performance RF integrated circuit with an ESD rating of 2.5 kV and is ESD sensitive. Take proper precautions for handling and assembly. TRANSISTOR COUNT The transistor count for the ADF5355 is 103,665 (CMOS) and 3214 (bipolar). ESD CAUTION

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Data Sheet ADF5355 Rev. D | Page 9 of 38 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK DATA LE CE VBIAS VREF C R EG 2 R EF IN A R EF IN B SD G N D VP CPOUT CPGND M U XO U T RSET R F O U TA + R F O U TB R F O U TA − VTUNE AGNDVCO AGNDVCO PD B R F C R EG 1 A G N D R F VVCO NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. D V D D VREGVCO A G N D R F A G N D AVDD V R F AV D D 12 71 4- 00 3 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ADF5355 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 2 DATA Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs) as the control bits. This input is a high impedance CMOS input. 3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the four LSBs. 4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high (at levels equal to DVDD) on this pin powers up the device, depending on the status of the power- down bits. Register contents are retained unless the supply voltages are removed. 5, 16 AVDD Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog ground plane as close to this pin as possible. AVDD must have the same value as DVDD. 6 VP Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground plane as close to this pin as possible. 7 CPOUT Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the loop filter is connected to VTUNE to drive the internal VCO. 8 CPGND Charge Pump Ground. This output is the ground return pin for CPOUT. 9 AGND Analog Ground. Ground return pin for AVDD. 10 VRF Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin as possible. VRF must have the same value as AVDD. Do not connect VRF to DVDD. 11 RFOUTA+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin. 12 RFOUTA− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin. 13, 15 AGNDRF RF Output Stage Ground. Ground return pins for the RF output stage. 14 RFOUTB Auxiliary VCO Output. The 2× VCO output is available at this pin. 17 VVCO Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to the analog ground plane as close to this pin as possible. For best performance, this supply must be clean and have low noise. 18, 21 AGNDVCO VCO Ground. Ground return path for the VCO. 19 VREGVCO VCO Compensation Node. Place decoupling capacitors to the ground plane as close to this pin as possible. Connect this pin directly to VVCO. 20 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT output voltage. The input capacitance of this pin is 9 pF. 22 RSET No Connection. Charge pump bias resistance is internal.

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July 17, 2020

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