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FDS3992

hot FDS3992

FDS3992

For Reference Only

Part Number FDS3992
Manufacturer Fairchild/ON Semiconductor
Description MOSFET 2N-CH 100V 4.5A 8-SO
Datasheet FDS3992 Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 446 piece(s)
Unit Price $ 0.8368 *
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FDS3992 Specifications

ManufacturerFairchild/ON Semiconductor
CategoryDiscrete Semiconductor Products - Transistors - FETs, MOSFETs - Arrays
Datasheet FDS3992 Datasheet
Package8-SOIC (0.154", 3.90mm Width)
SeriesPowerTrench?
FET Type2 N-Channel (Dual)
FET FeatureStandard
Drain to Source Voltage (Vdss)100V
Current - Continuous Drain (Id) @ 25��C4.5A
Rds On (Max) @ Id, Vgs62 mOhm @ 4.5A, 10V
Vgs(th) (Max) @ Id4V @ 250µA
Gate Charge (Qg) (Max) @ Vgs15nC @ 10V
Input Capacitance (Ciss) (Max) @ Vds750pF @ 25V
Power - Max2.5W
Operating Temperature-55°C ~ 150°C (TJ)
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SO

FDS3992 Datasheet

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To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. Is Now Part of ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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©2004 Fairchild Semiconductor Corporation April 2013 FDS3992 Rev. C F D S 3 9 9 2 FDS3992 Dual N-Channel PowerTrench® MOSFET 100V, 4.5A, 62mΩ Features • rDS(ON) = 54mΩ (Typ.), VGS = 10V, ID = 4.5A • Qg(tot) = 11nC (Typ.), VGS = 10V • Low Miller Charge • Low QRR Body Diode • Optimized efficiency at high frequencies • UIS Capability (Single Pulse and Repetitive Pulse) Formerly developmental type 82745 Applications • DC/DC converters and Off-Line UPS • Distributed Power Architectures and VRMs • Primary Switch for 24V and 48V Systems • High Voltage Synchronous Rectifier • Direct Injection / Diesel Injection Systems • 42V Automotive Load Control • Electronic Valve Train Systems MOSFET Maximum Ratings TA = 25°C unless otherwise noted Thermal Characteristics Package Marking and Ordering Information Symbol Parameter Ratings Units VDSS Drain to Source Voltage 100 V VGS Gate to Source Voltage ±20 V ID Drain Current 4.5 AContinuous (TA = 25 oC, VGS = 10V, RθJA = 50 oC/W) Continuous (TA = 100 oC, VGS = 10V, RθJA = 50 oC/W) 2.8 A Pulsed Figure 4 A EAS Single Pulse Avalanche Energy (Note 1) 167 mJ PD Total Package Power Dissipation 2.5 W Derate above 25oC 20 mW/oC TJ, TSTG Operating and Storage Temperature -55 to 150 oC RθJA Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) 50 oC/W RθJA Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 85 oC/W RθJC Thermal Resistance, Junction to Case (Note 2) 25 oC/W Device Marking Device Package Reel Size Tape Width Quantity SO-8 Branding Dash 1 5 2 3 4 (8)(1) (7) (6) (5) (3) (4) (2) FDS3992 FDS3992 SO-8 13’’ 12mm 2500 units

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©2004 Fairchild Semiconductor Corporation FDS3992 Rev. C F D S 3 9 9 2 Electrical Characteristics TA = 25°C unless otherwise noted Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics (VGS = 10V) Drain-Source Diode Characteristics Notes: 1: 2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user’s board design. 3: RθJA is measured with 1.0 in 2 copper on FR-4 board Symbol Parameter Test Conditions Min Typ Max Units BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 100 - - V IDSS Zero Gate Voltage Drain Current VDS = 80V - - 1 µA VGS = 0V TC = 150 oC - - 250 IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V rDS(ON) Drain to Source On Resistance ID = 4.5A, VGS = 10V - 0.054 0.062 Ω ID = 2A, VGS = 6V - 0.072 0.108 ID = 4.5A, VGS = 10V, TC = 150 oC - 0.107 0.123 CISS Input Capacitance VDS = 25V, VGS = 0V, f = 1MHz - 750 - pF COSS Output Capacitance - 118 - pF CRSS Reverse Transfer Capacitance - 27 - pF Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V VDD = 50V ID = 4.5A Ig = 1.0mA - 11 15 nC Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 1.4 1.9 nC Qgs Gate to Source Gate Charge - 3.5 - nC Qgs2 Gate Charge Threshold to Plateau - 2.1 - nC Qgd Gate to Drain “Miller” Charge - 2.8 - nC tON Turn-On Time VDD = 50V, ID = 4.5A VGS = 10V, RGS = 27Ω - - 47 ns td(ON) Turn-On Delay Time - 8 - ns tr Rise Time - 23 - ns td(OFF) Turn-Off Delay Time - 28 - ns tf Fall Time - 26 - ns tOFF Turn-Off Time - - 81 ns VSD Source to Drain Diode Voltage ISD = 4.5A - - 1.25 V ISD = 2A - - 1.0 V trr Reverse Recovery Time ISD= 4.5A, dISD/dt= 100A/µs - - 48 ns QRR Reverse Recovery Charge ISD= 4.5A, dISD/dt= 100A/µs - - 65 nC starting TJ = 25°C, L = 37mH, IAS = 3A. 100% test at L = 1mH, I = 10.3A.E of 167mJ is based on ASAS

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©2004 Fairchild Semiconductor Corporation FDS3992 Rev. C F D S 3 9 9 2 Typical Characteristics TA = 25°C unless otherwise noted Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Ambient Temperature Figure 3. Normalized Maximum Transient Thermal Impedance Figure 4. Peak Current Capability TA, AMBIENT TEMPERATURE ( oC) P O W E R D IS S IP A T IO N M U L T IP L IE R 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 1 2 3 4 5 25 50 75 100 125 150 I D , D R A IN C U R R E N T ( A ) TA, AMBIENT TEMPERATURE ( oC) VGS = 10V 0.001 0.01 0.1 1 10-5 10-4 10-3 10-2 10-1 100 101 102 103 2 t, RECTANGULAR PULSE DURATION (s) Z θ J A , N O R M A L IZ E D SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA PDM t1 t2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.01 0.02 T H E R M A L I M P E D A N C E RθJA=50 oC/W 1 10 100 10-5 10-4 10-3 10-2 10-1 100 101 102 103 200 I D M , P E A K C U R R E N T ( A ) t , PULSE WIDTH (s) TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION VGS = 10V TA = 25 oC I = I25 150 - TC 125 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

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©2004 Fairchild Semiconductor Corporation FDS3992 Rev. C F D S 3 9 9 2 Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics Figure 9. Drain to Source On Resistance vs Drain Current Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature Typical Characteristics TA = 25°C unless otherwise noted 0.01 0.1 1 10 100 1 10 100 3000.1 200 I D , D R A IN C U R R E N T ( A ) VDS, DRAIN TO SOURCE VOLTAGE (V) TJ = MAX RATED TC = 25 oC SINGLE PULSE LIMITED BY rDS(ON) AREA MAY BE OPERATION IN THIS 10µs 100ms 10ms 1s 100µs 1ms 0.1 1 0.01 0.1 1 10 100 7 I A S , A V A L A N C H E C U R R E N T ( A ) tAV, TIME IN AVALANCHE (ms) STARTING TJ = 25 oC STARTING TJ = 150 oC tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R = 0 If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 0 5 10 15 20 25 30 3.5 4.0 4.5 5.0 5.5 6.0 6.5 I D , D R A IN C U R R E N T ( A ) VGS , GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V TJ = 150 oC TJ = 25 oC TJ = -55 oC 0 5 10 15 20 25 30 0 0.5 1.0 1.5 2.0 I D , D R A IN C U R R E N T ( A ) VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 6V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 5V VGS = 7V VGS = 10V TA = 25 oC 50 55 60 65 70 75 80 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ID, DRAIN CURRENT (A) VGS = 6V VGS = 10V D R A IN T O S O U R C E O N R E S IS T A N C E ( m Ω ) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 160 N O R M A L IZ E D D R A IN T O S O U R C E TJ, JUNCTION TEMPERATURE ( oC) O N R E S IS T A N C E VGS = 10V, ID = 4.5A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

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©2004 Fairchild Semiconductor Corporation FDS3992 Rev. C F D S 3 9 9 2 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature Figure 13. Capacitance vs Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Currents Typical Characteristics TA = 25°C unless otherwise noted 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 N O R M A L IZ E D G A T E TJ, JUNCTION TEMPERATURE ( oC) VGS = VDS, ID = 250µA T H R E S H O L D V O L T A G E 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE ( oC) N O R M A L IZ E D D R A IN T O S O U R C E ID = 250µA B R E A K D O W N V O L T A G E 10 100 1000 0.1 1 10 100 2000 C , C A P A C IT A N C E ( p F ) VGS = 0V, f = 1MHz CISS = CGS + CGD COSS ≅ CDS + CGD CRSS = CGD VDS, DRAIN TO SOURCE VOLTAGE (V) 0 2 4 6 8 10 0 2 4 6 8 10 12 V G S , G A T E T O S O U R C E V O L T A G E ( V ) Qg, GATE CHARGE (nC) VDD = 50V ID = 4.5A ID = 2A WAVEFORMS IN DESCENDING ORDER:

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©2004 Fairchild Semiconductor Corporation FDS3992 Rev. C F D S 3 9 9 2 Test Circuits and Waveforms Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms tP VGS 0.01Ω L IAS + - VDS VDD RG DUT VARY tP TO OBTAIN REQUIRED PEAK IAS 0V VDD VDS BVDSS tP IAS tAV 0 VGS + - VDS VDD DUT Ig(REF) L VDD Qg(TH) VGS = 2V Qg(TOT) VGS = 10V VDS VGS Ig(REF) 0 0 Qgs Qgd Qgs2 VGS RL RGS DUT + - VDD VDS VGS tON td(ON) tr 90% 10% VDS 90% 10% tf td(OFF) tOFF 90% 50%50% 10% PULSE WIDTH VGS 0 0

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©2004 Fairchild Semiconductor Corporation FDS3992 Rev. C F D S 3 9 9 2 Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ( oC), and thermal resistance RθJA ( oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. The transient thermal impedance (ZθJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. (EQ. 1)P DM T JM T A –( ) RθJA ------------------------------= (EQ. 2)RθJA 64 26 0.23 Area+ -------------------------------+= 100 150 200 0.001 0.01 0.1 1 10 50 Figure 21. Thermal Resistance vs Mounting Pad Area RθJA = 64 + 26/(0.23+Area) R θ J A ( o C /W ) AREA, TOP COPPER AREA (in2) Figure 22. Thermal Impedance vs Mounting Pad Area 30 60 90 120 150 0 t, RECTANGULAR PULSE DURATION (s) Z θ J A , T H E R M A L COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 IM P E D A N C E ( o C /W ) 10-1 100 101 102 103

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©2004 Fairchild Semiconductor Corporation FDS3992 Rev. C F D S 3 9 9 2 PSPICE Electrical Model .SUBCKT FDS3992 2 1 3 ; rev Aug 2002 Ca 12 8 2.3e-10 Cb 15 14 3.5e-10 Cin 6 8 7.47e-10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 108 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1e-9 Lsource 3 7 1.98e-9 RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 25.e-3 Rgate 9 20 3.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 20e-3 Rvthres 22 8 Rvthresmod 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))} .MODEL DbodyMOD D (IS=2.4E-12 N=1.04 RS=13e-3 TRS1=2.1e-3 TRS2=4.7e-7 + CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6) .MODEL DbreakMOD D (RS=1.6 TRS1=2.4e-3 TRS2=-1e-5) .MODEL DplcapMOD D (CJO=1.6e-10 IS=1e-30 N=10 M=0.54) .MODEL MmedMOD NMOS (VTO=3.8 KP=2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.7) .MODEL MstroMOD NMOS (VTO=4.35 KP=28 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.26 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=37 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-8) .MODEL RdrainMOD RES (TC1=1.15e-2 TC2=2.8e-5) .MODEL RSLCMOD RES (TC1=3.3e-3 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-4.8e-3 TC2=-1.1e-5) .MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.5e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-3) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 19 22 12 13 15 S1A S1B S2A S2B CA CB EGS EDS 14 8 13 8 14 13 MWEAK EBREAK DBODY RSOURCE SOURCE 11 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 16 21 8 MMED MSTRO DRAIN 2 LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 10 5 51 50 RSLC2 1 GATE RGATE EVTEMP 9 ESG LGATE RLGATE 20 + - + - 6

FDS3992 Reviews

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Kade*****eema

December 6, 2019

It arrived on time. I was able to finish a repair before Sunday service and with no over time. Easy to work with.

Meli*****utala

November 10, 2019

The order has arrived ahead of time, we appreciate it very much!! Thanks

Jale*****nnedy

November 1, 2019

Very fast reply, professional seller and received the correct parts.

Cor*****ice

October 31, 2019

EVERY OK ...GOOD ITEM AND SUPERFAST SHIPPING

Elean*****erian

May 31, 2019

Various selection and thoughtful services! Prices are competitive as well. Thank you!

Chan***** Reyes

January 16, 2019

It is so great to order from a supplier that provides so many shipping options at reasonable cost. It couldn't be any easier to order from Heisener. Great job!

Nata*****Perez

December 28, 2018

The helper is super handy, especially if you work with medium size PCB boards as it allows to hold the board steady in every position. It feels pretty sturdy and of good quality.

Bri*****Gray

December 8, 2018

Sure appreciate your quality, expertise and professional service. Thank you so much!!!

Rod***** Luna

November 8, 2018

Always meet my expectations with order and questions.

Augu*****e Bava

August 5, 2018

Great kit, cost half the price of other stores. Includes most items that someone would need.

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  • Fairchild/ON Semiconductor FDS3992
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