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ID82C82

hot ID82C82

ID82C82

For Reference Only

Part Number ID82C82
Manufacturer Renesas Electronics America
Description IC DRIVER BUS OCT LATCHING 20DIP
Datasheet ID82C82 Datasheet
Package 20-CDIP (0.300", 7.62mm)
In Stock 275 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Feb 28 - Mar 4 (Choose Expedited Shipping)
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ID82C82 Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Interface - Drivers, Receivers, Transceivers
Datasheet ID82C82 Datasheet
Package20-CDIP (0.300", 7.62mm)
Series-
TypeDriver
Number of Drivers/Receivers8/0
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C
Mounting TypeThrough Hole
Package / Case20-CDIP (0.300", 7.62mm)
Supplier Device Package20-CERDIP

ID82C82 Datasheet

Page 1

Page 2

FN2975 Rev 2.00 Aug 25, 2015 82C82 CMOS Octal Latching Bus Driver DATASHEETFeatures • Full Eight-Bit Parallel Latching Buffer • Bipolar 8282 Compatible • Three-State Noninverting Outputs • Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max. • Gated Inputs: - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors • Single 5V Power Supply • Low Power Operation. . . . . . . . . . . . . . . .ICCSB = 10A • Operating Temperature Ranges - C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC - I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Description The Intersil 82C82 is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C82 provides an eight-bit parallel latch/buffer in a 20 pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to state-of-the-art microprocessor systems. Pinouts 82C82 (PDIP, CERDIP) TOP VIEW 82C82 (PLCC, CLCC) TOP VIEW 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1DI0 DI1 DI2 DI3 DI4 DI5 DI7 DI6 OE GND VCC DO1 DO2 DO3 DO0 DO4 DO5 DO6 DO7 STB 193 2 201 15 16 17 18 14 9 10 11 12 13 4 5 6 7 8 DI4 DI5 DI6 DI7 DI3 O E G N D S T B D O 7 D O 6 DO2 DO3 DO4 DO5 DO1 D I 2 D I 1 D I 0 V C C D O 0 NO LO NG ER AV AI LA BL E O R SU PP OR TE D TRUTH TABLE STB OE DI DO X H X Hi-Z H L L L H L H H  L X † H = Logic One L = Logic Zero X = Don’t Care † = Latched to Value of Last Data Hi-Z = High Impedance  = Neg. Transition PIN NAMES PIN DESCRIPTION DI0-DI7 Data Input Pins DO0-DO7 Data Output Pins STB Active High Strobe OE Active Low Output EnableFN2975 Rev 2.00 Page 1 of 8 Aug 25, 2015

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82C82Functional Diagram Gated Inputs During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transi- tions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switching threshold. Additionally, if the driv- ing signal becomes high impedance (“float” condition), it could create an indeterminate logic state at the input and cause a dis- ruption in device operation. The Intersil 82C8X Series of bus drivers eliminates these condi- tions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-channel and lower N-channel (see Fig- ures 1, 2). No new current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level inter- nal to the device. Ordering Information PART NUMBER TEMP. RANGE PACKAGE PKG. NO. CP82C82 (No longer available) 0oC to +70oC 20 Ld PDIP E20.3 IP82C82 (No longer available) -40oC to +85oC CS82C82 (No longer available) 0oC to +70oC 20 Ld PLCC N20.35 IS82C82 (No longer available) -40oC to +85oC CD82C82 (No longer available) 0oC to +70oC 20 Ld CERDIP F20.3 ID82C82 (No longer available) -40oC to +85oC MD82C82/B (No longer available) -55oC to +125oC 8406701RA SMD # MR82C82/B (No longer available) -55oC to +125oC 20 Pad CLCC J20.A 84067012A(No longer available) SMD # DIO DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 OESTB D Q CLKFN2975 Rev 2.00 Page 2 of 8 Aug 25, 2015

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82C82 F A DC input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input cir- cuitry in its linear operating region (partially conducting state). The 82C8X series gated inputs mean that this condi- tion will occur only during the time the device is in the trans parent mode (STB = logic one). ICC remains below the max- imum ICC standby specification of l0mA during the time inputs are disabled, thereby, greatly reducing the average power dissipation of the 82C8X series devices Typical 82C82 System Example In a typical 80C86/88 system, the 82C82 is used to latch multiplexed addresses and the STB input is driven by ALE (Address Latch Enable) (see Figure 3). The high pulse width of ALE is approximately 100ns with a bus cycle time of 800ns (80C86/88 at 5MHz). The 82C82 inputs are active only 12.5% of the bus cycle time. Average power dissipation related to input transitioning is reduced by this factor also. Application Information Decoupling Capacitors The transient current required to charge and discharge the 300pF load capacitance specified in the 82C82 data sheet is determined by: Assuming that all outputs change state at the same time and that dv/dt is constant; where tR = 20ns, VCC = 5.0V, CL = 300pF on each of eight outputs. FIGURE 1. 82C82/83H FIGURE 2. 82C86H/87H GATED INPUTS P P P N N NSTB DATA IN INTERNAL DATA VCC VCC P P N N OE DATA IN INTERNAL DATA VCC P N VCC I CL= (dv/dt) (EQ. 1) I CL= (EQ. 2) VCC x 80%  tR/tF ----------------------------------- (EQ. 3) I = 8 x 300 x 10 -12 x (5.0V x 0.8)/ 20 x 10 9–  = 480mA (EQ. 4) FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS ADDRESSADDRESS ALE MULTIPLEXED ICC BUS P P N N STB DATA IN INTERNAL DATA VCC P N VCCN2975 Rev 2.00 Page 3 of 8 ug 25, 2015

Page 5

82C82 F A Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC M82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Thermal Resistance (Typical) JA JC CERDIP. . . . . . . . . . . . . . . . . . . . . . . . 75oC/W 18oC/W CLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 85oC/W 22oC/W PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 75 N/A PLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 75 N/A Storage Temperature Range. . . . . . . . . . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Minimum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC (PLCC Lead Tips Only) Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications VCC = 5.0V 10%; TA = 0oC to +70oC (C82C82); TA = -40 oC to +85oC (I82C82); TA = -55 oC to +125oC (M82C82) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V C82C82, I82C82 (Note 1) 2.2 - V M82C82 (Note 1) VIL Logical Zero Input Voltage - 0.8 V VOH Logical One Output Voltage 2.9 - V IOH = -8mA, OE = GND VCC -0.4V - V IOH = -100A, OE = GND VOL Logical Zero Output Voltage - 0.4 V IOL = 8mA, OE = GND II Input Leakage Current -1.0 1.0 A VIN = GND or VCC, DIP Pins 1-9, 11 IO Output Leakage Current -10.0 10.0 A VO = GND or VCC, OE  VCC -0.5V DIP Pins 12-19 ICCSB Standby Power Supply Cur- rent - 10 A VIN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current - 1 mA/MHz TA = +25 oC, VCC = 5V, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VIH min to one data input at a time and checking the corresponding device output for a valid logical “1” during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at VCC -0.4. 2. Typical ICCOP = 1mA/MHz of STB cycle time. (Example: 5MHz P, ALE = 1.25MHz, ICCOP = 1.25mA). Capacitance TA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 13 pF Freq = 1MHz, all measurements are referenced to device GND COUT Output Capacitance 20 pFN2975 Rev 2.00 ug 25, 2015Page 4 of 8

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82C82Timing Waveforms AC Electrical Specifications VCC = 5.0V 10%; TA = 0oC to +70oC (C82C82); CL = 300pF (Note 1), Freq = 1MHz TA = -40 oC to +85oC (I82C82); TA = -55 oC to +125oC (M82C82) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS (1) TIVOV Propagation Delay Input to Output - 35 ns Notes 2, 3 (2) TSHOV Propagation Delay STB to Output - 55 ns Notes 2, 3 (3) TEHOZ Output Disable Time - 35 ns Notes 2, 3 (4) TELOV Output Enable Time - 50 ns Notes 2, 3 (5) TIVSL Input to STB Setup Time 0 - ns Notes 2, 3 (6) TSLIX Input to STB Hold Time 25 - ns Notes 2, 3 (7) TSHSL STB High Time 25 - ns Notes 2, 3 (8) TR, TF Input Rise/Fall Times - 20 ns Notes 2, 3 NOTES: 1. Output load capacitance is rated at 300pF for ceramic and plastic packages. 2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V. 3. Input test signals must switch between VIL - 0.4V and VIH +0.4V. TR, TF (8) TIVSL (5) TSLIX (6) 2.0V 0.8V VOH -0.1V TELOV (4) VOL +0.1V 2.4V 0.8V TEHOZ (3) TSHSL (7) (1) TIVOV TSHOV (2) INPUTS STB OUTPUTS OE Test Load Circuits NOTE: Includes stray and jig capacitance. OUTPUT TEST 300pF 150 1.7V POINT (NOTE) TIVOV, TSHOV, TELOV OUTPUT TEST 50pF 300 0.6V POINT (NOTE) TEHOZ OUTPUT HIGH DISABLE OUTPUT TEST 50pF 300 3.3V POINT (NOTE) TEHOZ OUTPUT LOW DISABLEFN2975 Rev 2.00 Page 5 of 8 Aug 25, 2015

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82C82 F A Burn-In Circuits MD82C82 CERDIP MR82C82 CLCC NOTES: 1. VCC = 5.5 0.5V, GND = 0V. 2. VIH = 4.5V 10%. 3. VIL = -0.2V to 0.4V. 4. R1 = 47k 5%. 5. R2 = 2.0k 5%. 6. R3 = 4.2k 5%. 7. R4 = 470k 5%. 8. C1 = 0.01F minimum. 9. F0 = 100kHz 10%. 10. F1 = F0/2, F2 = F1/2. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 R1 F2 A R2 VCC R1 F2 R1 F2 R1 F2 R1 F2 R1 F2 R1 F2 R1 F2 R1 F0 R1 A A A A A A A A F1 VCC C1 R2 R3 R3 F2 VCC/2 C1 4 5 6 7 8 10 11 12 139 3 2 1 20 19 16 17 18 15 14 R3 VCC/2 R3 VCC/2 R3 VCC/2 R3 VCC/2 R3 VCC/2 R3 R3 R3 R3 R3 F2 F2 F2 F2 F2 R3 F2 R3 F2 R3 R3R3R3 F0 F1 VCC/2 VCC VCC/2N2975 Rev 2.00 Page 6 of 8 ug 25, 2015

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82C82Die Characteristics DIE DIMENSIONS: 118.1 x 92.1 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ 1kÅ WORST CASE CURRENT DENSITY: 2.00 x 105 A/cm2 Metallization Mask Layout 82C82 2 3 1 20 19 18 17 16 15 14 13 121110 4 5 6 7 8 9 D11 D10 VCC DO0 D01 D12 D13 D14 D15 D16 D17 OE GND STB DO7 DO6 DO5 DO4 DO3 DO2Page 7 of 8FN2975 Rev 2.00 Aug 25, 2015

ID82C82 Reviews

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Land*****amdar

February 9, 2020

Excellent service over extended period of time. Incredibly fast shipping, never any errors. Couldn't be more pleased.

Kai*****Anne

December 4, 2019

So far all the items still work. I'm using these for some home made solar panels and they're doing great.

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November 22, 2019

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November 15, 2019

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November 13, 2019

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November 3, 2019

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November 1, 2019

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September 23, 2019

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September 19, 2019

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September 16, 2019

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