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IRFR3711ZTRPBF

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IRFR3711ZTRPBF

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Part Number IRFR3711ZTRPBF
Manufacturer Infineon Technologies
Description MOSFET N-CH 20V 93A DPAK
Datasheet IRFR3711ZTRPBF Datasheet
Package TO-252-3, DPak (2 Leads + Tab), SC-63
In Stock 4,000 piece(s)
Unit Price $ 0.4740 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 27 - Oct 2 (Choose Expedited Shipping)
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Part Number # IRFR3711ZTRPBF (Transistors - FETs, MOSFETs - Single) is manufactured by Infineon Technologies and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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IRFR3711ZTRPBF Specifications

ManufacturerInfineon Technologies
CategoryDiscrete Semiconductor Products - Transistors - FETs, MOSFETs - Single
Datasheet IRFR3711ZTRPBFDatasheet
PackageTO-252-3, DPak (2 Leads + Tab), SC-63
SeriesHEXFET?
FET TypeN-Channel
TechnologyMOSFET (Metal Oxide)
Drain to Source Voltage (Vdss)20V
Current - Continuous Drain (Id) @ 25°C93A (Tc)
Drive Voltage (Max Rds On, Min Rds On)4.5V, 10V
Vgs(th) (Max) @ Id2.45V @ 250µA
Gate Charge (Qg) (Max) @ Vgs27nC @ 4.5V
Input Capacitance (Ciss) (Max) @ Vds2160pF @ 10V
Vgs (Max)��20V
FET Feature-
Power Dissipation (Max)79W (Tc)
Rds On (Max) @ Id, Vgs5.7 mOhm @ 15A, 10V
Operating Temperature-55°C ~ 175°C (TJ)
Mounting TypeSurface Mount
Supplier Device PackageD-Pak
Package / CaseTO-252-3, DPak (2 Leads + Tab), SC-63

IRFR3711ZTRPBF Datasheet

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www.irf.com 1 12/13/04 IRFR3711ZPbF IRFU3711ZPbF HEXFETPower MOSFET Notes through  are on page 11 Applications Benefits  Very Low RDS(on) at 4.5V VGS  Ultra-Low Gate Impedance  Fully Characterized Avalanche Voltage and Current  High Frequency Synchronous Buck Converters for Computer Processor Power  High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use  Lead-Free D-Pak IRFR3711Z I-Pak IRFU3711Z  Absolute Maximum Ratings Parameter Units VDS Drain-to-Source Voltage V VGS Gate-to-Source Voltage ID @ TC = 25°C Continuous Drain Current, VGS @ 10V ID @ TC = 100°C Continuous Drain Current, VGS @ 10V A IDM Pulsed Drain Current PD @TC = 25°C Maximum Power Dissipation  W PD @TC = 100°C Maximum Power Dissipation  Linear Derating Factor W/°C TJ Operating Junction and °C TSTG Storage Temperature Range Soldering Temperature, for 10 seconds Thermal Resistance Parameter Typ. Max. Units RθJC Junction-to-Case ––– 1.9 RθJA Junction-to-Ambient (PCB Mount)  ––– 50 °C/W RθJA Junction-to-Ambient ––– 110 79 Max. 93 66 370 ± 20 20 0.53 39 300 (1.6mm from case) -55 to + 175 VDSS RDS(on) max Qg 20V 5.7m 18nC

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  2 www.irf.com Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage 20 ––– ––– V ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 13 ––– mV/°C RDS(on) Static Drain-to-Source On-Resistance ––– 4.5 5.7 mΩ ––– 6.2 7.8 VGS(th) Gate Threshold Voltage 1.55 2.0 2.45 V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.4 ––– mV/°C IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA ––– ––– 150 IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA Gate-to-Source Reverse Leakage ––– ––– -100 gfs Forward Transconductance 48 ––– ––– S Qg Total Gate Charge ––– 18 27 Qgs1 Pre-Vth Gate-to-Source Charge ––– 5.1 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 1.8 ––– nC Qgd Gate-to-Drain Charge ––– 6.5 ––– Qgodr Gate Charge Overdrive ––– 4.6 ––– See Fig. 16 Qsw Switch Charge (Qgs2 + Qgd) ––– 8.3 ––– Qoss Output Charge ––– 9.8 ––– nC td(on) Turn-On Delay Time ––– 12 ––– tr Rise Time ––– 13 ––– td(off) Turn-Off Delay Time ––– 15 ––– ns tf Fall Time ––– 5.2 ––– Ciss Input Capacitance ––– 2160 ––– Coss Output Capacitance ––– 700 ––– pF Crss Reverse Transfer Capacitance ––– 360 ––– Avalanche Characteristics Parameter Units EAS Single Pulse Avalanche Energy mJ IAR Avalanche Current A EAR Repetitive Avalanche Energy  mJ Diode Characteristics Parameter Min. Typ. Max. Units IS Continuous Source Current ––– ––– 93 (Body Diode) A ISM Pulsed Source Current ––– ––– 370 (Body Diode) VSD Diode Forward Voltage ––– ––– 1.0 V trr Reverse Recovery Time ––– 19 28 ns Qrr Reverse Recovery Charge ––– 9.4 14 nC ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) MOSFET symbol ––– VGS = 4.5V Typ. ––– ––– ID = 12A VGS = 0V VDS = 10V Clamped Inductive Load TJ = 25°C, IF = 12A, VDD = 10V di/dt = 100A/µs  TJ = 25°C, IS = 12A, VGS = 0V  showing the integral reverse p-n junction diode. VDS = 10V, ID = 12A VDS = 10V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 12A VDS = 10V Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 1mA VGS = 10V, ID = 15A  VGS = 4.5V, ID = 12A  VGS = 20V VGS = -20V VDS = VGS, ID = 250µA VDS = 16V, VGS = 0V VDS = 16V, VGS = 0V, TJ = 125°C Conditions 7.9 Max. 140 12 ƒ = 1.0MHz

Page 4

  www.irf.com 3 Fig 4. Normalized On-Resistance vs. Temperature Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics Fig 3. Typical Transfer Characteristics 0.1 1 10 VDS, Drain-to-Source Voltage (V) 0.1 1 10 100 1000 I D , D ra in -t o -S o u rc e C u rr e n t (A ) 2.5V 20µs PULSE WIDTH Tj = 25°C VGS TOP 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 0.1 1 10 VDS, Drain-to-Source Voltage (V) 1 10 100 1000 I D , D ra in -t o -S o u rc e C u rr e n t (A ) 2.5V 20µs PULSE WIDTH Tj = 175°C VGS TOP 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, Gate-to-Source Voltage (V) 1 10 100 1000 I D , D ra in -t o -S o u rc e C u rr e n t (Α ) TJ = 25°C TJ = 175°C VDS = 10V 20µs PULSE WIDTH -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature (°C) 0.5 1.0 1.5 2.0 R D S (o n ) , D ra in -t o -S o u rc e O n R e s is ta n c e (N o rm a liz e d ) ID = 30A VGS = 10V

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  4 www.irf.com Fig 8. Maximum Safe Operating Area Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 7. Typical Source-Drain Diode Forward Voltage 1 10 100 VDS, Drain-to-Source Voltage (V) 100 1000 10000 C , C a p a c it a n c e ( p F ) Coss Crss Ciss VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd 0 10 20 30 40 QG Total Gate Charge (nC) 0 2 4 6 8 10 12 V G S , G a te -t o -S o u rc e V o lt a g e ( V ) VDS= 18V VDS= 10V ID= 12A 0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-toDrain Voltage (V) 0.1 1.0 10.0 100.0 1000.0 I S D , R e v e rs e D ra in C u rr e n t (A ) TJ = 25°C TJ = 175°C VGS = 0V 0.1 1.0 10.0 100.0 1000.0 VDS , Drain-toSource Voltage (V) 1 10 100 1000 I D , D ra in -t o -S o u rc e C u rr e n t (A ) Tc = 25°C Tj = 175°C Single Pulse 1msec 10msec OPERATION IN THIS AREA LIMITED BY R DS(on) 100µsec

Page 6

  www.irf.com 5 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature 25 50 75 100 125 150 175 TC , Case Temperature (°C) 0 20 40 60 80 100 I D , D ra in C u rr e n t (A ) LIMITED BY PACKAGE -75 -50 -25 0 25 50 75 100 125 150 175 TJ , Temperature ( °C ) 0.0 0.5 1.0 1.5 2.0 2.5 V G S (t h ) G a te t h re s h o ld V o lt a g e ( V ) ID = 250µA 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) 0.001 0.01 0.1 1 10 T h e rm a l R e s p o n s e ( Z t h J C ) 0.20 0.10 D = 0.50 0.02 0.01 0.05 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc Ri (°C/W) τi (sec) 0.805 0.000237 0.606 0.001005 0.492 0.101628 τ J τ J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 R 1 R 1 R 2 R 2 R 3 R 3 τ τ C Ci= i/Ri Ci= τi/Ri

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  6 www.irf.com D.U.T. VDS IDIG 3mA VGS .3µF 50KΩ .2µF12V Current Regulator Same Type as D.U.T. Current Sampling Resistors + - Fig 13. Gate Charge Test Circuit Fig 12b. Unclamped Inductive Waveforms Fig 12a. Unclamped Inductive Test Circuit tp V(BR)DSS IAS Fig 12c. Maximum Avalanche Energy Vs. Drain Current RG IAS 0.01Ωtp D.U.T LVDS + - VDD DRIVER A 15V 20VVGS 25 50 75 100 125 150 175 Starting TJ, Junction Temperature (°C) 0 100 200 300 400 500 600 E A S , S in g le P u ls e A v a la n c h e E n e rg y ( m J ) I D TOP 7.7A 8.9A BOTTOM 12A Fig 14a. Switching Time Test Circuit Fig 14b. Switching Time Waveforms V GS V DS 90% 10% t d(on) td(off)tr tf V GS Pulse Width < 1µs Duty Factor < 0.1% VDD VDS LD D.U.T + -

Page 8

  www.irf.com 7 Fig 15.      for N-Channel HEXFETPower MOSFETs     •       •      •           P.W. Period di/dt Diode Recovery dv/dt Ripple ≤ 5% Body Diode Forward Drop Re-Applied Voltage Reverse Recovery Current Body Diode Forward Current VGS=10V VDD ISD Driver Gate Drive D.U.T. ISD Waveform D.U.T. VDS Waveform Inductor Curent D = P.W. Period      + - + + +- - -     •     •    !"!! •     #  $$ • !"!!%"     Fig 16. Gate Charge Waveform Vds Vgs Id Vgs(th) Qgs1 Qgs2 Qgd Qgodr

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  8 www.irf.com Control FET                                              !"    #  $   %& !"         #                        #' P loss = P conduction + P switching + P drive + P output This can be expanded and approximated by; Ploss = Irms 2 × Rds(on )( ) + I × Qgd ig × Vin × f ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ + I × Qgs 2 ig × Vin × f ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ + Qg × Vg × f( ) + Qoss 2 ×Vin × f ⎛ ⎝ ⎞ ⎠ "     (                  %& !"                           %& !"      "                                  )             #                             *                 % +                                        %& !"   #      #  ,         #              -   .   /           #    #       Synchronous FET The power loss equation for Q2 is approximated by; Ploss = Pconduction + Pdrive + Poutput * Ploss = Irms 2 × Rds(on)( ) + Qg × Vg × f( ) + Qoss 2 × Vin × f ⎛ ⎝ ⎜ ⎞ ⎠ + Qrr × Vin × f( ) *dissipated primarily in Q1. For the synchronous MOSFET Q2, R ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the con- trol IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and re- verse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions be- tween ground and V in . As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is ca- pacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on. Power MOSFET Selection for Non-Isolated DC/DC Converters Figure A: Q oss Characteristic

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  www.irf.com 9        0         -  . 12IN THE ASS EMBLY LINE "A" ASSEMBLED ON WW 16, 1999 EXAMPLE: WITH AS SEMBLY THIS IS AN IRFR120 LOT CODE 1234 YEAR 9 = 1999 DATE CODE WEEK 16 PART NUMBER LOGO INTERNATIONAL RECTIFIER ASS EMBLY LOT CODE 916A IRFU120 34 YEAR 9 = 1999 DATE CODE OR P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) Note: "P" in assembly line position indicates "Lead-Free" 12 34 WEEK 16 A = ASS EMBLY SITE CODE PART NUMBER IRFU120 LINE A LOGO LOT CODE ASS EMBLY INTERNATIONAL RECTIFIER

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