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L6205D013TR

hotL6205D013TR

L6205D013TR

For Reference Only

Part Number L6205D013TR
Manufacturer STMicroelectronics
Description IC MOTOR DRIVER PAR 20SOIC
Datasheet L6205D013TRDatasheet
Package 20-SOIC (0.295", 7.50mm Width)
In Stock 3508 piece(s)
Unit Price $ 3.0842 *
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L6205D013TR

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L6205D013TRSpecifications

ManufacturerSTMicroelectronics
CategoryIntegrated Circuits (ICs) - PMIC - Motor Drivers, Controllers
Datasheet L6205D013TRDatasheet
Package20-SOIC (0.295", 7.50mm Width)
Series-
Motor Type - StepperBipolar
Motor Type - AC, DCBrushed DC
FunctionDriver - Fully Integrated, Control and Power Stage
Output ConfigurationHalf Bridge (4)
InterfaceParallel
TechnologyBiCDMOS
ApplicationsGeneral Purpose
Current - Output2.8A
Voltage - Supply8 V ~ 52 V
Voltage - Load8 V ~ 52 V
Operating Temperature-25°C ~ 125°C (TJ)
Mounting TypeSurface Mount
Package / Case20-SOIC (0.295", 7.50mm Width)
Supplier Device Package20-SOIC

L6205D013TRDatasheet

Page 1

Page 2

1/21 L6205 September 2003 ■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V ■ 5.6A OUTPUT PEAK CURRENT (2.8A DC) ■ RDS(ON) 0.3Ω TYP. VALUE @ Tj = 25 °C ■ OPERATING FREQUENCY UP TO 100KHz ■ NON DISSIPATIVE OVERCURRENT PROTECTION ■ PARALLELED OPERATION ■ CROSS CONDUCTION PROTECTION ■ THERMAL SHUTDOWN ■ UNDER VOLTAGE LOCKOUT ■ INTEGRATED FAST FREE WHEELING DIODES TYPICAL APPLICATIONS ■ BIPOLAR STEPPER MOTOR ■ DUAL OR QUAD DC MOTOR DESCRIPTION The L6205 is a DMOS Dual Full Bridge designed for motor control applications, realized in MultiPower- BCD technology, which combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. Available in PowerDIP20 (16+2+2), PowerSO20 and SO20(16+2+2) packages, the L6205 features a non-dissipative protection of the high side PowerMOSFETs and thermal shutdown. BLOCK DIAGRAM D99IN1091A GATE LOGIC OVER CURRENT DETECTION OVER CURRENT DETECTION GATE LOGIC VCP VBOOT ENA IN1A IN2A ENB IN1B IN2B VBOOT 5V 10V VSA VSB OUT1A OUT2A OUT1B OUT2B SENSEA CHARGE PUMP VOLTAGE REGULATOR THERMAL PROTECTION VBOOT VBOOT 10V 10V BRIDGE A BRIDGE B SENSEB OCDA OCDB ORDERING NUMBERS: L6205N (PowerDIP20) L6205PD (PowerSO20) L6205D (SO20) PowerDIP20 (16+2+2) PowerSO20 SO20 (16+2+2) DMOS DUAL FULL BRIDGE DRIVER

Page 3

L6205 2/21 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Symbol Parameter Test conditions Value Unit VS Supply Voltage VSA = VSB = VS 60 V VOD Differential Voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND 60 V VBOOT Bootstrap Peak Voltage VSA = VSB = VS VS + 10 V VIN,VEN Input and Enable Voltage Range -0.3 to +7 V VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSEB -1 to +4 V IS(peak) Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1ms 7.1 A IS RMS Supply Current (for each VS pin) VSA = VSB = VS 2.8 A Tstg, TOP Storage and Operating Temperature Range -40 to 150 °C Symbol Parameter Test Conditions MIN MAX Unit VS Supply Voltage VSA = VSB = VS 8 52 V VOD Differential Voltage Between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB 52 V VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSEB (pulsed tW < trr) (DC) -6 -1 6 1 V V IOUT RMS Output Current 2.8 A Tj Operating Junction Temperature -25 +125 °C fsw Switching Frequency 100 KHz

Page 4

3/21 L6205 THERMAL DATA PIN CONNECTIONS (Top View) (5) The slug is internally connected to pins 1,10,11 and 20 (GND pins). Symbol Description PowerDIP20 SO20 PowerSO20 Unit Rth-j-pins MaximumThermal Resistance Junction-Pins 12 14 - °C/W Rth-j-case Maximum Thermal Resistance Junction-Case - - 1 °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 1 (1) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35µm). 40 51 - °C/W Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 2 (2) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm). - - 35 °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 3 (3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes and a ground layer. - - 15 °C/W Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient 4 (4) Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board. 56 77 62 °C/W PowerDIP20/SO20 PowerSO20 (5) GND OUT1A SENSEA IN2A IN1A VCP ENA OUT2A VSA VSB OUT2B VBOOT IN2B ENB IN1B SENSEB OUT1B GND10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 GND GND D99IN1092A GND OUT1B SENSEB IN1B IN2B 1 3 2 4 5 6 7 8 9 ENB VBOOT OUT2B VSB GND15 14 13 12 11 D99IN1093A 10 20 19 18 17 16 IN1A IN2A SENSEA OUT1A GND GND VSA OUT2A VCP ENA

Page 5

L6205 4/21 (6) Also connected at the output drain of the Overcurrent and Thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2kΩ - 180KΩ, recommended 100kΩ PIN DESCRIPTION PACKAGE Name Type Function SO20/ PowerDIP20 PowerSO20 PIN # PIN # 1 6 IN1A Logic Input Bridge A Logic Input 1. 2 7 IN2A Logic Input Bridge A Logic Input 2. 3 8 SENSEA Power Supply Bridge A Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 4 9 OUT1A Power Output Bridge A Output 1. 5, 6, 15, 16 1, 10, 11, 20 GND GND Signal Ground terminals. In PowerDIP and SO packages, these pins are also used for heat dissipation toward the PCB. 7 12 OUT1B Power Output Bridge B Output 1. 8 13 SENSEB Power Supply Bridge B Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 9 14 IN1B Logic Input Bridge B Logic Input 1. 10 15 IN2B Logic Input Bridge B Logic Input 2. 11 16 ENB Logic Input (6) Bridge B Enable. LOW logic level switches OFF all Power MOSFETs of Bridge B. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor. 12 17 VBOOT Supply Voltage Bootstrap Voltage needed for driving the upper PowerMOSFETs of both Bridge A and Bridge B. 13 18 OUT2B Power Output Bridge B Output 2. 14 19 VSB Power Supply Bridge B Power Supply Voltage. It must be connected to the supply voltage together with pin VSA. 17 2 VSA Power Supply Bridge A Power Supply Voltage. It must be connected to the supply voltage together with pin VSB. 18 3 OUT2A Power Output Bridge A Output 2. 19 4 VCP Output Charge Pump Oscillator Output. 20 5 ENA Logic Input (6) Bridge A Enable. LOW logic level switches OFF all Power MOSFETs of Bridge A. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor.

Page 6

5/21 L6205 ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol Parameter Test Conditions Min Typ Max Unit VSth(ON) Turn-on Threshold 6.6 7 7.4 V VSth(OFF) Turn-off Threshold 5.6 6 6.4 V IS Quiescent Supply Current All Bridges OFF; Tj = -25°C to 125°C (7) 5 10 mA Tj(OFF) Thermal Shutdown Temperature 165 °C Output DMOS Transistors RDS(ON) High-Side Switch ON Resistance Tj = 25 °C 0.34 0.4 Ω Tj =125 °C (7) 0.53 0.59 Ω Low-Side Switch ON Resistance Tj = 25 °C 0.28 0.34 Ω Tj =125 °C (7) 0.47 0.53 Ω IDSS Leakage Current EN = Low; OUT = VS 2 mA EN = Low; OUT = GND -0.15 mA Source Drain Diodes VSD Forward ON Voltage ISD = 2.8A, EN = LOW 1.15 1.3 V trr Reverse Recovery Time If = 2.8A 300 ns tfr Forward Recovery Time 200 ns Logic Input VIL Low level logic input voltage -0.3 0.8 V VIH High level logic input voltage 2 7 V IIL Low Level Logic Input Current GND Logic Input Voltage -10 µA IIH High Level Logic Input Current 7V Logic Input Voltage 10 µA Vth(ON) Turn-on Input Threshold 1.8 2.0 V Vth(OFF) Turn-off Input Threshold 0.8 1.3 V Vth(HYS) Input Threshold Hysteresis 0.25 0.5 V Switching Characteristics tD(on)EN Enable to out turn ON delay time (8) ILOAD =2.8A, Resistive Load 100 250 400 ns tD(on)IN Input to out turn ON delay time ILOAD =2.8A, Resistive Load (dead time included) 1.6 µs tRISE Output rise time(8) ILOAD =2.8A, Resistive Load 40 250 ns tD(off)EN Enable to out turn OFF delay time (8) ILOAD =2.8A, Resistive Load 300 550 800 ns

Page 7

L6205 6/21 (7) Tested at 25°C in a restricted range and guaranteed by characterization. (8) See Fig. 1. (9) See Fig. 2. Figure 1. Switching Characteristic Definition tD(off)IN Input to out turn OFF delay time ILOAD =2.8A, Resistive Load 600 ns tFALL Output Fall Time (8) ILOAD =2.8A, Resistive Load 40 250 ns tdt Dead Time Protection 0.5 1 µs fCP Charge pump frequency -25°C

Page 8

7/21 L6205 Figure 2. Overcurrent Detection Timing Definition ISOVER 90% 10% IOUT VEN tOCD(OFF)tOCD(ON) D02IN1399 ON OFF BRIDGE

Page 9

L6205 8/21 CIRCUIT DESCRIPTION POWER STAGES and CHARGE PUMP The L6205 integrates two independent Power MOS Full Bridges. Each Power MOS has an Rd- son=0.3ohm (typical value @ 25°C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1µs typical) be- tween the switch off and switch on of two Power MOS in one leg of a bridge. Using N Channel Power MOS for the upper transis- tors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped (Vboot) supply is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 3. The oscillator output (VCP) is a square wave at 600kHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table1. Table 1. Charge Pump External Components Values Figure 3. Charge Pump Circuit LOGIC INPUTS Pins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and µC compatible logic inputs. The internal structure is shown in Fig. 4. Typical value for turn-on and turn-off thresholds are respectively Vthon=1.8V and Vthoff=1.3V. Pins ENA and ENB have identical input structure with the exception that the drains of the Overcurrent and thermal protection MOSFETs (one for the Bridge A and one for the Bridge B) are also connected to these pins. Due to these connections some care needs to be taken in driving these pins. The ENA and ENB in- puts may be driven in one of two configurations as shown in figures 5 or 6. If driven by an open drain (collector) structure, a pull-up resistor REN and a ca- pacitor CEN are connected as shown in Fig. 5. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig. 6. The resistor REN should be chosen in the range from 2.2kΩ to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF. More information on selecting the values is found in the Overcurrent Protection section. Figure 4. Logic Inputs Internal Structure Figure 5. ENA and ENB Pins Open Collector Driving Figure 6. ENA and ENB Pins Push-Pull Driving TRUTH TABLE X = Don't care High Z = High Impedance Output CBOOT 220nF CP 10nF RP 100Ω D1 1N4148 D2 1N4148 D2 CBOOTD1 RP CP VS VSAVCP VBOOT VSB D01IN1328 INPUTS OUTPUTS EN IN1 IN2 OUT1 OUT2 L X X High Z High Z H L L GND GND H H L Vs GND H L H GND Vs H H H Vs Vs 5V D01IN1329 ESD PROTECTION 5V 5V OPEN COLLECTOR OUTPUT REN CEN ENA or ENB D02IN1349 5V PUSH-PULL OUTPUT REN CEN ENA or ENB D02IN1350

Page 10

9/21 L6205 NON-DISSIPATIVE OVERCURRENT PROTECTION The L6205 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external cur- rent sense resistor normally used and its associated power dissipation are eliminated. Figure 7 shows a simpli- fied schematic of the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the out- put current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference cur- rent IREF. When the output current in one bridge reaches the detection threshold (typically 5.6A) the relative OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an ex- ternal R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. Figure 7. Overcurrent Protection Simplified Schematic Figure 8 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal opera- tion can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 9. The Delay Time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 10. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should be chosen according to the desired Disable Time. The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time. + OVER TEMPERATURE IREF (I1A+I2A) / n I1A / n POWER SENSE 1 cell POWER SENSE 1 cellPOWER DMOS n cells POWER DMOS n cells HIGH SIDE DMOSs OF THE BRIDGE A OUT1A OUT2A VSA I1A I2A I2A / nOCD COMPARATOR TO GATE LOGIC INTERNAL OPEN-DRAIN RDS(ON) 40Ω TYP. CEN REN ENA +5V µC or LOGIC D02IN1353

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L6205D013TRGuarantees

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