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M24C01-WMN6TP/S

hot M24C01-WMN6TP/S

M24C01-WMN6TP/S

For Reference Only

Part Number M24C01-WMN6TP/S
Manufacturer STMicroelectronics
Description IC EEPROM 1KBIT 400KHZ 8SO
Datasheet M24C01-WMN6TP/S Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 707 piece(s)
Unit Price $ 0.2696 *
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M24C01-WMN6TP/S

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M24C01-WMN6TP/S Specifications

ManufacturerSTMicroelectronics
CategoryIntegrated Circuits (ICs) - Memory
Datasheet M24C01-WMN6TP/S Datasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
Memory TypeNon-Volatile
Memory FormatEEPROM
TechnologyEEPROM
Memory Size1Kb (128 x 8)
Clock Frequency400kHz
Write Cycle Time - Word, Page5ms
Access Time900ns
Memory InterfaceI2C
Voltage - Supply2.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SO

M24C01-WMN6TP/S Datasheet

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This is information on a product in full production. October 2017 DocID024020 Rev 6 1/42 M24C01/02-W M24C01/02-R M24C02-F 1-Kbit and 2-Kbit serial I²C bus EEPROMs Datasheet - production data PDIP8 (BN)(1) TSSOP8 (DW) 169 mil width UFDFPN8 (MC) DFN8 - 2 x 3 mm SO8 (MN) 150 mil width UFDFPN5 (MH) DFN5 - 1.7 x 1.4 mm 1. Not recommended for new designs Features • Compatible with I2C bus modes: – 400 kHz – 100 kHz • Memory array: – 1 Kbit (128 bytes) of EEPROM – 2 Kbit (256 bytes) of EEPROM – Page size: 16 byte • Single supply voltage: – M24C01/02-W: 2.5 V to 5.5 V – M24C01/02-R: 1.8 V to 5.5 V – M24C02-F: 1.7 V to 5.5 V (full temperature range) and 1.6 V to 1.7 V (limited temperature range) • Write: – Byte Write within 5 ms – Page Write within 5 ms • Operating temperature range: – from -40 °C up to +85 °C • Random and sequential Read modes • Write protect of the whole memory array • Enhanced ESD/Latch-Up protection • More than 4 million Write cycles • More than 200-years data retention Packages • RoHS compliant and halogen-free (ECOPACK2®) www.st.com

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Contents M24C01/02-W M24C01/02-R M24C02-F 2/42 DocID024020 Rev 6 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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DocID024020 Rev 6 3/42 M24C01/02-W M24C01/02-R M24C02-F Contents 3 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 UFDFPN5 (DFN5) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.4 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.5 UFDFPN8 (DFN8) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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List of tables M24C01/02-W M24C01/02-R M24C02-F 4/42 DocID024020 Rev 6 List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 11. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12. DC characteristics (M24C01/02-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13. DC characteristics (M24C01/02-R device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14. DC characteristics (M24C02-F, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. 400 kHz AC characteristics (I2C Fast-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 16. 100 kHz AC characteristics (I2C Standard mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 17. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18. TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 35 Table 21. UFDFPN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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DocID024020 Rev 6 5/42 M24C01/02-W M24C01/02-R M24C02-F List of figures 5 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. UFDFPN5 (DFN5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 13. UFDFPN5 – 1.7x1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 14. UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 15. TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 16. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline . 33 Figure 17. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 18. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 35 Figure 19. UFDFPN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 20. UFDFPN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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Description M24C01/02-W M24C01/02-R M24C02-F 6/42 DocID024020 Rev 6 1 Description The M24C01(C02) is a 1(2)-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 128 (256) × 8 bits. The M24C01/02-W can be accessed with a supply voltage from 2.5 V to 5.5 V, the M24C01/02-R can be accessed with a supply voltage from 1.8 V to 5.5 V, and the M24C02-F can be accessed either with a supply voltage from 1.7 V to 5.5 V (over the full temperature range) or with an extended supply voltage from 1.6 V to 1.7 V if the temperature is reduced to 0 °C/ 85 °C. All these devices operate with a maximum clock frequency of 400 kHz. Figure 1. Logic diagram Figure 2. 8-pin package connections, top view Table 1. Signal names Signal name Function Direction E2, E1, E0(1) 1. Signal not connected in the DFN5 package. Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage - VSS Ground -

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DocID024020 Rev 6 7/42 M24C01/02-W M24C01/02-R M24C02-F Description 41 Figure 3. UFDFPN5 (DFN5) package connections 1. Inputs E2, E1, E0 are not connected, therefore read as (000). Please refer to Section 2.3 for further explanations.

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Signal description M24C01/02-W M24C01/02-R M24C02-F 8/42 DocID024020 Rev 6 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 11 indicates how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, as shown in Table 2: Device select code. When not connected (left floating), these inputs are read as low (0). For the UFDFPN5 package, the (E2,E1,E0) inputs are not connected, therefore read as (0,0,0). 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.

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DocID024020 Rev 6 9/42 M24C01/02-W M24C01/02-R M24C02-F Signal description 41 This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

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hotM24C01-WMN6TP/S M24C01-RMN6P STMicroelectronics, IC EEPROM 1KBIT 400KHZ 8SO, 8-SOIC (0.154", 3.90mm Width), - View
hotM24C01-WMN6TP/S M24C02-RMN6P STMicroelectronics, IC EEPROM 2KBIT 400KHZ 8SO, 8-SOIC (0.154", 3.90mm Width), - View
hotM24C01-WMN6TP/S M24C02-RDW6TP STMicroelectronics, IC EEPROM 2KBIT 400KHZ 8TSSOP, 8-TSSOP (0.173", 4.40mm Width), - View
hotM24C01-WMN6TP/S M24C08-FMH6TG STMicroelectronics, SERIAL I2C BUS EEPROM, 5-UFDFN, - View
hotM24C01-WMN6TP/S M24C04-FMH6TG STMicroelectronics, SERIAL I2C BUS EEPROM, 5-UFDFN, - View

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