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MAX1102EUA

hot MAX1102EUA

MAX1102EUA

For Reference Only

Part Number MAX1102EUA
Manufacturer Maxim Integrated
Description IC CODEC 8-BIT 2.7-3.6V 8-UMAX
Datasheet MAX1102EUA Datasheet
Package 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
In Stock 441 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Feb 27 - Mar 3 (Choose Expedited Shipping)
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MAX1102EUA

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MAX1102EUA Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Interface - CODECs
Datasheet MAX1102EUA Datasheet
Package8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Series-
TypeGeneral Purpose
Data InterfaceSerial
Resolution (Bits)8 b
Number of ADCs / DACs1 / 1
Sigma DeltaNo
Dynamic Range, ADCs / DACs (db) Typ59 / 55
Voltage - Supply, Analog2.7 V ~ 3.6 V
Voltage - Supply, Digital2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Supplier Device Package8-uMAX

MAX1102EUA Datasheet

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General Description The MAX1102/MAX1103/MAX1104 CODECs provide both an 8-bit analog-to-digital converter (ADC) and an 8-bit digital-to-analog converter (DAC) with a 4-wire logic interface. The MAX1102/MAX1103 include an onboard +2V/+4V reference, providing a well-regulat- ed, low noise reference for both the ADC and DAC. The MAX1104 offers ratiometric conversion, with the reference internally connected to VDD. The MAX1102/MAX1103/MAX1104 are low-cost, low- power CODECs for use with microcontrollers (µCs). They allow for greater flexibility when selecting a µC. Less expensive µCs without onboard converters can be used while maintaining overall system performance. The MAX1102 operates from a single +2.7V to +3.6V supply, the MAX1103 operates from a +4.5V to +5.5V supply, and the MAX1104 operates from a +2.7V to +5.5V supply. The MAX1102/MAX1103 incorporate a VDD monitor in addition to AIN for power supply moni- toring. All devices feature a low 18µA standby mode, where both data converters are disabled while the ref- erence remains active, and three shutdown modes: ADC disabled, DAC disabled, and complete shutdown (1µA). A quick 10µs wake-up time allows the MAX1102/MAX1103/MAX1104 to cycle in and out of shutdown even during short-duration idle times. The MAX1102/MAX1103/MAX1104 are available in a space-saving 8-pin µMAX® package. ________________________Applications Analog I/O for Microcontrollers Analog System Signal Supervision Voice Recording and Playback Features  8-Bit ADC ±1LSB INL Built-In Track-and-Hold 48dB of SINAD  8-Bit DAC ±1LSB INL 55dB of SFDR  Internal Conversion Clock  Single-Supply Operation +2.7V to +3.6V (MAX1102) +4.5V to +5.5V (MAX1103) +2.7V to +5.5V (MAX1104)  Low Power Consumption 0.5mA at 25ksps 1µA Shutdown Mode  6MHz 4-Wire SPI™, QSPI™, and MICROWIRE™ Compatible Interface  Compact 8-Pin µMAX Package  Internal Voltage Reference +2V: MAX1102 +4V: MAX1103  Power-Supply Monitor (MAX1102/MAX1103)  Rail-to-rail DAC Output Buffer M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs ________________________________________________________________ Maxim Integrated Products 1 1 + 2 3 4 8 7 6 5 DIN DOUT SCLK CSOUT AIN GND VDD MAX1102 MAX1103 MAX1104 µMAX TOP VIEW Pin Configuration SCLK SERIAL INTERFACE AND CONTROL LOGIC ADC DAC LATCH T/H AIN VDD/2 AOUT VOLTAGE REFERENCE DIN DOUT MAX1102 MAX1103 MAX1104 GND VDD DAC CS Functional Diagram 19-1873; Rev 1; 1/11 Ordering Information PART TEMP RANGE PIN- PA CKA GE REFER ENC E MAX1102EUA+ - 40°C to + 85°C 8 µMAX +2V MAX1103EUA+ - 40°C to + 85°C 8 µMAX +4V MAX1104EUA+ - 40°C to + 85°C 8 µMAX VDD µMAX is a registered trademark of Maxim Integrated Products, Inc. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes a lead(Pb)-free/RoHS-compliant package.

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M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10kΩ, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD to GND..............................................................-0.3V to +6V AIN, OUT, DOUT to GND ...........................-0.3V to (VDD + 0.3V) DIN, SCLK, CS to GND ............................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 8-Pin µMAX (derate 4.1mW/°C above +70°C) .................330mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering,10s) ..................................+300°C Soldering Temperature (reflow) .......................................+260°C PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS ADC DC ACCURACY (Note 1) Resolution 8 Bits Relative Accuracy (Note 2) INL All codes ±1/4 ±1 LSB Differential Nonlinearity DNL Guaranteed monotonic ±1/4 ±1 LSB Offset Error ±1 LSB MAX1102/MAX1103 ±5 %Gain Error (Note 3) MAX1104 ±1 LSB ADC DYNAMIC SPECIFICATIONS (fAIN = 10kHz SINE WAVE. VAIN = 0.9 ✕ VREFp-p) Signal to Noise and Distortion Ratio SINAD 48 dB Spurious-Free Dynamic Range SFDR 59 dB Total Harmonic Distortion THD 58 dB Full-Power Bandwidth 2.5 MHz ADC Wake-Up Time from Standby Reference enabled (MAX1102/MAX1103) 3 µs MAX1102/MAX11103 200ADC Wake-Up Time from Full Shutdown MAX1104 3 µs ANALOG INPUT Analog Input Voltage VAIN 0 VREF V Input Resistance RIN 10 MΩ Input Capacitance CIN 20 pF VOLTAGE REFERENCE MAX1102 2 Reference Voltage VREF MAX1103 4 V Temperature Coefficient MAX1102/MAX1103 100 ppm/ oC CONVERSION RATE Conversion Time tCONV 24 36 µs Track/Hold Acquisition Time tACQ 3.5 µs Internal Clock Frequency 375 kHz

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M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs _______________________________________________________________________________________ 3 PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS Throughput Rate ADC in continuous conversion mode 25 ksps DAC DC ACCURACY Resolution 8 Bits Relative Accuracy (Note 2) INL ±1/4 ±1 LSB Differential Nonlinearity DNL Guaranteed monotonic ±1/4 ±1 LSB Offset Error ±30 mV MAX1102/MAX1103 ±5 %Gain Error (Note 3) MAX1104 ±30 mV DAC DYNAMIC SPECIFICATIONS (fOUT = 1kHz SINE WAVE, VOUT = 0.9 ✕ VREFp-p) Spurious-Free Dynamic Range SFDR 55 dB Total Harmonic Distortion THD 53 dB Small-Signal Bandwidth 1 MHz Full-Power Bandwidth 72 kHz DAC Wake-Up Time from Standby (Note 4) Reference enabled (MAX1102/MAX1103) 10 µs MAX1102/MAX1103 200DAC Wake-Up Time from Full Shutdown (Note 4) MAX1104 10 µs DAC OUTPUT Full-Scale Swing MAX1104 0 VDD - 0.1 V Settling Time (Note 5) Settle to within ±1/2 LSB 11 µs Slew Rate 1.2 Vµs Load Regulation RL open to 10kΩ 0 < VOUT < VDD - 0.1V 0.05 LSB LOGIC INPUTS AND OUTPUTS (DIN, SLCK, CS) Input High Voltage VIH VDD x 0.7 V Input Low Voltage VIL VDD x 0.3 V Input Current VLOGIC = VGND or VDD ±0.1 ±5 µA Digital Input Hysteresis 0.5 V Digital Input Capacitance 15 pF Output High Voltage VOH ISOURCE = 1.0mA VDD x 0.9 V Output Low Voltage VOL ISINK = 1.0mA VDD x 0.1 V Three-State Leakage ILEAK ±5.0 µA ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10kΩ, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25°C unless otherwise noted.)

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M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs 4 _______________________________________________________________________________________ Note 1: MAX1102/MAX1104 tested with VDD = +3V. MAX1103 tested with VDD = +5V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. Note 3: Gain error calculation is referenced to the ideal FS output. Gain error for the MAX1102/MAX1103 also includes reference ini- tial accuracy error. Note 4: Wake-up time is the time it takes for the DAC output to settle to within ±1/2 LSB of the FS value after a power-up command. Note 5: Output settling time is measured by taking the DAC from code 00hex to FFhex. PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS POWER SUPPLY REQUIREMENTS MAX1102 2.7 3.6 MAX1103 4.5 5.5Supply Voltage VDD MAX1104 2.7 5.5 V ADC on (25ksps), DAC off 0.25 0.5 Supply Current ICC ADC off, DAC on (VDD = +5.5V) 0.4 0.66 mA Standby Current ADC off, DAC off, clock off, reference on 18 35 µA Full Shutdown Current ADC off, DAC off, clock off 1 µA ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10kΩ, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25°C unless otherwise noted.) PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS Power Up to Reset Complete t9 40 µs CS Rise-to-DOUT = High-Z t10 40 ns CS Fall-to-DOUT Valid t11 RDOUT = 3kΩ, CDOUT = 50pF 60 ns CS Fall-to-SCLK Rise t3 15 ns SCLK Fall-to-CS Rise t8 25 ns DIN-to-SCLK Setup Time t4 10 ns DIN-to-SCLK Hold Time t5 15 ns SCLK Fall to DOUT Valid t6 RDOUT = 3kΩ, CDOUT = 50pF 78 ns SCLK Maximum Frequency fSCLK 6 MHz SCLK Pulse Width High tCH 60 ns SCLK Pulse Width Low tCL 70 ns TIMING CHARACTERISTICS (Figures 4a and 4b) (VDD = +2.7V to +3.6V (MAX1102), VDD = +4.5V to +5.5V (MAX1103), VDD = +2.7V to +5.5V (MAX1104), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10kΩ, COUT = 100pF, TA = TMIN to TMAX. Typical values are at TA = +25°C unless otherwise noted.)

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M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs 0 100 50 200 150 250 300 2.5 3.5 4.03.0 4.5 5.0 5.5 SUPPLY CURRENT vs. SUPPLY VOLTAGE (ADC ENABLED, DAC DISABLED) M A X 1 1 0 2 t o c0 1 SUPPLY VOLTAGE (V) S U P P LY C U R R EN T (µ A ) CODE = AAhex 0 150 50 250 200 300 350 2.5 3.5 4.03.0 4.5 5.0 5.5 SUPPLY CURRENT vs. SUPPLY VOLTAGE (DAC ENABLED, ADC DISABLED) M A X 1 1 0 2 t o c0 2 SUPPLY VOLTAGE (V) S U P P LY C U R R EN T (µ A ) CODE = FFhex 100 CODE = 00hex 0 400 350 450 500 2.5 3.5 4.03.0 4.5 5.0 5.5 SUPPLY CURRENT vs. SUPPLY VOLTAGE (ADC ENABLED, DAC ENABLED) M A X 1 1 0 2 t o c0 3 SUPPLY VOLTAGE (V) S U P P LY C U R R EN T (µ A ) DAC CODE = FFhex 200 150 250 300 50 100 DAC CODE = 00hex ADC CODE = AAhex 20 15 10 5 0 2.5 4.03.0 3.5 4.5 5.0 5.5 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE M A X 1 1 0 2 t o c0 4 SUPPLY VOLTAGE (V) S U P P LY C U R R EN T (µ A ) ADC and DAC OFF REFERENCE ON ADC, DAC, and REFERENCE OFF 0 1.5 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.53.0 4.0 4.5 5.0 5.5 ADC OFFSET ERROR vs. SUPPLY VOLTAGE M A X 1 1 0 2 t o c0 5 SUPPLY VOLTAGE (V) O FF S ET E R R O R ( m V ) 5 6 8 7 9 10 2.5 3.53.0 4.0 4.5 5.0 5.5 DAC OFFSET ERROR vs. SUPPLY VOLTAGE M A X 1 1 0 2 t o c0 6 SUPPLY VOLTAGE (V) O FF S ET E R R O R ( m V ) CODE = 0Ahex 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.5 3.53.0 4.0 4.5 5.0 5.5 ADC GAIN ERROR vs. SUPPLY VOLTAGE M A X 1 1 0 2 t o c0 7 SUPPLY VOLTAGE (V) G A IN E R R O R ( % FS ) VREF = 2.0V CODE = FFhex 0 3 2 1 4 5 6 7 8 9 10 -40 10-15 35 60 85 ADC GAIN ERROR vs. TEMPERATURE M A X 1 1 0 2 to c0 8 TEMPERATURE (°C) G A IN E R R O R ( m V ) VREF = 2.0V CODE = 7Fhex 0 3 2 1 4 5 6 7 8 9 10 2.5 3.53.0 4.0 4.5 5.0 DAC GAIN ERROR vs. SUPPLY VOLTAGE M A X 1 1 0 2 t o c0 9 SUPPLY VOLTAGE (V) G A IN E R R O R ( m V ) 5.5 VREF = 2.0V CODE = FFhex Typical Operating Characteristics (VDD = +3.0V (MAX1102), VDD = +5V (MAX1103), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10kΩ, COUT = 100pF, TA = +25°C, unless otherwise noted.) _______________________________________________________________________________________ 5

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M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs 6 _______________________________________________________________________________________ 20 15 10 5 0 -40 10-15 35 60 85 DAC GAIN ERROR vs. TEMPERATURE M A X 1 1 0 2 t o c1 0 TEMPERATURE (°C) G A IN E R R O R ( m V ) VDD = +5.0V VREF = +2.0V CODE = FFhex 0 200 400 600 800 1000 1200 1400 1600 0 2 4 6 8 10 DAC OUTPUT LOW VOLTAGE vs. OUTPUT SINK CURRENT M A X 1 1 0 2 t o c1 1 OUTPUT SINK CURRENT (mA) O U TP U T V O LT A G E (m V ) CODE = 0Ahex VDD = +5.0V CODE = 00hex 3.55 3.60 3.65 3.70 3.75 3.80 3.85 3.90 3.95 0 2 4 6 8 10 DAC OUTPUT HIGH VOLTAGE vs. OUTPUT SOURCE CURRENT M A X 1 1 0 2 t o c1 2 OUTPUT SOURCE CURRENT (mA) O U TP U T V O LT A G E (V ) CODE = F0hex CODE = FFhex VDD = +5.0V VREF = +4.0V -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 50 100 150 200 250 ADC INTEGRAL NONLINEARITY vs. CODE M A X 1 1 0 2 t o c1 3 ADC OUTPUT CODE IN TE R G R A L N O N LI N EA R IT Y ( LS B ) 300 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 50 100 150 200 250 ADC DIFFERENTIAL NONLINEARITY vs. CODE M A X 1 1 0 2 t o c1 4 ADC OUTPUT CODE D IF FE R EN TI A L N O N LI N EA R IT Y ( LS B ) 300 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 50 100 150 200 250 DAC INTEGRAL NONLINEARITY vs. CODE M A X 1 1 0 2 t o c1 5 DAC OUTPUT CODE IN TE R G R A L N O N LI N EA R IT Y ( LS B ) 300 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 0 50 100 150 200 250 DAC DIFFERENTIAL NONLINEARITY vs. CODE M A X 1 1 0 2 t o c1 6 DAC OUTPUT CODE D IF FE R EN TI A L N O N LI N EA R IT Y ( LS B ) 300 SCLK WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE) MAX1102 toc17 1µs/div OUT 3V 0 20mV/div SCLK WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE) MAX1102 toc18 1µs/div OUT 3V 0 20mV/div Typical Operating Characteristics (continued) (VDD = +3.0V (MAX1102), VDD = +5V (MAX1103), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10kΩ, COUT = 100pF, TA = +25°C, unless otherwise noted.)

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_______________________________________________________________________________________ 7 M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs SCLK POSITIVE SETTLING TIME MAX1102 toc19 1µs/div OUT 3V 0 1V/div SCLK NEGATIVE SETTLING TIME MAX1102 toc20 1µs/div OUT 3V 0 1V/div SCLK CLOCK FEEDTHROUGH MAX1102 toc21 1µs/div OUT 3V 0 2mV/div -140 -100 -120 -60 -80 -20 -40 0 0 4 62 8 10 12 14 ADC FFT M A X 1 1 0 2 t o c2 2 FREQUENCY (kHz) M A G N IT U D E (d B ) VDD = +4.5V FSAMPLE = 24.576kHz FL = 10.002kHz -120 -80 -100 -60 0 20 -20 -40 40 0 2 3 4 51 6 7 8 9 10 DAC FFT M A X 1 1 0 2 t o c2 3 FREQUENCY (kHz) M A G N IT U D E (d B ) VDD = +4.5V Typical Operating Characteristics (continued) (VDD = +3.0V (MAX1102), VDD = +5V (MAX1103), fSCLK = 6.0MHz (50% duty cycle), ROUT = 10kΩ, COUT = 100pF, TA = +25°C, unless otherwise noted.)

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M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 Detailed Description The MAX1102/MAX1103/MAX1104 are 8-bit CODECs in a compact 8-pin package. These devices consist of an 8-bit ADC, an 8-bit DAC, track/hold (T/H), DAC output buffer amplifier, internal voltage reference, input multi- plexer (mux) and a 6MHz SPI, QSPI and MICROWIRE compatible 4-wire serial interface. A single 8-bit word configures the MAX1102/MAX1103/MAX1104, provid- ing a simple interface to a microcontroller (µC). Analog-to-Digital Converter The MAX1102/MAX1103/MAX1104 ADC section uses a successive-approximation (SAR) conversion technique and input T/H circuitry to convert an analog signal to an 8-bit digital output. No external hold capacitors are required. The MAX1102/MAX1103 have an input multi- plexer that directs either AIN or VDD/2 to the input of the T/H, allowing these devices to either convert the analog input, or monitor the power supply. Figure 1 shows the detailed functional diagram of the ADC block. ADC Operation The input architecture of the ADC is illustrated in Figure 2, the equivalent input circuit, and is composed of the T/H, input mux (MAX1102/MAX1103), input comparator, switched capacitor DAC, and the auto-zero rail. The switched capacitor DAC is independent of the R-2R ladder DAC and does not provide the converted analog output on OUT. The T/H is in hold mode while a conversion is taking place. Once the conversion is completed, the T/H enters acquisition mode, and tracks the input signal until the start of the next conversion. In single conver- sion mode, conversion starts at the falling clock edge corresponding to the last bit of the control word. In con- tinuous conversion mode, the first conversion following the control word starts on the falling clock edge of the 8-Bit CODECs 8 _______________________________________________________________________________________ Pin Description PIN NAME FUNCTION 1 VDD Voltage Supply 2 GND Ground 3 AIN ADC Analog Input 4 OUT DAC Analog Voltage Output 5 CS Chip Select Input. Device ignores all logic signals when CS is high. 6 SCLK Serial Clock Input. Data in is latched on the rising edge, data out transitions on the falling edge. 7 DOUT ADC Digital Output. Output is high impedance when CS is high. 8 DIN DAC Digital Input. Input ignores all signals when CS is high. DIN ANALOG INPUT MUX ANALOG INPUT MUX CONTROL LOGIC/2 AIN VDD/2 T/H SCLK CS MAX1102 MAX1103 SUCCESSIVE APPROXIMATION REGISTER INTERNAL OSCILLATOR INTERNAL OSCILLATOR DOUT CHARGE REDISTRIBUTION DAC OUTPUT SHIF REGISTER Figure 1. ADC Detailed Functional Diagram

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LSB of the control word. Successive conversions are initiated after the last bit of the previous conversion result has been clocked out. Resultant data is only available after conversion is complete. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. This time, tACQ2, is cal- culated by the following equation: tACQ2 = (6.2  RS  15pF) + tACQ where RS = the source impedance of the input signal; tACQ is the T/H acquisition time from the Electrical Characteristics table. Conversion Progress The comparator’s negative input is connected to the auto-zero rail. Since the device requires only a single supply, the ZERO node at the input of the comparator equals VDD/2. The capacitive DAC restores node ZERO to have no voltage difference at the comparator inputs within the limits of an 8-bit resolution. Input Voltage Range Internal protection diodes that clamp the analog input to VDD and GND allow AIN to swing from (VGND - 0.3V) to (VDD + 0.3V) without damaging the device. However, for accurate conversions, the input must not exceed (VDD + 0.05V) or be less than (VGND - 0.05V). The valid input range for the analog input is from GND to VREF. The output code is invalid (code zero) when a negative input voltage is applied, and full scale (FS) when the input voltage exceeds the reference. Input Bandwidth The ADC’s input tracking circuitry has a 2.5MHz full- power bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-fre- quency signals being aliased into the frequency band of interest, low-pass filters such as the MAX7418– MAX7426 are recommended. Digital-to-Analog Converter The MAX1102/MAX1103/MAX1104 DAC section uses an R-2R ladder network that converts the 8-bit digital input into an equivalent analog output voltage propor- tional to the applied reference voltage (Figure 3). The DAC features a double-buffered input, and a buffered analog output. M A X 1 1 0 2 /M A X 1 1 0 3 /M A X 1 1 0 4 8-Bit CODECs _______________________________________________________________________________________ 9 AIN HOLD HOLD TRACK 5pF TRACK ZERO CAPACITIVE DAC VDD/2 VREF GND 15pF MAX1102 MAX1103 MAX1104 2R R R R R 2R 2R 2R 2R REF GND NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FFhex. DAC_ REGISTER OUT MSBLSB 2R R R R 2R 2R 2R Figure 2. Equivalent Input Circuit Figure 3. DAC Simplified Circuit Diagram

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