MPC8306SVMADDCA

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Freescale Semiconductor Technical Data © 2011 Freescale Semiconductor, Inc. All rights reserved. This document provides an overview of the MPC8306S PowerQUICC II Pro processor features. The MPC8306S is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including residential gateways, modem/routers, industrial control, and test and measurement applications. The MPC8306S extends current PowerQUICC offerings, adding higher CPU performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate. This document describes the electrical characteristics of MPC8306S. To locate published errata or updates for this document, refer to the MPC8306S product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. Document Number: MPC8306SEC Rev. 1, 09/2011 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 21 9. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10. HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 44 20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22. System Design Information . . . . . . . . . . . . . . . . . . . 64 23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 67 24. Document Revision History . . . . . . . . . . . . . . . . . . . 69 MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 2 Freescale Semiconductor Overview 1 Overview The MPC8306S incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8306S also includes two DMA engines and a 16-bit DDR2 memory controller. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8306S. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure. Figure 1. MPC8306S Block Diagram Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII Ethernet, HDLC and TDM. 3 RMII/MII2x TDM Ports 16-KB D-Cache 16-KB I-Cache e300c3 Core with Power2 x DUART Interrupt I2C Timers GPIO DDR2 Controller Controller Baud Rate Generators Accelerators Single 32-bit RISC CP Serial DMA Serial Interface QUICC Engine™ Block U C C 7 U C C 5 U C C 3 U C C 2 U C C 1 Time Slot Assigner 16 KB Multi-User RAM FPU Management SPI RTC 2x HDLC DMA 48 KB Instruction RAM Engine USB 2.0 HS Host/Device/OTG ULPI Enhanced Local Bus Controller

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 3 Overview In summary, the MPC8306S provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. 1.1 Features The major features of the device are as follows: • e300c3 Power Architecture processor core — Enhanced version of the MPC603e core — High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times — Floating-point, dual integer units, load/store, system register, and branch processing units — 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities — Dynamic power management — Enhanced hardware program debug features — Software-compatible with Freescale processor families implementing Power Architecture technology — Separate PLL that is clocked by the system bus clock — Performance monitor • QUICC Engine block — 32-bit RISC controller for flexible support of the communications peripherals with the following features: – One clock per instruction – Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization – 32-bit instruction object code – Executes code from internal IRAM – 32-bit arithmetic logic unit (ALU) data path – Modular architecture allowing for easy functional enhancements – Slave bus for CPU access of registers and multiuser RAM space – 48 Kbytes of instruction RAM – 16 Kbytes of multiuser data RAM – Serial DMA channel for receive and transmit on all serial channels — Five unified communication controllers (UCCs) supporting the following protocols and interfaces: – 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces. – HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8) – HDLC Bus (bit rate up to 10 Mbps) – Asynchronous HDLC (bit rate up to 2 Mbps)

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 4 Freescale Semiconductor Overview – Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference Manual with Protocol Interworking. • DDR SDRAM memory controller — Programmable timing supporting DDR2 SDRAM — Integrated SDRAM clock generation — 16-bit data interface, up to 266-MHz data rate — 14 address lines — The following SDRAM configurations are supported: – Up to two physical banks (chip selects), 256-Mbyte per chip select for 16 bit data interface. – 64-Mbit to 2-Gbit devices with x8/x16 data ports (no direct x4 support) – One 16-bit device or two 8-bit devices on a 16-bit bus, — Support for up to 16 simultaneous open pages for DDR2 — One clock pair to support up to 4 DRAM devices — Supports auto refresh — On-the-fly power management using CKE • Enhanced local bus controller (eLBC) — Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz — Eight chip selects supporting eight external slaves – Four chip selects dedicated – Four chip selects offered as multiplexed option — Supports boot from parallel NOR Flash and parallel NAND Flash — Supports programmable clock ratio dividers — Up to eight-beat burst transfers — 16- and 8-bit ports, separate LWE for each 8 bit — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – NAND Flash control machine (FCM) — Variable memory block sizes for FCM, GPCM, and UPM mode — Default boot ROM chip select with configurable bus width (8 or 16) — Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC slave devices • Integrated programmable interrupt controller (IPIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for external and internal discrete interrupt sources — Programmable highest priority request

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 5 Overview — Six groups of interrupts with programmable priority — External and internal interrupts directed to host processor — Unique vector number for each interrupt source • Universal serial bus (USB) dual-role controller — Designed to comply with Universal Serial Bus Revision 2.0 Specification — Supports operation as a stand-alone USB host controller — Supports operation as a stand-alone USB device — Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations. Low speed is only supported in host mode. • Dual I2C interfaces — Two-wire interface — Multiple-master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus — I2C1 can be used as the boot sequencer • DMA Engine — Support for the DMA engine with the following features: – Sixteen DMA channels – All data movement via dual-address transfers: read from source, write to destination – Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations – Channel activation via one of two methods (for both the methods, one activation per execution of the minor loop is required): – Explicit software initiation – Initiation via a channel-to-channel linking mechanism for continuous transfers (independent channel linking at end of minor loop and/or major loop) – Support for fixed-priority and round-robin channel arbitration – Channel completion reported via optional interrupt requests — Support for scatter/gather DMA processing • DUART — Two 2-wire interfaces (RxD, TxD) – The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D • Serial peripheral interface (SPI) — Master or slave support • Power managemnt controller (PMC) — Supports core doze/nap/sleep/ power management — Exits low power state and returns to full-on mode when – The core internal time base unit invokes a request to exit low power state

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 6 Freescale Semiconductor Electrical Characteristics – The power management controller detects that the system is not idle and there are outstanding transactions on the internal bus or an external interrupt. • Parallel I/O — General-purpose I/O (GPIO) – 56 parallel I/O pins multiplexed on various chip interfaces – Interrupt capability • System timers — Periodic interrupt timer — Software watchdog timer — Eight general-purpose timers • Real time clock (RTC) module — Maintains a one-second count, unique over a period of thousands of years — Two possible clock sources: – External RTC clock (RTC_PIT_CLK) – CSB bus clock • IEEE Std. 1149.1™ compliant JTAG boundary scan 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8306S. The MPC8306S is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings The following table provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 Characteristic Symbol Max Value Unit Notes Core supply voltage VDD –0.3 to 1.26 V — PLL supply voltage AVDD1 AVDD2 AVDD3 –0.3 to 1.26 V — DDR2 DRAM I/O voltage GVDD –0.3 to 1.98 V — Local bus, DUART, system control and power management, I2C, SPI, MII, RMII, MII management, USB and JTAG I/O voltage OVDD –0.3 to 3.6 V 2

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 7 Electrical Characteristics Input voltage DDR2 DRAM signals MVIN –0.3 to (GVDD + 0.3) V 3 DDR2 DRAM reference MVREF –0.3 to (GVDD + 0.3) V 3 Local bus, DUART, SYS_CLK_IN, system control and power management, I2C, SPI, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 4 Storage temperature range TSTG –55 to 150 C — Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. 3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. Table 1. Absolute Maximum Ratings1 (continued) Characteristic Symbol Max Value Unit Notes

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 8 Freescale Semiconductor Electrical Characteristics 2.1.2 Power Supply Voltage Specification The following table provides the recommended operating conditions for the MPC8306S. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8306S Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD Table 2. Recommended Operating Conditions Characteristic Symbol Recommended Value Unit Note Core supply voltage VDD 1.0 V ± 50 mV V 1 PLL supply voltage AVDD1 AVDD2 AVDD3 1.0 V ± 50 mV V 1 DDR2 DRAM I/O voltage GVDD 1.8 V ± 100 mV V 1 Local bus, DUART, system control and power management, I2C, SPI, MII, RMII, MII management, USB and JTAG I/O voltage OVDD 3.3 V ± 300 mV V 1, 3 Junction temperature TA/TJ 0 to 105 C 2 Notes: 1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction. 2. Minimum temperature is specified with TA(Ambient Temperature); maximum temperature is specified with TJ(Junction Temperature). 3. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. GND GND – 0.3 V GND – 0.7 V Not to Exceed 10% G/OVDD + 20% G/OVDD G/OVDD + 5% of tinterface 1 1. tinterface refers to the clock period associated with the bus clock interface. VIH VIL Note:

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MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 Freescale Semiconductor 9 Electrical Characteristics 2.1.3 Output Driver Characteristics The following table provides information on the characteristics of the output driver strengths. 2.1.4 Input Capacitance Specification The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8306S. 2.2 Power Sequencing The device does not require the core supply voltage (VDD) and I/O supply voltages (GVDD and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input and output pins are actively driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating PORESET. NOTE There is no specific power down sequence requirement for the device. I/O voltage supplies (GVDD and OVDD) do not have any ordering requirements with respect to one another. Table 3. Output Drive Capability Driver Type Output Impedance () Supply Voltage (V) Local bus interface utilities signals 42 OVDD = 3.3 DDR2 signal 18 GVDD = 1.8 DUART, system control, I2C, SPI, JTAG 42 OVDD = 3.3 GPIO signals 42 OVDD = 3.3 Table 4. Input Capacitance Specification Parameter/Condition Symbol Min Max Unit Note Input capacitance for all pins except SYS_CLK_IN and QE_CLK_IN CI 6 8 pF — Input capacitance for SYS_CLK_IN and QE_CLK_IN CICLK_IN 10 — pF 1 Note: 1. The external clock generator should be able to drive 10 pF.