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MT47H256M8EB-3:C

hotMT47H256M8EB-3:C

MT47H256M8EB-3:C

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Part Number MT47H256M8EB-3:C
Manufacturer Micron Technology Inc.
Description IC SDRAM 2GBIT 333MHZ 60FBGA
Datasheet MT47H256M8EB-3:C Datasheet
Package 60-TFBGA
In Stock 1,083 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 4 - Dec 9 (Choose Expedited Shipping)
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Part Number # MT47H256M8EB-3:C (Memory) is manufactured by Micron Technology Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MT47H256M8EB-3:C Specifications

ManufacturerMicron Technology Inc.
CategoryIntegrated Circuits (ICs) - Memory
Datasheet MT47H256M8EB-3:CDatasheet
Package60-TFBGA
Series-
Memory TypeVolatile
Memory FormatDRAM
TechnologySDRAM - DDR2
Memory Size2Gb (256M x 8)
Memory InterfaceParallel
Clock Frequency333MHz
Write Cycle Time - Word, Page15ns
Access Time450ps
Voltage - Supply1.7 V ~ 1.9 V
Operating Temperature0°C ~ 85°C (TC)
Mounting TypeSurface Mount
Package / Case60-TFBGA
Supplier Device Package60-FBGA (9x11.5)

MT47H256M8EB-3:C Datasheet

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DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks Features • VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V • JEDEC-standard 1.8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • 4n-bit prefetch architecture • Duplicate output strobe (RDQS) option for x8 • DLL to align DQ and DQS transitions with CK • 8 internal banks for concurrent operation • Programmable CAS latency (CL) • Posted CAS additive latency (AL) • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength • 64ms, 8192-cycle refresh • On-die termination (ODT) • Industrial temperature (IT) option • RoHS-compliant • Supports JEDEC clock jitter specification Options1 Marking • Configuration – 512 Meg x 4 (64 Meg x 4 x 8 banks) 512M4 – 256 Meg x 8 (32 Meg x 8 x 8 banks) 256M8 – 128 Meg x 16 (16 Meg x 16 x 8 banks) 128M16 • FBGA package (Pb-free) – x16 – 84-ball FBGA (11.5mm x 14mm) Rev. A HG • FBGA package (Pb-free) – x4, x8 – 60-ball FBGA (11.5mm x 14mm) Rev. A HG • FBGA package (Pb-free) – x16 – 84-ball FBGA (9mm x 12.5mm) Rev. C RT • FBGA package (Pb-free) – x4, x8 – 60-ball FBGA (9mm x 11.5mm) Rev. C EB • FBGA package (Lead solder) – x16 – 84-ball FBGA (9mm x 12.5mm) Rev. C PK • Timing – cycle time – 1.875ns @ CL = 7 (DDR2-1066) -187E – 2.5ns @ CL = 5 (DDR2-800) -25E – 2.5ns @ CL = 6 (DDR2-800) -25 – 3.0ns @ CL = 5 (DDR2-667) -3 • Self refresh – Standard None • Operating temperature – Commercial (0°C TC +85°C) None – Industrial (–40°C TC +95°C; –40°C TA +85°C) IT • Revision :A/:C Note: 1. Not all options listed can be combined to define an offered product. Use the Part Catalog Search on www.micron.com for product offerings and availability. 2Gb: x4, x8, x16 DDR2 SDRAM Features CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

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Table 1: Key Timing Parameters Speed Grade Data Rate (MHz) tRC (ns)CL = 3 CL = 4 CL = 5 CL = 6 CL = 7 -187E 400 533 800 800 1066 54 -25E 400 533 800 800 n/a 55 -25 400 533 667 800 n/a 55 -3 400 533 667 n/a n/a 55 Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address A[14:0] (32K) A[14:0] (32K) A[13:0] (16K) Bank address BA[2:0] (8) BA[2:0] (8) BA[2:0] (8) Column address A[11, 9:0] (2K) A[9:0] (1K) A[9:0] (1K) Part Numbers Figure 1: 2Gb DDR2 Part Numbers Example Part Number: MT47H256M8EB-25 :C Configuration 512 Meg x 4 256 Meg x 8 128 Meg x 16 512M4 256M8 128M16 Speed Grade tCK = 1.875ns, CL = 7 tCK = 2.5ns, CL = 5 tCK = 2.5ns, CL = 6 tCK = 3ns, CL = 5 -187E -25E -25 -3 - ConfigurationMT47H Package Speed Revision Revision:A/:C : Industrial TemperatureIT 84-Ball 11.5mm x 14mm FBGA 60-Ball 11.5mm x 14mm FBGA 84-Ball 9.0mm x 12.5mm FBGA 60-Ball 9.0mm x 11.5mm FBGA 84-Ball 9.0mm x 12.5mm FBGA (lead solder) Package EB RT PK HG HG Standard Blank Power Note: 1. Not all speeds and configurations are available. FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. 2Gb: x4, x8, x16 DDR2 SDRAM Features CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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Contents Important Notes and Warnings ......................................................................................................................... 8 State Diagram .................................................................................................................................................. 9 Functional Description ................................................................................................................................... 10 Industrial Temperature ............................................................................................................................... 10 General Notes ............................................................................................................................................ 11 Functional Block Diagrams ............................................................................................................................. 12 Ball Assignments and Descriptions ................................................................................................................. 15 Packaging ...................................................................................................................................................... 19 Package Dimensions ................................................................................................................................... 19 FBGA Package Capacitance ......................................................................................................................... 23 Electrical Specifications – Absolute Ratings ..................................................................................................... 24 Temperature and Thermal Impedance ........................................................................................................ 24 Electrical Specifications – IDD Parameters ........................................................................................................ 27 IDD Specifications and Conditions ............................................................................................................... 27 IDD7 Conditions .......................................................................................................................................... 27 AC Timing Operating Specifications ................................................................................................................ 33 AC and DC Operating Conditions .................................................................................................................... 45 ODT DC Electrical Characteristics ................................................................................................................... 46 Input Electrical Characteristics and Operating Conditions ............................................................................... 47 Output Electrical Characteristics and Operating Conditions ............................................................................. 50 Output Driver Characteristics ......................................................................................................................... 52 Power and Ground Clamp Characteristics ....................................................................................................... 56 AC Overshoot/Undershoot Specification ......................................................................................................... 57 Input Slew Rate Derating ................................................................................................................................ 59 Commands .................................................................................................................................................... 72 Truth Tables ............................................................................................................................................... 72 DESELECT ................................................................................................................................................. 76 NO OPERATION (NOP) ............................................................................................................................... 77 LOAD MODE (LM) ...................................................................................................................................... 77 ACTIVATE .................................................................................................................................................. 77 READ ......................................................................................................................................................... 77 WRITE ....................................................................................................................................................... 77 PRECHARGE .............................................................................................................................................. 78 REFRESH ................................................................................................................................................... 78 SELF REFRESH ........................................................................................................................................... 78 Mode Register (MR) ........................................................................................................................................ 78 Burst Length .............................................................................................................................................. 79 Burst Type .................................................................................................................................................. 80 Operating Mode ......................................................................................................................................... 80 DLL RESET ................................................................................................................................................. 80 Write Recovery ........................................................................................................................................... 81 Power-Down Mode ..................................................................................................................................... 81 CAS Latency (CL) ........................................................................................................................................ 82 Extended Mode Register (EMR) ....................................................................................................................... 83 DLL Enable/Disable ................................................................................................................................... 84 Output Drive Strength ................................................................................................................................ 84 DQS# Enable/Disable ................................................................................................................................. 84 RDQS Enable/Disable ................................................................................................................................. 84 Output Enable/Disable ............................................................................................................................... 84 On-Die Termination (ODT) ......................................................................................................................... 85 2Gb: x4, x8, x16 DDR2 SDRAM Features CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 85 Posted CAS Additive Latency (AL) ................................................................................................................ 85 Extended Mode Register 2 (EMR2) ................................................................................................................... 87 Extended Mode Register 3 (EMR3) ................................................................................................................... 88 Initialization .................................................................................................................................................. 89 ACTIVATE ...................................................................................................................................................... 92 READ ............................................................................................................................................................. 94 READ with Precharge .................................................................................................................................. 98 READ with Auto Precharge ......................................................................................................................... 100 WRITE .......................................................................................................................................................... 105 PRECHARGE ................................................................................................................................................. 115 REFRESH ...................................................................................................................................................... 116 SELF REFRESH .............................................................................................................................................. 117 Power-Down Mode ........................................................................................................................................ 119 Precharge Power-Down Clock Frequency Change ........................................................................................... 126 Reset ............................................................................................................................................................. 127 CKE Low Anytime ...................................................................................................................................... 127 ODT Timing .................................................................................................................................................. 129 MRS Command to ODT Update Delay ........................................................................................................ 131 2Gb: x4, x8, x16 DDR2 SDRAM Features CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 2 Table 2: Addressing ......................................................................................................................................... 2 Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 17 Table 4: Input Capacitance ............................................................................................................................ 23 Table 5: Absolute Maximum DC Ratings ......................................................................................................... 24 Table 6: Temperature Limits .......................................................................................................................... 25 Table 7: Thermal Impedance ......................................................................................................................... 26 Table 8: General IDD Parameters ..................................................................................................................... 27 Table 9: IDD7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 28 Table 10: DDR2 IDD Specifications and Conditions (Die Revision A) ................................................................. 29 Table 11: DDR2 IDD Specifications and Conditions (Die Revision C) ................................................................ 31 Table 12: AC Operating Specifications and Conditions .................................................................................... 33 Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 45 Table 14: ODT DC Electrical Characteristics ................................................................................................... 46 Table 15: Input DC Logic Levels ..................................................................................................................... 47 Table 16: Input AC Logic Levels ...................................................................................................................... 47 Table 17: Differential Input Logic Levels ......................................................................................................... 48 Table 18: Differential AC Output Parameters ................................................................................................... 50 Table 19: Output DC Current Drive ................................................................................................................ 50 Table 20: Output Characteristics .................................................................................................................... 51 Table 21: Full Strength Pull-Down Current (mA) ............................................................................................. 52 Table 22: Full Strength Pull-Up Current (mA) .................................................................................................. 53 Table 23: Reduced Strength Pull-Down Current (mA) ...................................................................................... 54 Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 55 Table 25: Input Clamp Characteristics ............................................................................................................ 56 Table 26: Address and Control Balls ................................................................................................................ 57 Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 57 Table 28: AC Input Test Conditions ................................................................................................................ 57 Table 29: DDR2-400/533 Setup and Hold Time Derating Values ( tIS and tIH) .................................................... 60 Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values ( tIS and tIH) ........................................... 61 Table 31: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ...................................................... 64 Table 32: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................. 65 Table 33: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb ................................................... 66 Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 ...................................... 66 Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 ...................................... 67 Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 ...................................... 67 Table 37: Truth Table – DDR2 Commands ...................................................................................................... 72 Table 38: Truth Table – Current State Bank n – Command to Bank n ................................................................ 73 Table 39: Truth Table – Current State Bank n – Command to Bank m ............................................................... 75 Table 40: Minimum Delay with Auto Precharge Enabled ................................................................................. 76 Table 41: Burst Definition .............................................................................................................................. 80 Table 42: READ Using Concurrent Auto Precharge ......................................................................................... 100 Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 106 Table 44: Truth Table – CKE .......................................................................................................................... 121 2Gb: x4, x8, x16 DDR2 SDRAM Features CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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List of Figures Figure 1: 2Gb DDR2 Part Numbers ................................................................................................................... 2 Figure 2: Simplified State Diagram ................................................................................................................... 9 Figure 3: Functional Block Diagram – 512 Meg x 4 ........................................................................................... 12 Figure 4: Functional Block Diagram – 256 Meg x 8 ........................................................................................... 13 Figure 5: Functional Block Diagram – 128 Meg x 16 ......................................................................................... 14 Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15 Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 16 Figure 8: 84-Ball FBGA Package (11.5mm x 14mm) – x16 ................................................................................. 19 Figure 9: 84-Ball FBGA Package (9mm x 12.5mm) – x16 ................................................................................... 20 Figure 10: 60-Ball FBGA Package (11.5mm x 14mm) – x4, x8 ............................................................................ 21 Figure 11: 60-Ball FBGA Package (9mm x 11.5mm) – x4, x8 .............................................................................. 22 Figure 12: Example Temperature Test Point Location ...................................................................................... 25 Figure 13: Single-Ended Input Signal Levels ................................................................................................... 47 Figure 14: Differential Input Signal Levels ...................................................................................................... 48 Figure 15: Differential Output Signal Levels .................................................................................................... 50 Figure 16: Output Slew Rate Load .................................................................................................................. 51 Figure 17: Full Strength Pull-Down Characteristics ......................................................................................... 52 Figure 18: Full Strength Pull-Up Characteristics .............................................................................................. 53 Figure 19: Reduced Strength Pull-Down Characteristics .................................................................................. 54 Figure 20: Reduced Strength Pull-Up Characteristics ...................................................................................... 55 Figure 21: Input Clamp Characteristics .......................................................................................................... 56 Figure 22: Overshoot ..................................................................................................................................... 57 Figure 23: Undershoot ................................................................................................................................... 57 Figure 24: Nominal Slew Rate for tIS ............................................................................................................... 62 Figure 25: Tangent Line for tIS ........................................................................................................................ 62 Figure 26: Nominal Slew Rate for tIH .............................................................................................................. 63 Figure 27: Tangent Line for tIH ....................................................................................................................... 63 Figure 28: Nominal Slew Rate for tDS ............................................................................................................. 68 Figure 29: Tangent Line for tDS ...................................................................................................................... 68 Figure 30: Nominal Slew Rate for tDH ............................................................................................................. 69 Figure 31: Tangent Line for tDH ..................................................................................................................... 69 Figure 32: AC Input Test Signal Waveform Command/Address Balls ................................................................ 70 Figure 33: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 70 Figure 34: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 71 Figure 35: AC Input Test Signal Waveform (Differential) .................................................................................. 71 Figure 36: MR Definition ............................................................................................................................... 79 Figure 37: CL ................................................................................................................................................. 82 Figure 38: EMR Definition ............................................................................................................................. 83 Figure 39: READ Latency ............................................................................................................................... 86 Figure 40: WRITE Latency .............................................................................................................................. 86 Figure 41: EMR2 Definition ........................................................................................................................... 87 Figure 42: EMR3 Definition ........................................................................................................................... 88 Figure 43: DDR2 Power-Up and Initialization ................................................................................................. 89 Figure 44: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 92 Figure 45: Multibank Activate Restriction ....................................................................................................... 93 Figure 46: READ Latency ............................................................................................................................... 95 Figure 47: Consecutive READ Bursts .............................................................................................................. 96 Figure 48: Nonconsecutive READ Bursts ........................................................................................................ 97 Figure 49: READ Interrupted by READ ............................................................................................................ 98 Figure 50: READ-to-WRITE ............................................................................................................................ 98 2Gb: x4, x8, x16 DDR2 SDRAM Features CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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Figure 51: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 99 Figure 52: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 99 Figure 53: Bank Read – Without Auto Precharge ............................................................................................. 101 Figure 54: Bank Read – with Auto Precharge .................................................................................................. 102 Figure 55: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window .................................................. 103 Figure 56: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window ..................................................... 104 Figure 57: Data Output Timing – tAC and tDQSCK ......................................................................................... 105 Figure 58: Write Burst ................................................................................................................................... 107 Figure 59: Consecutive WRITE-to-WRITE ...................................................................................................... 108 Figure 60: Nonconsecutive WRITE-to-WRITE ................................................................................................ 108 Figure 61: WRITE Interrupted by WRITE ....................................................................................................... 109 Figure 62: WRITE-to-READ ........................................................................................................................... 110 Figure 63: WRITE-to-PRECHARGE ................................................................................................................ 111 Figure 64: Bank Write – Without Auto Precharge ............................................................................................ 112 Figure 65: Bank Write – with Auto Precharge .................................................................................................. 113 Figure 66: WRITE – DM Operation ................................................................................................................ 114 Figure 67: Data Input Timing ........................................................................................................................ 115 Figure 68: Refresh Mode ............................................................................................................................... 116 Figure 69: Self Refresh .................................................................................................................................. 118 Figure 70: Power-Down ................................................................................................................................ 120 Figure 71: READ-to-Power-Down or Self Refresh Entry .................................................................................. 122 Figure 72: READ with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................... 122 Figure 73: WRITE-to-Power-Down or Self Refresh Entry ................................................................................. 123 Figure 74: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 123 Figure 75: REFRESH Command-to-Power-Down Entry .................................................................................. 124 Figure 76: ACTIVATE Command-to-Power-Down Entry ................................................................................. 124 Figure 77: PRECHARGE Command-to-Power-Down Entry ............................................................................. 125 Figure 78: LOAD MODE Command-to-Power-Down Entry ............................................................................. 125 Figure 79: Input Clock Frequency Change During Precharge Power-Down Mode ............................................ 126 Figure 80: RESET Function ........................................................................................................................... 128 Figure 81: ODT Timing for Entering and Exiting Power-Down Mode ............................................................... 130 Figure 82: Timing for MRS Command to ODT Update Delay .......................................................................... 131 Figure 83: ODT Timing for Active or Fast-Exit Power-Down Mode .................................................................. 131 Figure 84: ODT Timing for Slow-Exit or Precharge Power-Down Modes .......................................................... 132 Figure 85: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 132 Figure 86: ODT Turn-On Timing When Entering Power-Down Mode .............................................................. 133 Figure 87: ODT Turn-Off Timing When Exiting Power-Down Mode ................................................................ 134 Figure 88: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................. 135 2Gb: x4, x8, x16 DDR2 SDRAM Features CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this docu- ment if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi- cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib- utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non- automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con- ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in- demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo- nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ- mental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi- cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL- URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en- vironmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. 2Gb: x4, x8, x16 DDR2 SDRAM Important Notes and Warnings CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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State Diagram Figure 2: Simplified State Diagram Automatic Sequence Command Sequence PRE Initialization sequence Self refreshing CKE_L Refreshing Precharge power- down Setting MRS EMRS SR CKE _H REFRESH Idle all banks precharged CK E_ L CKE_L CKE_L (E)MRS OCD default Activating ACT Bank active Reading READ Writing W RIT E Active power- down CKE _L CKE_L CKE_H CKE_L Writing with auto precharge Reading with auto precharge READ A WRITE A PRE, PRE_A W R IT E A W RIT E A R EA D A PR E , PR E_ A READ A READ WRITE Precharging CKE_H WRITE READ PR E, PR E_A ACT = ACTIVATE CKE_H = CKE HIGH, exit power-down or self refresh CKE_L = CKE LOW, enter power-down (E)MRS = (Extended) mode register set PRE = PRECHARGE PRE_A = PRECHARGE ALL READ = READ READ A = READ with auto precharge REFRESH = REFRESH SR = SELF REFRESH WRITE = WRITE WRITE A = WRITE with auto precharge Note: 1. This diagram provides the basic command flow. It is not comprehensive and does not identify all timing requirements or possible command restrictions such as multibank in- teraction, power down, entry/exit, etc. 2Gb: x4, x8, x16 DDR2 SDRAM State Diagram CCMTD-1725822587-6523 2Gb_DDR2.pdf – Rev. J 09/18 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

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TVS DIODE 6VWM 12.3VC UDFN

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