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R5F571MFDDFB#V0

R5F571MFDDFB#V0

R5F571MFDDFB#V0

For Reference Only

Part Number R5F571MFDDFB#V0
Manufacturer Renesas Electronics America
Description IC MCU 32BIT 2MB FLASH 144LFQFP
Datasheet R5F571MFDDFB#V0 Datasheet
Package 144-LQFP
In Stock 420 piece(s)
Unit Price $ 19.0500 *
Lead Time To be Confirmed
Estimated Delivery Time Jul 12 - Jul 17 (Choose Expedited Shipping)
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Part Number # R5F571MFDDFB#V0 (Embedded - Microcontrollers) is manufactured by Renesas Electronics America and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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R5F571MFDDFB#V0 Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet R5F571MFDDFB#V0Datasheet
Package144-LQFP
SeriesRX71M
Core ProcessorRXv2
Core Size32-Bit
Speed240MHz
ConnectivityCAN, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
PeripheralsDMA, LVD, POR, PWM, WDT
Number of I/O111
Program Memory Size2MB (2M x 8)
Program Memory TypeFLASH
EEPROM Size64K x 8
RAM Size512K x 8
Voltage - Supply (Vcc/Vdd)2.7 V ~ 3.6 V
Data ConvertersA/D 8x12b, 21x12b, D/A 2x12
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C (TA)
Mounting Type-
Package / Case144-LQFP
Supplier Device Package144-LFQFP (20x20)

R5F571MFDDFB#V0 Datasheet

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RX71M Group Renesas MCUs Datasheet R01DS0249EJ0110 Rev.1.10 Page 1 of 232 Dec 28, 2017 Features ■ 32-bit RXv2 CPU core • Max. operating frequency: 240 MHz Capable of 480 DMIPS in operation at 240 MHz • Single precision 32-bit IEEE-754 floating point • Two types of multiply-and-accumulation unit (between memories and between registers) • 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) • Divider (fastest instruction execution takes two CPU clock cycles) • Fast interrupt • CISC Harvard architecture with 5-stage pipeline • Variable-length instructions: Ultra-compact code • Supports the memory protection unit (MPU) • JTAG and FINE (one-line) debugging interfaces ■ Low-power design and architecture • Operation from a single 2.7- to 3.6-V supply • Low power consumption: A product that supports all peripheral functions draws only 0.2mA/MHz (Typ.). • RTC is capable of operation from a dedicated power supply. • Four low-power modes ■ On-chip code flash memory • Supports versions with up to 4 Mbytes of ROM • No wait states at up to 120 MHz or when the AFU is hit, one wait state at above 120 MHz and when the AFU is missed • User code is programmable by on-board or off-board programming. • Programming/erasing as background operations (BGOs) ■ On-chip data flash memory • 64 Kbytes, reprogrammable up to 100,000 times • Programming/erasing as background operations (BGOs) ■ On-chip SRAM • 512 Kbytes of SRAM (no wait states except in the 256 Kbytes from 0004 0000h to 0007 FFFFh when ICLK is set to 120 MHz or faster) • 32 Kbytes of RAM with ECC (single-error correction and double error detection) • 8 Kbytes of standby RAM (backup on deep software standby) ■ Data transfer • DMAC: 8 channels • DTC • EXDMAC: 2 channels • DMAC for the Ethernet controller: 3 channels for 176- and 177-pin products; 2 channels for 100-, 144-, and 145-pin products ■ Reset and supply management • Power-on reset (POR) • Low voltage detection (LVD) with voltage settings ■ Clock functions • External crystal resonator or internal PLL for operation at 8 to 24 MHz • Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz • 120-kHz clock for the IWDTa ■ Real-time clock • Adjustment functions (30 seconds, leap year, and error) • Real-time clock counting and binary counting modes are selectable • Time capture function (for capturing times in response to event-signal input) ■ Independent watchdog timer • 120-kHz (1/2 LOCO frequency) clock operation ■ Useful functions for IEC60730 compliance • Oscillation-stoppage detection, frequency measurement, CRC, IWDTa, self-diagnostic function for the A/D converter, etc. • Register write protection function can protect values in important registers against overwriting. ■ Various communications interfaces • IEEE 1588-compliant Ethernet MAC (for 176- and 177-pin products: 2 modules) • PHY layer for host/function or OTG controller (1) with high-speed USB 2.0 with battery charging transfer (only for 176- and 177-pin products) • PHY layer (1) for host/function or OTG controller (1) with full- speed USB 2.0 transfer • CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3 modules) • SCIg and SCIh with multiple functionalities (up to 9) Choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, simplified SPI, simplified I2C, and extended serial mode. • SCIFA with 16-byte transmission and reception FIFOs (up to 4 interfaces) • I2C bus interface for transfer at up to 1 Mbps (up to 2 interfaces) • Four-wire QSPI (1 interface) in addition to RSPIa (2 interfaces) • Parallel data capture unit (PDC) for the CMOS camera interface (not in 100-pin products) • SD host interface (optional: 1 interface) with a 1- or 4-bit SD bus for use with SD memory or SDIO • MMCIF with 1-, 4-, or 8-bit transfer bus width ■ External address space • Buses for full-speed data transfer (max. operating frequency of 60 MHz) • 8 CS areas • 8-, 16-, or 32-bit bus space is selectable per area • Independent SDRAM area (128 Mbytes) ■ Up to 29 extended-function timers • 16-bit TPUa, MTU3a, and GPTA: input capture, output compare, PWM waveform output • 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 channels) ■ 12-bit A/D converter • Two 12-bit units (8 channels for unit 0; 21 channels for unit 1) • Self diagnosis • Detection of analog input disconnection ■ 12-bit D/A converter: 2 channels • On-chip operational amplifier output or direct input selectable ■ Temperature sensor for measuring temperature within the chip ■ Encryption (optional) • AES (key lengths: 128, 192, and 256 bits) • DES (key lengths: 56 bits (DES); 3 × 56 bits (T-DES)) • SHA (SHA-1 (128), SHA-2 (224 or 256), HMAC (160, 224, or 256)) ■ Up to 127 pins for general I/O ports • 5-V tolerance, open drain, input pull-up, switchable driving ability ■ Operating temp. range • –40°C to +85°C PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch PLBG0176GA-A 13 × 13mm, 0.8-mm pitch 240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface R01DS0249EJ0110 Rev.1.10 Dec 28, 2017 Features

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R01DS0249EJ0110 Rev.1.10 Page 2 of 232 Dec 28, 2017 RX71M Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/9) Classification Module/Function Description CPU CPU • Maximum operating frequency: 240 MHz • 32-bit RX CPU (RXv2) • Minimum instruction execution time: One instruction per state (cycle of the system clock) • Address space: 4-Gbyte linear • Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers • Basic instructions: 75 • Floating-point instructions: 11 • DSP instructions: 23 • Addressing modes: 11 • Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian • On-chip 32-bit multiplier: 32 × 32 → 64 bits • On-chip divider: 32 / 32 → 32 bits • Barrel shifter: 32 bits FPU • Single precision (32-bit) floating point • Data types and floating-point exceptions in conformance with the IEEE754 standard Memory Code flash memory • Capacity: 2 Mbytes, 2.5 Mbytes, 3 Mbytes, 4 Mbytes • No-wait access at up to 120 MHz, single wait access at frequencies above 120 MHz • No-wait access to instructions and operands when the AFU is hit in operation at 240 MHz • On-board programming: Four types • Off-board programming (parallel programmer mode) • The trusted memory (TM) function protects against the reading of programs from blocks 8 and 9. Data flash memory • Capacity: 64 Kbytes • Programming/erasing: 100,000 times RAM • Capacity: 512 Kbytes • 0000 0000h to 0003 FFFFh (256 Kbytes): 240 MHz No-wait access 0004 0000h to 0007 FFFFh (256 Kbytes): No-wait access at up to 120 MHz, single wait access at frequencies above 120 MHz • SED (single error detection) Unique ID • 12-byte length ID unique to the device RAM with ECC (ECCRAM) • Capacity: 32 Kbytes • Single wait access at up to 120 MHz, two wait accesses for reading and three wait accesses for writing at frequencies above 120 MHz • SEC-DED (single error correction/double error detection) Standby RAM • Capacity: 8 Kbytes • Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access

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R01DS0249EJ0110 Rev.1.10 Page 3 of 232 Dec 28, 2017 RX71M Group 1. Overview Operating modes • Operating modes by the mode-setting pins at the time of release from the reset state Single-chip mode Boot mode (for the SCI interface) Boot mode (for the USB interface) User boot mode • Selection of operating mode by register setting Single-chip mode, user boot mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode • Endian selectable Clock Clock generation circuit • Main clock oscillator, sub clock oscillator, low-speed/high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator • The peripheral module clocks can be set to frequencies above that of the system clock. • Main-clock oscillation stoppage detection • Separate frequency-division and multiplication settings for the system clock (ICLK), peripheral module clocks (PCLKA, PCLKB, PCLKC, PCLKD), flash-IF clock (FCLK) and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): Up to 240 MHz Peripheral modules of MTU3, GPT, RSPI, SCIFA, USBA, ETHERC, EPTPC, EDMAC, and AES run in synchronization with PCLKA, which operates at up to 120 MHz. Other peripheral modules run in synchronization with PCLKB: Up to 60 MHz ADCLK in the SD12AD (unit 0) runs in synchronization with PCLKC: Up to 60 MHz ADCLK in the SD12AD (unit 1) runs in synchronization with PCLKD: Up to 60 MHz Flash IF run in synchronization with the flash-IF clock (FCLK): Up to 60 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): Up to 60 MHz • Multiplication is possible with using the high-speed on-chip oscillator (HOCO) as a reference clock of the PLL circuit Reset Nine types of reset • RES# pin reset: Generated when the RES# pin is driven low. • Power-on reset: Generated when the RES# pin is driven high and VCC = AVCC0 = AVCC1 rises. • Voltage-monitoring 0 reset: Generated when VCC = AVCC0 = AVCC1 falls. • Voltage-monitoring 1 reset: Generated when VCC = AVCC0 = AVCC1 falls. • Voltage-monitoring 2 reset: Generated when VCC = AVCC0 = AVCC1 falls. • Deep software standby reset: Generated in response to an interrupt to trigger release from deep software standby. • Independent watchdog timer reset: Generated when the independent watchdog timer underflows, or a refresh error occurs. • Watchdog timer reset: Generated when the watchdog timer underflows, or a refresh error occurs. • Software reset: Generated by register setting. Power-on reset If the RES# pin is at the high level when power is supplied, an internal reset is generated. After VCC = AVCC0 = AVCC1 has exceeded the voltage detection level and the specified period has elapsed, the reset is cancelled. Voltage detection circuit (LVDA) Monitors the voltage being input to the VCC = AVCC0 = AVCC1 pins and generates an internal reset or internal interrupt. • Voltage detection circuit 0 Capable of generating an internal reset The option-setting memory can be used to select enabling or disabling of the reset. Voltage detection level: Selectable from three different levels (2.94 V, 2.87 V, and 2.80 V) • Voltage detection circuits 1 and 2 Voltage detection level: Selectable from three different levels (2.99 V, 2.92 V, and 2.85 V) Digital filtering (1/2, 1/4, 1/8, and 1/16 LOCO frequency) Capable of generating an internal reset • Two types of timing are selectable for release from reset An internal interrupt can be requested. • Detection of voltage rising above and falling below thresholds is selectable. • Maskable or non-maskable interrupt is selectable Voltage detection monitoring Event linking Table 1.1 Outline of Specifications (2/9) Classification Module/Function Description

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R01DS0249EJ0110 Rev.1.10 Page 4 of 232 Dec 28, 2017 RX71M Group 1. Overview Low power consumption Low power consumption facilities • Module stop function • Four low power consumption modes Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode Battery backup function • When the voltage on the VCC pin drops, battery power from the VBATT pin is supplied to keep the real-time clock (RTC) operating. Interrupt Interrupt controller (ICUA) • Peripheral function interrupts: 298 sources • External interrupts: 16 (pins IRQ0 to IRQ15) • Software interrupts: 2 sources • Non-maskable interrupts: 7 sources • Sixteen levels specifiable for the order of priority • Method of interrupt source selection: The interrupt vectors consist of 256 vectors (128 sources are fixed. The remaining 128 vectors are selected from among the other 157 sources.) External bus extension • The external address space can be divided into eight areas (CS0 to CS7), each with independent control of access settings. Capacity of each area: 16 Mbytes (CS0 to CS7) A chip-select signal (CS0# to CS7#) can be output for each area. Each area is specifiable as an 8-, 16-, or 32-bit bus space. The data arrangement in each area is selectable as little or big endian (only for data). • SDRAM interface connectable • Bus format: Separate bus, multiplex bus • Wait control • Write buffer facility DMA DMA controller (DMACAa) • 8 channels • Three transfer modes: Normal transfer, repeat transfer, and block transfer • Request sources: Software trigger, external interrupts, and interrupt requests from peripheral functions EXDMA controller (EXDMACa) • 2 channels Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer • Single-address transfer enabled with the EDACKn signal • Request sources: Software trigger, external DMA requests (EDREQn), and interrupt requests from peripheral functions Data transfer controller (DTCa) • Three transfer modes: Normal transfer, repeat transfer, and block transfer • Request sources: External interrupts and interrupt requests from peripheral functions I/O ports Programmable I/O ports • I/O ports for the 177-pin TFLGA, 176-pin LFBGA, and 176-pin LFQFP I/O pins: 127 Input pin: 1 Pull-up resistors: 127 Open-drain outputs: 127 5-V tolerance: 19 • I/O ports for the 145-pin TFLGA and 144-pin LFQFP I/O pins: 111 Input pin: 1 Pull-up resistors: 111 Open-drain outputs: 111 5-V tolerance: 18 • I/O ports for the 100-pin TFLGA and 100-pin LFQFP I/O pins: 78 Input pin: 1 Pull-up resistors: 78 Open-drain outputs: 78 5-V tolerance: 17 Table 1.1 Outline of Specifications (3/9) Classification Module/Function Description

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R01DS0249EJ0110 Rev.1.10 Page 5 of 232 Dec 28, 2017 RX71M Group 1. Overview Event link controller (ELC) • Event signals such as interrupt request signals can be interlinked with the operation of functions such as timer counting, eliminating the need for intervention by the CPU to control the functions. • 119 internal event signals can be freely combined for interlinked operation with connected functions. • Event signals from peripheral modules can be used to change the states of output pins (of ports B and E). • Changes in the states of pins (of ports B and E) being used as inputs can be interlinked with the operation of peripheral modules. Timers 16-bit timer pulse unit (TPUa) • (16 bits × 6 channels) × 1 unit • Maximum of 16 pulse-input/output possible • Select from among seven or eight counter-input clock signals for each channel • Input capture/output compare function • Output of PWM waveforms in up to 15 phases in PWM mode • Support for buffered operation, phase-counting mode (two phase encoder input) and cascade-connected operation (32 bits × 2 channels) depending on the channel. • PPG output trigger can be generated • Capable of generating conversion start triggers for the A/D converters • Digital filtering of signals from the input capture pins • Event linking by the ELC Multifunction timer pulse unit (MTU3a) • 9 channels (16 bits × 8 channels, 32 bits × 1 channel) • Maximum of 28 pulse-input/output and 3 pulse-input possible • Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/ 2, PCLKA/4, PCLKA/8, PCLKA/16, PCLKA/32, PCLKA/64, PCLKA/256, PCLKA/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A) 14 of the signals are available for channel 0, 12 are available for channel 2, 11 are available for channels 1, 3, 4, 6 to 8, and 10 are available for channel 5. • Input capture function • 39 output compare/input capture registers • Counter clear operation (synchronous clearing by compare match/input capture) • Simultaneous writing to multiple timer counters (TCNT) • Simultaneous register input/output by synchronous counter operation • Buffered operation • Support for cascade-connected operation • 43 interrupt sources • Automatic transfer of register data • Pulse output mode Toggle/PWM/complementary PWM/reset-synchronized PWM • Complementary PWM output mode Outputs non-overlapping waveforms for controlling 3-phase inverters Automatic specification of dead times PWM duty cycle: Selectable as any value from 0% to 100% Delay can be applied to requests for A/D conversion. Non-generation of interrupt requests at peak or trough values of counters can be selected. Double buffer configuration • Reset synchronous PWM mode Three phases of positive and negative PWM waveforms can be output with desired duty cycles. • Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2) • Counter functionality for dead-time compensation • Generation of triggers for A/D converter conversion • A/D converter start triggers can be skipped • Digital filter function for signals on the input capture and external counter clock pins • PPG output trigger can be generated • Event linking by the ELC Port output enable 3 (POE3a) • Control of the high-impedance state of the MTU3/GPT's waveform output pins • 5 pins for input from signal sources: POE0, POE4, POE8, POE10, POE11 • Initiation on detection of short-circuited outputs (detection of simultaneous PWM output to the active level) • Initiation by oscillation-stoppage detection or software • Additional programming of output control target pins is enabled Table 1.1 Outline of Specifications (4/9) Classification Module/Function Description

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R01DS0249EJ0110 Rev.1.10 Page 6 of 232 Dec 28, 2017 RX71M Group 1. Overview Timers General PWM timer (GPTA) • 16 bits × 4 channels • Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels • Four clock sources independently selectable for all channels (PCLKA/1, PCLKA/4, PCLKA/8, PCLKA/16) • 2 input/output pins per channel • 2 output compare/input capture registers per channel • For the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. • In output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically PWM waveforms. • Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) • Synchronizable operation of the several counters • Modes of synchronized operation (synchronized, or displaced by desired times for phase shifting) • Generation of dead times in PWM operation • Through combination of three counters, generation of automatic three-phase PWM waveforms incorporating dead times • Starting, clearing, and stopping counters in response to external or internal triggers • Internal trigger sources: output of the internal comparator detection, software, and compare-match • Digital filter function for signals on the input capture and external trigger pins • Event linking by the ELC Programmable pulse generator (PPG) • (4 bits × 4 groups) × 2 units • Pulse output with the MTU or TPU output as a trigger • Maximum of 32 pulse-output possible 8-bit timers (TMRb) • (8 bits × 2 channels) × 2 units • Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal • Capable of output of pulse trains with desired duty cycles or of PWM signals • The 2 channels of each unit can be cascaded to create a 16-bit timer • Generation of triggers for A/D converter conversion • Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12 • Event linking by the ELC Compare match timer (CMT) • (16 bits × 2 channels) × 2 units • Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) • Event linking by the ELC Compare match timer W (CMTW) • (32 bits × 1 channel) × 2 units • Compare-match, input-capture input, and output-comparison output are available. • Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) • Interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. • Event linking by the ELC Realtime clock (RTCd) • Clock sources: Main clock, sub clock • Selection of the 32-bit binary count in time count/second unit possible • Clock and calendar functions • Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt • Battery backup operation • Time-capture facility for three values • Event linking by the ELC Watchdog timer (WDTA) • 14 bits × 1 channel • Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128, PCLKB/512, PCLKB/2048, PCLKB/8192) Table 1.1 Outline of Specifications (5/9) Classification Module/Function Description

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R01DS0249EJ0110 Rev.1.10 Page 7 of 232 Dec 28, 2017 RX71M Group 1. Overview Timers Independent watchdog timer (IWDTa) • 14 bits × 1 channel • Counter-input clock: IWDT-dedicated on-chip oscillator • Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 • Window function: The positions where the window starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled). • Event linking by the ELC Communication function Ethernet controller (ETHERC) • 2 channels • Input and output of Ethernet/IEEE 802.3 frames • Transfer at 10 or 100 Mbps • Full- and half-duplex modes • MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as defined in IEEE 802.3u • Detection of Magic PacketsTM*1 or output of a “wake-on-LAN” signal (WOL) • Compliance with flow control as defined in IEEE 802.3x standards • Filtering of multicast frames • Direct transfer of frames between two channels by cut-through PTP controller for Ethernet controller (EPTPCa) • A block compatible with the IEEE 1588 standard is connected to the Ethernet controller (ETHERC). • Matching with a time stamp can start counting by MTU3 and the GPT. DMA controller for Ethernet controller (EDMACa) • 3 channels (the round-robin method determines the priority of the channels) 2 channels for ETHERC; 1 channel for EPTPC • Alleviation of CPU load by the descriptor control method • Transmission FIFO: 2 Kbytes; Reception FIFO: 4 Kbytes USB 2.0 FS host/ function module (USBb) • Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS • One port • Compliance with the USB 2.0 specification • Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only) • Self-power mode and bus power are selectable • OTG (On the Go) operation is possible (low-speed is not supported) • Incorporates 2 Kbytes of RAM as a transfer buffer • External pull-up and pull-down resistors are not required USB 2.0 HS host/ function module with battery charging (USBAa) • Includes a UDC (USB Device Controller) and transceiver for USB 2.0 HS • One port (only in 177-/176-pin devices) • Compliance with the USB 2.0 specification • Transfer rate: High speed (480 Mbps), full speed (12 Mbps), low speed (1.5 Mbps) (host only) • Self-power mode and bus power are selectable • OTG (On the Go) operation is possible (low-speed is not supported) • Incorporates 8.5 Kbytes of RAM as a transfer buffer • External pull-up and pull-down resistors are not required Serial communications interfaces (SCIg, SCIh) • 9 channels (SCIg: 8 channels + SCIh: 1 channel) • SCIg Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12 Start-bit detection: Level or edge detection is selectable. Simple I2C Simple SPI 9-bit transfer mode Bit rate modulation Double-speed mode Event linking by the ELC (supported by SCI5 only) • SCIh (The following functions are added to SCIg) Supports the serial communications protocol, which contains the start frame and information frame Supports the LIN format Table 1.1 Outline of Specifications (6/9) Classification Module/Function Description

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R01DS0249EJ0110 Rev.1.10 Page 8 of 232 Dec 28, 2017 RX71M Group 1. Overview Communication function Serial communications interface with FIFO (SCIFA) • 4 channels • Methods of transfer: Asynchronous and clock synchronous • Desired bit rates can be selected from the internal baud rate generators. • LSB or MSB first is selectable. • Both the transmission and reception sections are equipped with 16-byte FIFO buffers, allowing continuous transmission and reception. • Bit rate modulation • Double-speed mode I2C bus interface (RIICa) • 2 channels (only channel 0 can be used in fast-mode plus) Communication formats I2C bus format/SMBus format Supports the multi-master Max. transfer rate: 1 Mbps (channel 0) • Event linking by the ELC CAN module (CAN) • 3 channels • Compliance with the ISO11898-1 specification (standard frame and extended frame) • 32 mailboxes per channel Serial peripheral interface (RSPIa) • 2 channels • RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave • Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) • Buffered structure Double buffers for both transmission and reception • RSPCK can be stopped with the receive buffer full for master reception. • Event linking by the ELC Quad serial peripheral interface (QSPI) • 1 channel • Connectable with serial flash memory equipped with multiple input and output lines (i.e. for single, dual, or quad operation) • Programmable bit length and selectable active sense and phase of the clock signal • Sequential execution of transfer • LSB or MSB first is selectable. Serial sound interface (SSI) • 2 channels • Full-duplex transfer is possible (only on channel 0). • Support for multiple audio formats • Support for master or slave operation • Bit clock frequency is selectable from four different types (16 fs, 32 fs, 48 fs, and 64 fs). • Support for 8-/16-/18-/20-/22-/24 bit data formats • Internal 8-stage FIFO for transmission and reception • Stopping SSIWS when data transfer is stopped is selectable. Sampling rate converter (SRC) • 1 channel • Data formats: 32-bit stereo (16 bits for the left, 16 bits for the right) and 16-bit monaural. • Input sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz • Output sampling rates: 32, 44.1, 48, 8*2 or 16 kHz*2 SD host interface (SDHI)*4 • 1 channel • Transfer speed: Supports high-speed mode (15 MB/s) and default speed mode (10 MB/s) • One interface for SD memory and I/O cards (supporting 1- and 4-bit SD buses) • SD specifications Part 1: Physical Layer Specification Ver. 3.01 compliant (DDR not supported) Part E1: SDIO Specification Ver. 3.00 • Error checking: CRC7 for commands and CRC16 for data • Interrupt requests: Card access interrupt, SDIO access interrupt, card detection interrupt • DMA transfer requests: SD_BUF write and SD_BUF read • Support for card detection and write protection Table 1.1 Outline of Specifications (7/9) Classification Module/Function Description

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R01DS0249EJ0110 Rev.1.10 Page 9 of 232 Dec 28, 2017 RX71M Group 1. Overview MMC host interface (MMCIF) • 1 channel • Transfer speed: Supports high-speed mode (30 MB/s) and Backward-compatible mode (25 MB/s) • Compliant with JEDEC STANDARD JESD84-A441 (DDR is not supported) • Interface for Multimedia Cards (MMCs) • Device buses: Support for 1-, 4-, and 8-bit MMC buses • Interrupt requests: Card detection interrupt, error/timeout interrupt, normal operation interrupt • DMA transfer requests: CE_DATA write and CE_DATA read • Support for card detection, boot operation, high priority interrupt (HPI) Parallel data capture unit (PDC) • 1 channel • Acquisition of synchronization through external 8-bit horizontal and vertical synchronization signals • Setting of the image size when clipping of the output for a one-frame image is required 12-bit A/D converter (S12ADC) • 12 bits × 2 units (unit 0: 8 channels; unit 1: 21 channels) • 12-bit resolution (switchable between 8, 10, and 12 bits) • Conversion time 0.48 μs per channel (for 12-bit conversion) 0.45 μs per channel (for 10-bit conversion) 0.42 μs per channel (for 8-bit conversion) • Operating mode Scan mode (single scan mode, continuous scan mode, or group scan mode) Group A priority control (only for group scan mode) • Sample-and-hold function Common sample-and-hold circuit included In addition, channel-dedicated sample-and-hold function (3ch: in unit 0 only) included • Sampling variable Sampling time can be set up for each channel. • Digital comparison Method: Comparison to detect voltages above or below thresholds and window comparison Measurement: Comparison of two results of conversion or comparison of a value in the comparison register and a result of conversion • Self-diagnostic function The self-diagnostic function internally generates three analog input voltages (unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: AVSS1, AVCC1 × 1/2, AVCC1) • Double trigger mode (A/D conversion data duplicated) • Detection of analog input disconnection • Three ways to start A/D conversion Software trigger, timer (MTU3, GPT, TMR, TPU) trigger, external trigger • Event linking by the ELC 12-bit D/A converter (R12DA) • 2 channels • 12-bit resolution • Output voltage: 0.2 V to AVCC1 – 0.2 V (amplifier output), 0 V to AVCC1 (direct output) • Output via an amplifier or direct output can be selected. • Event linking by the ELC Temperature sensor • 1 channel • Relative precision: ±1°C • The voltage of the temperature is converted into a digital value by the 12-bit A/D converter (unit 1). Safety Memory protection unit (MPU) • Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to FFFF FFFFh. • Minimum protection unit: 16 bytes • Reading from, writing to, and enabling the execution access can be specified for each area. • An address exception occurs when the detected access is not in the permitted area. Trusted Memory (TM) Function • Protects against the reading of programs from blocks 8 and 9 of the code flash memory • Instruction fetching by the CPU is the only form of access to these areas when the TM function is enabled. Register write protection function • Protects important registers from being overwritten for in case a program runs out of control. Table 1.1 Outline of Specifications (8/9) Classification Module/Function Description

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