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SI3410DV-T1-GE3

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SI3410DV-T1-GE3

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Part Number SI3410DV-T1-GE3
Manufacturer Vishay Siliconix
Description MOSFET N-CH 30V 8A 6-TSOP
Datasheet SI3410DV-T1-GE3 Datasheet
Package SOT-23-6 Thin, TSOT-23-6
In Stock 100,200 piece(s)
Unit Price $ 0.3350 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 2 - Jun 7 (Choose Expedited Shipping)
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Part Number # SI3410DV-T1-GE3 (Transistors - FETs, MOSFETs - Single) is manufactured by Vishay Siliconix and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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SI3410DV-T1-GE3 Specifications

ManufacturerVishay Siliconix
CategoryDiscrete Semiconductor Products - Transistors - FETs, MOSFETs - Single
Datasheet SI3410DV-T1-GE3Datasheet
PackageSOT-23-6 Thin, TSOT-23-6
SeriesTrenchFET?
FET TypeN-Channel
TechnologyMOSFET (Metal Oxide)
Drain to Source Voltage (Vdss)30V
Current - Continuous Drain (Id) @ 25°C8A (Tc)
Drive Voltage (Max Rds On, Min Rds On)4.5V, 10V
Vgs(th) (Max) @ Id3V @ 250µA
Gate Charge (Qg) (Max) @ Vgs33nC @ 10V
Input Capacitance (Ciss) (Max) @ Vds1295pF @ 15V
Vgs (Max)��20V
FET Feature-
Power Dissipation (Max)2W (Ta), 4.1W (Tc)
Rds On (Max) @ Id, Vgs19.5 mOhm @ 5A, 10V
Operating Temperature-55°C ~ 150°C (TJ)
Mounting TypeSurface Mount
Supplier Device Package6-TSOP
Package / CaseSOT-23-6 Thin, TSOT-23-6

SI3410DV-T1-GE3 Datasheet

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Page 2

Vishay Siliconix Si3410DV Document Number: 69254 S09-2110-Rev. B, 12-Oct-09 www.vishay.com 1 N-Channel 30-V (D-S) MOSFET FEATURES • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • Notebook Load Switch • Low Current dc-to-dc PRODUCT SUMMARY VDS (V) RDS(on) (Ω) ID (A) a Qg (Typ.) 30 0.0195 at VGS = 10 V 8 9.2 nC 0.023 at VGS = 4.5 V 8 Notes: a. Package Limited. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under Steady State conditions is 110 °C/W. ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol Limit Unit Drain-Source Voltage VDS 30 V Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C) TC = 25 °C ID 8a A TC = 70 °C 8 a TA = 25 °C 7.5 b,c TA = 70 °C 5.9 b,c Pulsed Drain Current IDM 30 Continuous Source-Drain Diode Current TC = 25 °C IS 2.7 TA = 25 °C 1.7 b,c Maximum Power Dissipation TC = 25 °C PD 4.1 W TC = 70 °C 2.6 TA = 25 °C 2 b,c TA = 70 °C 1.25 b,c Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambientb, d t ≤ 5 s RthJA 45 62.5 °C/W Maximum Junction-to-Foot Steady State RthJF 25 30 Marking Code AM XXX Lot Traceability and Date Code Part # Code Ordering Information: Si3410DV-T1-E3 (Lead (Pb)-free) Si3410DV-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET G D S TSOP-6 Top View 6 4 1 2 3 5 3 mm 2.85 mm D D D D S G (1, 2, 5, 6) (3) (4)

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www.vishay.com 2 Document Number: 69254 S09-2110-Rev. B, 12-Oct-09 Vishay Siliconix Si3410DV Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 30 V VDS Temperature Coefficient ΔVDS/TJ ID = 250 µA 33 mV/°C VGS(th) Temperature Coefficient ΔVGS(th)/TJ - 6.2 Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1 3 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 1 µA VDS = 30 V, VGS = 0 V, TJ = 55 °C 10 On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 20 A Drain-Source On-State Resistancea RDS(on) VGS = 10 V, ID = 5 A 0.016 0.0195 Ω VGS = 4.5 V, ID = 4 A 0.019 0.023 Forward Transconductancea gfs VDS = 10 V, ID = 5 A 24 S Dynamicb Input Capacitance Ciss VDS = 15 V, VGS = 0 V, f = 1 MHz 1295 pFOutput Capacitance Coss 170 Reverse Transfer Capacitance Crss 72 Total Gate Charge Qg VDS = 15 V, VGS = 10 V, ID = 5 A 21.8 33 nC VDS = 15 V, VGS = 4.5 V, ID = 5 A 9.2 14 Gate-Source Charge Qgs 3.8 Gate-Drain Charge Qgd 2.5 Gate Resistance Rg f = 1 MHz 2.4 Ω Turn-On Delay Time td(on) VDD = 15 V, RL = 3 Ω ID ≅ 5 A, VGEN = 4.5 V, Rg = 1 Ω 21 40 ns Rise Time tr 14 25 Turn-Off DelayTime td(off) 20 40 Fall Time tf 9 18 Turn-On Delay Time td(on) VDD = 15 V, RL = 3 Ω ID ≅ 5 A, VGEN = 10 V, Rg = 1 Ω 10 20 Rise Time tr 8 16 Turn-Off DelayTime td(off) 21 35 Fall Time tf 8 16 Drain-Source Body Diode Characteristics Continous Source-Drain Diode Current IS TC = 25 °C 2.7 A Pulse Diode Forward Current ISM 30 Body Diode Voltage VSD IS = 1.7 A, VGS = 0 V 0.77 1.2 V Body Diode Reverse Recovery Time trr IF = 3 A, dI/dt = 100 A/µs, TJ = 25 °C 21 40 ns Body Diode Reverse Recovery Charge Qrr 15 30 nC Reverse Recovery Fall Time ta 13 ns Reverse Recovery Rise Time tb 8

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Document Number: 69254 S09-2110-Rev. B, 12-Oct-09 www.vishay.com 3 Vishay Siliconix Si3410DV TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Output Characteristics On-Resistance vs. Drain Current and Gate Voltage Gate Charge 0 6 12 18 24 30 0.0 0.5 1.0 1.5 2.0 2.5 VGS = 10 V thru 4 V VDS - Drain-to-Source Voltage (V) - D ra in C u rr e n t (A ) I D VGS = 3 V 0.010 0.014 0.018 0.022 0.026 0.030 0 6 12 18 24 30 - O n -R e s is ta n c e ( Ω ) R D S (o n ) ID - Drain Current (A) VGS = 4.5 V VGS = 10 V ID = 5 A 0 2 4 6 8 10 0 5 10 15 20 25 - G a te -t o -S o u rc e V o lt a g e ( V ) Qg - Total Gate Charge (nC) V G S VDS = 10 V VDS = 20 V VDS = 15 V Transfer Characteristics Capacitance On-Resistance vs. Junction Temperature 0.0 0.3 0.6 0.9 1.2 1.5 0 1 2 3 4 5 VGS - Gate-to-Source Voltage (V) - D ra in C u rr e n t (A ) I D TC = 25 °C TC = 125 °C TC = - 55 °C Crss 0 320 640 960 1280 1600 0 6 12 18 24 30 Coss Ciss VDS - Drain-to-Source Voltage (V) C - C a p a c it a n c e ( p F ) - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) R D S (o n ) - O n -R e s is ta n c e (N o rm a liz e d ) 0.7 0.9 1.1 1.3 1.5 1.7 VGS = 4.5 V VGS = 10 V ID = 5 A

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www.vishay.com 4 Document Number: 69254 S09-2110-Rev. B, 12-Oct-09 Vishay Siliconix Si3410DV TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Source-Drain Diode Forward Voltage Threshold Voltage 0.001 0.01 0.1 1 10 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VSD - Source-to-Drain Voltage (V) - S o u rc e C u rr e n t (A ) I S TJ = 25 °C TJ = 150 °C - 0.9 - 0.6 - 0.3 0 0.3 0.6 - 50 - 25 0 25 50 75 100 125 150 V a ri a n c e ( V ) V G S (t h ) TJ - Temperature (°C) ID = 250 µA ID = 5 mA On-Resistance vs. Gate-to-Source Temperature Single Pulse Power, Junction-to-Ambient 0 0.02 0.04 0.06 0.08 0.10 0 1 2 3 4 5 6 7 8 9 10 - O n -R e s is ta n c e ( Ω ) R D S (o n ) VGS - Gate-to-Source Voltage (V) TA = 125 °C TA = 25 °C 0 12 24 36 48 60 P o w e r (W ) Time (s) 1 100.10.010.001 Safe Operating Area, Junction-to-Ambient 0.001 0.01 0.1 1 10 100 - D ra in C u rr e n t (A ) I D 0.1 1 10 100 TA = 25 °C Single Pulse 1 s, 10 s 10 ms 100 ms DC Limited by R *DS(on) VDS - Drain-to-Source Voltage (V) * VGS minimum VGS at which RDS(on) is specified 1 ms

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Document Number: 69254 S09-2110-Rev. B, 12-Oct-09 www.vishay.com 5 Vishay Siliconix Si3410DV TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Current Derating* 0 2 5 7 10 12 0 25 50 75 100 125 150 TC - Case Temperature (°C) I D - D ra in C u rr e n t (A ) Package Limited Power Derating, Junction-to-Foot 0 1 2 3 4 5 0 25 50 75 100 125 150 TC - Case Temperature (°C) P o w e r (W ) Power Derating, Junction-to-Ambient 0.0 0.3 0.6 0.9 1.2 1.5 0 25 50 75 100 125 150 TA - Ambient Temperature (°C) P o w e r (W )

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www.vishay.com 6 Document Number: 69254 S09-2110-Rev. B, 12-Oct-09 Vishay Siliconix Si3410DV TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69254. Normalized Thermal Transient Impedance, Junction-to-Ambient 0.001 0.1 1 10-3 10-2 000101110-110-4 100 0.2 0.1 0.05 0.02 Square Wave Pulse Duration (s) N o rm a liz e d E ff e c ti v e T ra n s ie n t T h e rm a l Im p e d a n c e Single Pulse t1 t2 Notes: PDM 1. Duty Cycle, D = 2. Per Unit Base = RthJA = 110 °C/W 3. TJM - TA = PDMZthJA (t) t1 t2 4. Surface Mounted Duty Cycle = 0.5 0.01 Normalized Thermal Transient Impedance, Junction-to-Foot 10-3 10-2 01110-110-4 0.2 0.1 Duty Cycle = 0.5 Square Wave Pulse Duration (s) N o rm a liz e d E ff e c ti v e T ra n s ie n t T h e rm a l Im p e d a n c e 1 0.1 0.01 0.05 0.02 Single Pulse

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Vishay Siliconix Package Information Document Number: 71200 18-Dec-06 www.vishay.com 1 1 2 3 Gauge Plane L 5 4 R R C 0.15 M B A b C 0.08 0.17 Ref Seating Plane -C- Seating Plane A 1 A 2 A -A - D -B - E 1 E L 2 (L 1 ) c 4x 1 4x 1 e e1 1 2 3 6 5 4 C 0.15 M B A b -B - E 1 E e e1 5-LEAD TSOP 6-LEAD TSOP TSOP: 5/6−LEAD JEDEC Part Number: MO-193C MILLIMETERS INCHES Dim Min Nom Max Min Nom Max A 0.91 - 1.10 0.036 - 0.043 A 1 0.01 - 0.10 0.0004 - 0.004 A 2 0.90 - 1.00 0.035 0.038 0.039 b 0.30 0.32 0.45 0.012 0.013 0.018 c 0.10 0.15 0.20 0.004 0.006 0.008 D 2.95 3.05 3.10 0.116 0.120 0.122 E 2.70 2.85 2.98 0.106 0.112 0.117 E 1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.95 BSC 0.0374 BSC e 1 1.80 1.90 2.00 0.071 0.075 0.079 L 0.32 - 0.50 0.012 - 0.020 L 1 0.60 Ref 0.024 Ref L 2 0.25 BSC 0.010 BSC R 0.10 - - 0.004 - - 0 4 8 0 4 8 1 7 Nom 7 Nom ECN: C-06593-Rev. I, 18-Dec-06 DWG: 5540

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AN823 Vishay Siliconix Document Number: 71743 27-Feb-04 www.vishay.com 1 Mounting LITTLE FOOT TSOP-6 Power MOSFETs Surface mounted power MOSFET packaging has been based on integrated circuit and small signal packages. Those packages have been modified to provide the improvements in heat transfer required by power MOSFETs. Leadframe materials and design, molding compounds, and die attach materials have been changed. What has remained the same is the footprint of the packages. The basis of the pad design for surface mounted power MOSFET is the basic footprint for the package. For the TSOP-6 package outline drawing see http://www.vishay.com/doc?71200 and see http://www.vishay.com/doc?72610 for the minimum pad footprint. In converting the footprint to the pad set for a power MOSFET, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose. FIGURE 1. Recommended Copper Spreading Footprint 0.049 1.25 0.010 0.25 0.014 0.35 0.074 1.875 0.122 3.1 0.026 0.65 0.167 4.25 0.049 1.25 Since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3. Ramp-Up Rate +6C/Second Maximum Temperature @ 155  15C 120 Seconds Maximum Temperature Above 180C 70 − 180 Seconds Maximum Temperature 240 +5/−0C Time at Maximum Temperature 20 − 40 Seconds Ramp-Down Rate +6C/Second Maximum FIGURE 2. Solder Reflow Temperature Profile

Page 10

AN823 Vishay Siliconix www.vishay.com 2 Document Number: 71743 27-Feb-04 255 − 260C 14C/s (max) 3-6C/s (max) 10 s (max) Reflow Zone Pre-Heating Zone 3C/s (max) 140 − 170C Maximum peak temperature at 240C is allowed. FIGURE 3. Solder Reflow Temperature and Time Durations 60-120 s (min) 217C 60 s (max) THERMAL PERFORMANCE A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rjc, or the junction-to-foot thermal resistance, Rjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows the thermal performance of the TSOP-6. TABLE 1. Equivalent Steady State Performance—TSOP-6 Thermal Resistance Rjf 30C/W SYSTEM AND ELECTRICAL IMPACT OF TSOP-6 In any design, one must take into account the change in MOSFET rDS(on) with temperature (Figure 4). 0.6 0.8 1.0 1.2 1.4 1.6 −50 −25 0 25 50 75 100 125 150 VGS = 4.5 V ID = 6.1 A On-Resistance vs. Junction Temperature TJ − Junction Temperature (C) FIGURE 4. Si3434DV r D S (o n) − O n- R es iis ta nc e (N or m al iz ed )

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